Field-effect transistor

 

(57) Abstract:

Created field-effect transistor having electrodes (2, 4, 5) and insulators (3) in vertically spaced layers, such that at least the electrodes (4, 5) and insulators (3) form a step (6), oriented vertically relative to the first electrode (2) or the substrate (1). In the variants of implementation in the form of a field-effect transistor with a control p-n junction (PTOP) or in the form of a field-effect transistor with a structure of metal - oxide - semiconductor (MOS transistor) electrodes (2, 5) respectively form the drain electrodes and source of the field-effect transistor, or Vice versa, and the electrode (4) forms the gate electrode of field-effect transistor, on top of layers of vertical steps (6) deposited amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material forming the active semiconductor transistor that has a direct or indirect contact with the electrode (8) shutter and forms a vertically oriented channel (9) of the transistor of the p - or n-type between the first (2) and second (5) electrodes. In the method of manufacturing the field-effect transistor of the vertical step (6) is formed through a photolithographic process, and nikaloy steps (6) carry out so, between the drain electrodes and source (2, 5) receive a vertically oriented channel transistor. In PTOP semiconductor material (8) is in direct contact with the electrode (4) of the shutter. In the MOS transistor between the gate electrode (4) and the semiconductor material (8) vertically oriented insulator (7) of the shutter. The technical result is to obtain a sufficient channel length on a smaller area. 3 S. and 14 C.p. f-crystals, 7 Il.

The invention relates to field effect transistors, respectively, to a field effect transistor with a control p-n junction and field-effect transistor with a structure of metal - oxide - semiconductor (MOS transistor) (MOSFET) having essentially vertical geometry, and field-effect transistors include a flat substrate of non-conductive material. The invention also relates to a method of manufacturing field-effect transistors of this type with essentially vertical geometry, and the transistor includes a flat substrate of non-conductive material.

Field-effect transistors, FETS (FET), in which the active semiconductor using an amorphous material, traditionally designed with horizontal geometry, for example, presented the local level equipment. Here, the drain electrode and the source electrode are separated from one another by the channel of the transistor. This channel consists of an amorphous semiconductor material. The gate electrode is defined as a horizontal layer, which is isolated from the channel by a gate insulator. The transistor effect determine or as the mode of depletion or enrichment mode, depending on the gate voltage. As an active amorphous semiconductor material in field-effect transistors of this type are used conjugated polymers, aromatic molecules and amorphous inorganic semiconductors.

For example, in Fig.1 shows a thin-film transistor active semiconductor material in the form of a layer of amorphous Si:H thickness of 10 nm (D. B. tómasson, etc. / Electronic devices. Letters, IEEE, volume 18, page 117, March 1997) (D. B. Thomasson & al., IEEE El. Dev. Lett., Vol. 18, p. 117; March 1997).

On the substrate is provided by the gate electrode, which may be metal. On top of this gate electrode is provided an insulating layer of silicon nitride (SiN), a on the insulator caused the active semiconductor material in the form of a layer of amorphous Si:H thickness of 10 nm. On the active semiconductor material are provided with electrode hundred is the lia, than the gate electrode, for example, from aluminum. Another example of the thin-film transistor of the organic material shown in Fig.1B (A. Dodabalapur and others, journal of Applied Physics Letters, volume 69, pages 4227-29, December 1996) (A. Dodabalapur & al. Arr. Phys. Lett.: Vol. 69, pp. 4227-29. December 1996). Here the active semiconductor material is an organic compound, for example, a polymer or aromatic molecules. As in the example shown in Fig.1A, on a substrate is provided, the gate electrode and above the gate electrode - insulator layer, which may be performed by depositing an oxide layer on the surface of the gate electrode, which can be accomplished by oxidation of the material on the surface of the gate electrode. On the insulating layer provided with the spaced source electrode and the drain electrode and the top electrode of the drain and source are spaced one from the other vertical side walls, both of which one end is connected with a similar vertical transverse wall. Therefore, in the plane perpendicular to the walls, channel transistor has a U-shaped cross section in which the sides of the U formed by side walls and intersecting line formed by the transverse wall. what at the forefront of an insulating material. On top of the insulating layer is a conductive layer which forms the gate electrode of the transistor. The ends of the side walls or edges of the sides of the channel of the U-shaped forms are open, and in these end sections of the channel are formed, respectively, the electrodes of the source and drain, for example, by a process of ion implantation. The main purpose of providing a thin-film transistor of this type is sufficient channel length on a smaller area, compared with that which can be obtained by traditional variants of implementation, along with the reduction of leakage current in the closed state of the transistor.

In Fig. 1B is a schematic diagram of the structure of the planar field-effect transistor with a control p-n junction (PTOP) (JFET) of the prior art, which in this embodiment is implemented as n-channel field-effect transistor with a control p-n junction (PTOP) (JFET).

The use of amorphous semiconductor material allows the implementation of different geometry transistors using a very special processing properties of amorphous materials. Therefore, the aim of the present invention is to provide a field-effect transistor thus is etall - oxide - semiconductor (MOS transistor) (MOSFET) with a vertical geometry, and more specifically to the active deposition of amorphous semiconductor material in the form of organic molecules, conjugated polymer or an amorphous inorganic semiconductor on a vertical structure, which contains and the gate electrode, and the drain electrode or the source electrode. And finally, another goal is the creation of a channel of the transistor with a vertical orientation.

Previously traditional semiconductor devices produced with a vertical geometry. The aim was a more efficient use of the chip area. Naturally, for a transistor with a vertical geometry requires less area than transistor with horizontal geometry.

For example, from U.S. patent 5563077 (G. K. Ho) (N.With. In) famous thin-film transistor with a vertical channel in which the channel is formed of two spaced one relative to the other vertical side walls, of which one end is connected with a similar vertical end wall. Therefore, in the plane perpendicular to the walls, channel transistor has a U-formation is echnol wall. The walls may be designed in such a way that they are on an appropriate substrate and fully covered by a layer of an insulating material. On top of the insulating layer is a conductive layer which forms the gate electrode of the transistor. The ends of the side walls or the end of the channel of the U-shaped forms are open, and in these end sections of the channel are formed, respectively, the electrodes of the source and drain, for example, by a process of ion implantation. The main purpose of creating thin-film transistor of this type is sufficient channel length on a smaller area, compared with that which can be obtained by traditional variants of implementation, along with the reduction of leakage current when the transistor is in the closed state.

In accordance with the invention, the above objectives and other advantages reached by means of field-effect transistor with a control p-n junction (PTOP) (JFET), characterized in that on the substrate to provide a conductor layer containing the first electrode, while on top of the first electrode to form a layer of an insulating material, which forms a first insulator that on top of the first insulator to form a layer of providesyou of an insulating material, which forms a second insulator that on top of the second insulator create a layer of conductive material, which forms the third electrode, and the above first and third electrodes are formed, respectively, the electrodes of the drain and source of the transistor, or Vice versa, and the second electrode is an electrode of the transistor that at least the specified second and said third electrodes and said first and second insulators with the corresponding layers in a multilayer structure forming step, oriented vertically with respect to the specified first electrode and/or the substrate, and that on top of the open part of the first electrode, the specified second electrode and the third electrode is a semiconductor material forming the active semiconductor transistor, and a specified active semiconductor has a direct contact with the gate electrode and forms an essentially vertically oriented channel of the transistor between the specified first and the specified third electrodes; and through the field-effect transistor with a structure of metal - oxide - semiconductor (MOS transistor) (MOSFET), wherein the substrate obespechivayuschego material, which forms a first insulator that on top of the first insulator create a layer of conductive material, which forms the second electrode, which is on top of the second electrode provide an additional layer of insulating material, which forms the second insulator that on top of the second insulator create a layer of conductive material, which forms the third electrode, and the above first and third electrodes provide, respectively, the electrodes of the drain and source of the transistor, or Vice versa, and the second electrode forms an electrode of the transistor, that at least the specified second and said third electrodes and said first and second insulators with the corresponding layers in a multilayer structure forming step, oriented vertically with respect to the specified first electrode and/or the substrate, which is over the specified second electrode and over a specified vertical steps provide a vertical layer of an insulating material that forms the gate insulator, and that on top of the open part of the first electrode, the specified vertical steps with the specified gate insulator and the third electrode applied poluprovodn the society, a vertically oriented channel of the transistor between the specified first and the specified third electrodes.

In addition, according to the invention, the above objectives and advantages reached by means of the method of manufacturing the field-effect transistor, characterized in that the method includes the following operations on the specified substrate is applied to the conductor layer, forming a first electrode; the first electrode through a photolithographic process to form a step consisting of photoresist and located vertically with respect to the specified first electrode and/or the substrate; on top of the specified layer of the conductor and the specified photoresist, forming a vertical step, are, respectively, the first insulator, the conductor that forms the second electrode, the second insulator and the conductive material forming the third electrode, in a multilayer structure; the specified multi-layered structure over the specified photoresist and the photoresist is removed by the method of inverse lithography, whereby the remaining structure of insulators, electrodes provided on the first electrode forming step, oriented vertically with respect to the specified first electrode is the range of active amorphous semiconductor material so as semiconductor material in contact with a first electrode and the third electrode, forming, respectively, the electrodes of the drain or source of the field-effect transistor, and Vice versa, and the second electrode, forming a gate electrode field-effect transistor, thus forming a vertical channel transistor.

In the case when the field-effect transistor is a field effect transistor metal - oxide - semiconductor (MOS field-effect transistor), the advantage is that the insulating material is applied on the vertical step in the form of a vertical layer that is provided over the second electrode and forms an insulator gate field effect transistor, and the application is performed after the deletion of such a multilayer structure, and the photoresist, but before applying soluble active amorphous semiconductor material.

According to the invention, the advantage is that as the active semiconductor material can be used amorphous inorganic or organic semiconductor material, but it need not be amorphous semiconductor mateh or organic semiconductor materials.

Additional characteristics and advantages will become apparent from the remaining dependent claims appended claims.

Now will be described more detailed description of the invention with reference to the drawings, in which:

In Fig.1A shows the above-mentioned example of the prior art.

In Fig. 1B shows another of the above-mentioned example of the prior art.

In Fig.1B shows an example of a planar field-effect transistor with a control p-n junction according to the prior art.

In Fig.2 shows the preferred implementation of the field-effect transistor with a control p-n junction according to the invention.

In Fig. 3 shows the preferred implementation of MOS transistor (MOSFET) according to the invention.

In Fig. 4A - 4D shows the different stages of the process in the embodiment of the method according to the invention, whereby carry out the implementation of the field-effect transistor in the form of a field-effect transistor with a control p-n junction, and

In Fig. 5A - 5B illustrates additional steps of the process for the implementation of the MOS transistor according to the invention.

In Fig.2 shows variou made by thin-film technology, more detailed explanation will be given below. On the substrate 1 to provide layer 2 of conductive material that forms the first electrode of the transistor. This layer is deposited insulating material 3A, forming the first insulator and the first insulator 3A caused additional conductive material 4, for example, metal, which forms the second electrode 4 of the transistor. On the second electrode 4 deposited insulating material 3b, which forms the second insulator of the transistor, and on top of the second insulator 3b create a layer 5 of conductive material forming the third electrode of the transistor.

In a variant implementation in the form of a field-effect transistor with a control p-n junction of the first electrode 2 and the third electrode 5 are now, respectively, form the drain electrode and the source electrode of the transistor, or Vice versa. The second electrode 4 forms a gate electrode. On the first electrode 2 are the second and third electrodes 4, 5, and insulators 3A, 3b, so that they form a vertical step with respect to the first electrode 2 and the substrate 1, which in Fig.2 is marked with the number 6 links. Thus, the structure consisting of the second and third electrodes 4, 5 and the insulator 3, closes only the de 2 or the substrate 1, can be made sufficiently small.

On top of the third electrode 5, which, for example, may be a source electrode of the transistor, on top of the vertical steps 6 and outside vertical surfaces of the gate electrode 4, is contained in the vertical step 6 create a layer 8, continuing down to the first electrode 2 consisting of active semiconductor material, which may be an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material. The gate electrode 2 and the semiconductor material 8 now form a p-n junction. Essentially, the vertical channel transistor 9 in the active semiconductor material 8 determine or as the channel is p-type or n-type channel, and it has a length from the first electrode 2 to the third electrode 5 and, in essence, is located near the p-n junction in the gate electrode 4. Implemented in this way, the structure shown in Fig.2, forms a field-effect transistor with a control p-n junction (PTOP) (JFET). Possible variant of its execution, in which the drain electrode using the first electrode 2 and the third electrode 5 is used as the source electrode, and shall be implemented by the electric field, which is applied to the channel of the transistor through the p-n junction.

In Fig.3 shows a variant implementation of MOS transistor (MOSFET) according to the invention. It is completely made by thin-film technology, for a more detailed explanation of which will be described below. On the substrate 1 to provide layer 2 of conductive material, which forms the first electrode of the transistor. This layer is deposited insulating material 3A, forming the first insulator and the first insulator 3A caused additional conductive material, for example metal, which forms the second electrode 4 of the transistor. On the second electrode 4 deposited insulating material 3b, which forms the second insulator of the transistor, and on top of the second insulator 3b create a layer 5 of conductive material forming the third electrode of the transistor.

In a variant implementation in the form of a MOS transistor (MOSFET), the first electrode 2 and the third electrode 5 are now, respectively, form the drain electrode and the source electrode of the transistor, or Vice versa. The second electrode 4 forms a gate electrode. On the first electrode 2 are the second and third electrodes 4, 5, and insulators 3A, 3b, so that they form a vertical step Rel is the way, the structure consisting of the second and third electrodes 4, 5 and the insulator 3, covers only a portion of the substrate 1, and the horizontal length of the layers, forming a vertical step 6 on the first electrode 2 or the substrate 1 may be made sufficiently small.

On the outside vertical surface of the gate electrode 4, is contained in the vertical step 6, the applied insulating material 7, which forms the insulator gate field-effect transistor. On top of the third electrode 5, which, for example, may be a source electrode of the transistor, over a vertical step 6 create a layer, continuing down to the first electrode 2 consisting of active semiconductor material, which may be an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material. The gate electrode 4 is insulated from the active semiconductor material 8 insulator 7 of the shutter so that the injected charge is prevented. In the active semiconductor material 8 is selected, essentially, a vertical channel transistor, and it has a length from the first electrode 2 to the third electrode 5 and, in essence, is radialsystem with the structure of the metal - oxide - semiconductor (MOS field-effect transistor) (MOSFET). Possible variant of its execution, in which the drain electrode using the first electrode 2 and the third electrode 5 is used as the source electrode, and a reverse option. Depending on the gate voltage, the transistor effect or mode of depletion or enrichment mode.

It should be understood that the substrate 1 in the variants of the implementation of Fig.2 and 3 is intended to be a carrier structure of the transistor. In addition, the conductive layer 2 and the first electrode provide on the entire substrate, that is, they are not structured, but they equally can be structured and can in this case, for example, to cover part of the substrate corresponding to the portion that is covered structure with a vertical step. For example, in this case, the first electrode in the embodiment of Fig.2 may be on the same level with the surface of the vertical steps 6 and to provide a vertical step with respect to the substrate 1. This vertical step can thus, for example, to be flush with the vertical surface of the insulator 7 bolt. Of course, neobhodimymi with a vertical step relative to the substrate may be an advantage in the case, if the first electrode should have a galvanic connection with the corresponding electrodes of the other transistors in transistor circuits. For this purpose the horizontal surface of the substrate can be provided with an electrical conductor outside vertical steps.

Now, with reference to Fig.4A - 4D will be examined in more detail the method of manufacturing the field-effect transistor with a control p-n junction according to the invention using thin-film technology. The main problem associated with the fabrication of field-effect transistors with a control p-n junction shown in Fig. 2 and 3, is the formation of vertical steps in which the transistor effect will be present in its entirety. For example, there may be used the so-called method of inverse lithography, which has proved its effectiveness as a method of forming a vertical surface.

It should be understood that the various stages of the process, which is shown in Fig.4A - 4D and will be discussed below, is presented schematically and in simplified form.

As shown in Fig.4A, in the first stage of the process on a substrate 1, which itself is made of an insulating or dielectric material cause is wodnika 2 is applied to the photoresist, which impose a mask and carry out etching according to known techniques of photolithography in such a way that the first electrode 2 to form a structured photoresist layer 10 with a vertical step 11. This is shown in Fig. 4B and is the second stage of the process of the present method. In the third stage of the process shown in Fig.4B, consistently create an insulating layer 3A, which forms the first insulator, the conductor 4, which forms the second electrode of the transistor, the second insulating layer 3b, which forms the second insulator, and on top of a layer 5 of conductive material, which forms the third electrode of the transistor. Through the use of, for example, the process of vapor deposition layers 3,4,5 now cover and the open portion of the first electrode 2 and the upper part of the photoresist 10 as a horizontal multilayer coating, as is clear from Fig.4V.

Now in the fourth stage of the process for removing a layer on the top surface of the photoresist and the photoresist 10 use the method of inverse lithography. This is carried out through a process of dissolution, for example, with acetone. When the photoresist layers 10 and its top surface removed, the product after chetvertok the pout electrode 2 or the substrate 1.

Then on the fifth stage of the process on the first electrode 2, second electrode 4, a vertical step 6 and on the upper surface of the third electrode 5 is applied soluble active amorphous semiconductor material 8, as shown in Fig.4D. Thus, the active semiconductor 8 cover the layered structure as horizontally and vertically. In the case where the first electrode 2 is structured and covers only a portion of the substrate 1, for example, in such a way that it itself forms a vertical step, which is on the same level with a vertical step 6, additional problems associated with providing contact between the first electrode 2 and the active semiconductor material 8, does not occur.

In the manufacture of MOS transistor (MOSFET) using thin-film technology according to the invention, after the fourth step of the process shown in Fig.4G, apply an intermediate stage of the process shown in Fig.5A. This additional stage of the process over the second electrode 4 create an insulating layer 6 so that its surface covers vertical step 6. Now this insulating layer 7 contains a gate insulator floor is by using the first electrode 2 as the substrate. In this case, for forming the insulator 7 shutter, oriented in the vertical direction in such a way that it covers the gate electrode 4, use the operation of the vertical etching. In an alternative embodiment, the insulator 7, the shutter can also be done by creating a gate electrode 4 in the material that can be selectively oxidized or treated in some way or another so that the surface of the gate electrode to form an insulating layer. In the preferred embodiment, this is carried out by selective oxidation of the surface material of the gate electrode 4.

After creating the insulator 7 shutter on the secondary stage of the process shown in Fig.5A, on the stage of the process shown in Fig.5B, on top of the first electrode 2, an insulator 7 shutter, vertical steps 6 and the upper surface of the third electrode 5 is applied soluble active amorphous semiconductor material 8. This process step corresponds to the fifth step of the process shown in Fig.4D.

Thus, the active semiconductor material 8 covering the layered structure both horizontally and vertically. In the case where the first electrode 2 is strukturirovannykh layers, additional problems associated with providing contact between the first electrode 2 and the active semiconductor material 8, does not occur.

For the application of active amorphous semiconductor material 8 can be used methods such as sublimation in vacuum, vacuum deposition, coating, obtained by the process of centrifugation, and forming from a solution. This implies that the active amorphous semiconductor material 8 can be made in the form of various structures, which, for example, cover the gate electrode 4 with different orientation both vertically and horizontally. You should also understand that to provide a field-effect transistor of the special functions in amorphous semiconductor material can be mixed or combined different active substances. If the FET is PTOP (JFET), it may be particularly desirable to use such materials, which spontaneously form a barrier of a Schottky with a gate electrode receiving structure field-effect transistor with the barrier Schottky (MESFET).

Even though the fabrication of field-effect transistors according to the invention from Fig. 2 and 3 shows, in principle, dozowania way in partially or fully continuous processes with roll forward with the application of all layers. In this case, the process of applying this method of active semiconductor material 8 may be continuous. Accordingly, if the field-effect transistor is a MOS field-effect transistor, and the process of applying this method insulator shutter can also be continuous. When the continuous process of vertical step 6 in the preferred embodiment, is formed parallel to the direction of movement of the batch, and the application of the insulator 7 of the shutter, and the active semiconductor material may be in the form of continuous strips on the vertical step. After the final stage of the process shown in Fig.4D, or in Fig.5B, the individual transistors can be separated from the batch and arranged in the form of a discrete component.

However, there is no objection to the fact that large parts of the party of items with a large number of transistors can be formed transistor matrix, which, in turn, can be used to implement the active memory modules with a single transistor as a memory element. In this case, the transistor must be connected with a galvanic circuit by forming correspond to the Stour in the General case can be carried out in the form of two - and three-dimensional structural parts electronic integrated circuits. Possible applications of such schemes can be memory devices, processors, and so on, the Obvious advantage of using active memory component based on the transistors of the present invention is in the record mode small signal and read in large-signal mode, which, in particular, is advantageous for electrical addressing of the memory cells in the memory device of large capacity, implemented in a matrix network.

As for the process of manufacturing field-effect transistors according to the invention, as mentioned above, it can be implemented in General through the use of continuous production lines. In this case, field-effect transistors PTOP (JFET) and a MOS transistor (MOSFET) for component VLSI (very large integrated circuits) (VLSI) having a structure with a vertical geometry, it is possible to produce by way of lithography, and not only through the use of known manufacturing processes.

1. Field-effect transistor, in particular a field-effect transistor with a control p-n junction (PTOP) with essentially vertical geometry, in which the transistor contains a flat substrate (1) yey contains the first electrode, this on top of the first electrode (2) create a layer (3A) of an insulating material, which forms the first insulator, and on top of the first insulator (3A) create a layer of conductive material (4) which forms a second electrode over the second electrode (4) create an additional layer (3b) of an insulating material, which forms the second insulator, and on top of the second insulator (3b) create a layer (5) of conductive material, which forms the third electrode, and the specified first (2) and third (5) electrodes respectively form the drain electrodes and source of the transistor, or Vice versa, and the second electrode (4) forms an electrode of the transistor that at least the specified second (4) and the specified third (5) electrodes and said first (3A) and second (3b) insulators with the corresponding layers in a multilayer structure forming step (6), oriented vertically with respect to the specified first electrode (2) and/or the substrate (1), and that on top of the open part of the first electrode (2), the specified second electrode (4) and the third electrode (5) is a semiconductor material (8), forming an active semiconductor transistor, and the specified active propriatary channel (9) of the transistor between the said first (2) and the specified third (5) electrodes.

2. Field-effect transistor under item 1, characterized in that the substrate (1) create a structured first electrode (2) and form an additional intermediate step relative to the substrate (1), whereby each electrode (2, 4, 5) is essentially vertical surface with respect to the active semiconductor (8).

3. Field-effect transistor under item 1, characterized in that the choice of semiconductor material (8) is carried out on amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor materials.

4. Field-effect transistor under item 1, characterized in that the channel of the transistor (9) is defined as the vertical portion of the active semiconductor (8) between the said first (2) and the specified third (5) the electrodes and the adjacent vertical step (6), which is formed of a multilayer structure.

5. Field-effect transistor under item 1, characterized in that the semiconductor (8) and the gate electrode (4) spontaneously form a barrier of a Schottky (7).

6. Field-effect transistor under item 1, characterized in that the channel (9) of the transistor is defined as the n-type channel or the channel is p-type, located in the vertical part of the active unnatural semiconductors is RA.

7. Field-effect transistors, in particular field effect transistor metal-oxide-semiconductor (MOS field-effect transistor) with essentially vertical geometry, in which the transistor contains a flat substrate (1) made of non-conductive material, characterized in that the substrate (1) create a layer (2) of conductive material, which contains a first electrode that on top of the first electrode (2) create a layer (3A) of an insulating material, which forms a first insulator that on top of the first insulator (3A) create a layer of conductive material (4) which forms the second electrode, which is on top of the second electrode (4) create an additional layer (3b) of an insulating material, which forms a second insulator that on top of the second insulator (3b) create a layer (5) of conductive material, which forms the third electrode, and the specified first (2) and third (5) electrodes respectively form the drain electrodes and source of the transistor, or Vice versa, and the second electrode (4) forms an electrode of the transistor that at least the specified second (4) and the specified third (5) the electrodes and the specified first (3A) and second (3b) insulators with the corresponding layers in a multilayer structure is formed with the key (1), that on top of the specified second electrode (4) and at the specified vertical step (6) create a vertical layer (7) of insulating material, which forms the gate insulator, and that on top of the open part of the first electrode (2), the specified vertical steps (6) with the specified insulator (7) of the shutter and the third electrode (5) deposited semiconductor material (8) through which implemented the active semiconductor transistor and formed essentially vertically oriented channel (9) of the transistor between the said first (2) and the specified third (5) the electrodes.

8. Field-effect transistor according to p. 7, characterized in that the substrate (1) create a structured first electrode (2) and form an additional intermediate step relative to the substrate (1), whereby each electrode (2, 4, 5) is essentially vertical surface with respect to the active semiconductor (8).

9. Field-effect transistor according to p. 7, characterized in that the choice of semiconductor material (8) is carried out on amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor materials.

10. Field effect transistor (8) between the said first (2) and the specified third (5) the electrodes and the adjacent vertical step (6), formed a multi-layered structure.

11. Field-effect transistor according to p. 7, characterized in that the insulator of the shutter (7) is formed in the form of an oxide coating on a vertical surface electrode (5) of the shutter.

12. Field-effect transistor according to p. 11, characterized in that the oxide coating (7) is formed by selective oxidation of the electrode material on the electrode surface (4) of the shutter.

13. A method of manufacturing a field-effect transistor with essentially vertical geometry, in which the transistor contains a flat substrate (1) made of non-conductive material, characterized in that the method comprises the following operations: on the specified substrate (1) put a layer (2) of conductive material, which forms the first electrode, the first electrode (2) through a photolithographic process to form a step (6), consisting of photoresist (10) and located vertically with respect to the specified first electrode (2) and/or the substrate (1) on top as specified conductive layer (2) and specified photoresist (10), which forms a vertical step (6), are respectively the first insulator (3A), conductive material (4), forming the second electrode, the second insulator is th structure above the specified photoresist (10) and the photoresist is removed by the method of inverse lithography, whereby the remaining structure of insulators electrodes created on the first electrode (2), forms a step (6), oriented vertically with respect to the specified first electrode (2) and/or the substrate (1), and the first electrode (2) and at the specified vertical step (6) is applied soluble active amorphous semiconductor material so that the semiconductor material has a contact with a first electrode (2) and the third electrode (5), respectively forming the electrodes of the drain or source of the field-effect transistor, and Vice versa, and the second electrode (4) forming a gate electrode field-effect transistor, forming, thereby, a vertically oriented channel (9) of the transistor.

14. The method according to p. 13, in which the field-effect transistor is a field effect transistor metal-oxide-semiconductor (MOS field-effect transistor), wherein the insulating material is applied on the vertical step (6) in the form of a vertical layer that is located over the second electrode (5) and forms an insulator gate field effect transistor, and the application is performed after the deletion of such multilayer structures (8).

15. The method according to p. 14, characterized in that the insulator (7) of the shutter is formed in the form of an oxide coating on a vertical surface of the electrode (4) of the shutter.

16. The method according to p. 15, characterized in that the oxide coating (7) is formed by selective oxidation of the electrode material on the electrode surface (4) of the shutter.

17. The method according to p. 13, characterized in that the first electrode (2) is applied on a substrate (1) in a structured manner, and it only partially covers the latter.

 

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FIELD: technologies for making transistors.

SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.

EFFECT: ultra-short channel length of produced transistors.

11 cl, 17 dwg

FIELD: electronic engineering; high-power microwave transistors and small-scale integrated circuits built around them.

SUBSTANCE: proposed method for producing high-power microwave transistors includes formation of transistor-layout semiconductor wafer on face side, evaporation of metals, application and etching of insulators, electrolytic deposition of gold, formation of grooves on wafer face side beyond transistor layout for specifying transistor chip dimensions, thinning of semiconductor wafer, formation of grooves on wafer underside just under those on face side, formation of through holes for grounding transistor leads, formation of integrated heat sinks for transistor chips around integrated heat sink followed by dividing semiconductor wafer into transistor chips by chemical etching using integrated heat sinks of transistor chips as mask.

EFFECT: enhanced power output due to reduced thermal resistance, enhanced yield, and facilitated manufacture.

2 cl, 1 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: manufacturing method of microwave transistor with control electrode of T-shaped configuration of submicron length involves formation on the front side of semi-insulating semi-conductor plate with active layer of the specified structure of a pair of electrodes of transistor, which form ohmic contacts by means of lithographic, etching method and method of sputtering of metal or system of metals, formation of transistor channel by means of electronic lithography and etching, application of masking dielectric layer, formation in masking dielectric layer of submicron slot by means of electronic lithography and etching; at that, submicron slot is formed with variable cross section decreasing as to height from wide upper part adjacent to the head of the above control electrode to narrow lower part adjacent to transistor channel, formation of topology of the above control electrode by means of electronic lithography method, formation of the above control electrode in submicron slot by means of sputtering of metal or system of metals; at that, configuration of its base repeats configuration of submicron slot. During formation of submicron slot with variable cross section in masking dielectric layer, which decreases throughout its height, by means of electronic lithography and etching, the latter of masking dielectric layer is performed in one common production process in high-frequency plasma of hexafluoride of sulphur, oxygen and helium and discharge power of 8-10 W.

EFFECT: increasing output power and amplification factor, increasing reproducibility of the above output parametres and therefore yield ratio, simplifying and decreasing labour input for manufacturing process.

2 cl, 1 dwg, 1 tbl, 5 ex

FIELD: electricity.

SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.

EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.

6 dwg

FIELD: electricity.

SUBSTANCE: method for UHF high-power transistors manufacturing includes formation of transistor topology semiconductor substratum on the face side by electronic lithography and photolithography methods, metals spraying on, dielectrics application and etching, cathodic electrodeposition of gold, formation of preset size grooves on the face side outside the transistor topology, substrate thinning, formation of grounding through holes for the transistors source electrodes, formation of a common integrated heat sink, formation of a integrated heat sink for each transistor crystal, semiconductor substrate division into transistor crystals; one uses a semiconductor substrate with the preset structure of active layers having two stop layers with the preset distance between them, the stop layers ensuring minimum thermal resistance; the semiconductor substrate reverse side thinning is performed down to the stop-layer located close to such side; grounding through holes are formed immediately on the source electrodes with the common integrated heat sink thickness is set by the type of the transistor crystal subsequent mounting.

EFFECT: enhanced output capacity through reduction of thermal resistance, parasitic of the electric resistance in series and source electrodes grounding inductance; increased yield ratio, repeatability and functionalities extension.

4 cl, 1 dwg, 1 tbl

FIELD: electrical engineering.

SUBSTANCE: method for manufacture of a powerful UHF transistor includes formation of the topology of at least one transistor crystal on the semiconductor substrate face side, formation of the transistor electrodes, formation of at least one protective dielectric layer along the whole of the transistor crystal topology by way of plasma chemical application, the layer total length being 0.15-0.25 mcm, formation of the transistor crystal size by way of lithography and chemical etching processes. Prior to formation of the transistor crystal size, within the choke electrode area one performs local plasma chemical etching of the protective dielectric layer to a depth equal to the layer thickness; immediately after that one performs formation of protectively passivating dielectric layers of silicon nitride and diozide with thickness equal to 0.045-0.050 mm; plasma chemical application of the latter layers and the protective dielectric layer is performed in the same technological modes with plasma power equal to 300-350 W, during 30-35 sec and at a temperature of 150-250°C; during formation of the transistor crystal size ne performs chemical etching of the protectively passivating dielectric layers and the protective dielectric layer within the same technological cycle.

EFFECT: increased power output and augmentation ratio or powerful transistors with their long-term stability preservation.

4 cl, 1 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.

EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.

3 cl, 7 dwg

FIELD: physics.

SUBSTANCE: invention relates to semiconductor technology. Proposed method comprises removal of photoresist from at least one surface of conducting layer with the help of the mix of chemical including first material of self-optimising monolayer and chemical to remove said photoresist. Thus self-optimising monolayer is deposited on at least one surface of said conducting ply. Semiconductor material is deposited on self-optimising monolayer applied on conducting layer without ozone cleaning of conducting layer.

EFFECT: simplified method.

15 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: method for manufacture of powerful SHF transistor includes application of a solder layer to the flange, shaping of pedestal, application of a sublayer fixing the transistor crystal to the pedestal, formation of p-type conductivity oriented at the plane (111) at the base substrate of single-crystalline silicon and auxiliary epitaxial layers, application of the basic layer and buffer layer for growing of epitaxial structure of a semiconductor device based on wide-gap III-nitrides, application of heat conductive layer of CVD polycrystalline diamond to the basic layer, removal of the basic substrate with auxiliary epitaxial layers up to the basic layer, growing of heteroepitaxial structure based on wide-gap III-nitrides on the basic layer and formation of the source, gate and drain. The heat conductive layer of CVD polycrystalline diamond is used as a pedestal; nickel is implanted to its surficial region and annealed. Before formation of the source, gate and drain an additional layer of insulating polycrystalline diamond and additional layers of hafnium dioxide and aluminium oxide are deposited on top of the transistor crystal; the total thickness of the above layers is 1.0-4.0 nm.

EFFECT: invention allows increased heat removal from the active part of SHF-transistor and minimisation of gate current losses.

6 cl, 4 dwg

FIELD: electronic equipment.

SUBSTANCE: invention is intended to create discrete devices and microwave integrated circuits with the help of field-effect transistors. Method of making field-effect transistor, including creation of drain and source contacts on the contact layer of semiconductor structure and extraction of active region, metal or metal and dielectric mask is applied directly on the surface of contact layer, formation of submicron slot in the mask for further etching operations of contact layer etching and application of T-shaped gate metal through resist mask, after application of the first metal mask lithography for opening windows is carried out when one of the edges coincides with location of Schottky gates in manufactured transistor, and after opening windows the second metal or dielectric mask is applied on the whole surface, remove resist and by lithography create window in resist surrounding slits formed between two metals or between metal and dielectric, perform selective etching of contact layer, after which spray metal films to form T-shaped gates. As a result, edges of T-shaped gate heads on both sides resting on metal or metal and dielectric masks. Then, via selective etching the mask is removed from under the "wings" of T-shaped gate and from the surface of transistor active area. After that, the surface of transistor active area, containing drain, source contacts and Schottky gates, is coated with a passivating layer of dielectric so that under "wings" of T-shaped gate cavities are formed filled with vacuum or gas medium.

EFFECT: technical result is production of gated with length less than 100 nm, as well as reduced thickness of the metal mask and elimination of intermediate layer of dielectric placed between the active region surface and mask.

1 cl, 1 dwg

FIELD: heterostructures of semiconductor devices, primarily those of field-effect transistors.

SUBSTANCE: proposed semiconductor heterostructure of field-effect transistor has AlN single-crystalline substrate, GaN template layer, GaN channel layer, and AlxGa1-xN layer; disposed one on top of other between template and channel layers are intermediate AlyGa1-yN layer and AlzGa1-zN buffer layer, respectively; value of y at template layer boundary is 1 and at buffer layer boundary it equals buffer layer z value; in this case 0.3 ≤ x ≤0.5 and 0.1 ≤ z ≤0.5. Buffer layer in semiconductor heterostructure at channel layer boundary can be doped with Si through depth of 50 to 150 Å.

EFFECT: enhanced conductivity of heterostructure channel layer and, hence, enhanced working currents and power of field-effect transistors.

2 cl, 1 dwg

FIELD: electric engineering.

SUBSTANCE: invention is related to power vertical transistors, comprising MOS-structure, produced with application of double diffusion, having source electrodes (emitter) and gate on one surface of substrate, and drain electrode (collector) on opposite surface of substrate. In transistor with current limitation, comprising substrate having the first and second opposite surfaces, DMOS-transistor installed on the first surface of substrate, alternating areas of N-type and P-type of conductivity arranged on the second surface of substrate, cells of DMOS-transistor on the first surface of substrate have a shape of strips, alternating areas of N-type and P-type of conductivity have a shape of strips on the second surface of substrate, moreover, strips on the second surface of substrate are arranged perpendicularly relative to strips on the first surface of substrate. In process of transistor manufacturing they form areas of N-type and P-type of conductivity on the second surface of substrate with a certain ratio of areas.

EFFECT: manufacturing of transistor of increased resistance to short circuit of load circuit with specified current limitation, increased accuracy of reproducibility of specified current limiter, increased yield of good transistors in percentage ratio, reduced prime cost of transistors manufacturing.

7 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: in vertical field transistor containing the source connection, ohmic contact to the source, source, vertical conducting channels, gate made in the form of metal band, sink, the first and the second dielectric layers located on upper and lower surfaces of metal band and adjacent to side surfaces of vertical conducting channels, and substrate, to lower sink surface there in series applied is layer of ohmic contact, contact layer of ductile metal and damping layer of ductile metal, to lower surface of non-perforated end of metal band there in series applied is the first process layer, the second process layer and support for non-perforated end of metal band; substrate is made from heat-conducting dielectric material; to upper side of substrate there applied are the first and the second contact platforms which are galvanically connected to lower surfaces of damping layer and metal support, and all the transistor elements arranged on dielectric substrate, except the source connection, are enveloped with protective dielectric filling.

EFFECT: invention allows increasing output power of transistor and improving reliability and its life time.

8 cl, 3 dwg

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