System for software control of technological equipment

 

(57) Abstract:

The invention relates to microprocessor technology and can be used in a microprocessor-based control system. The technical result is to increase the reliability of functioning of the system for software control of technological equipment. This system contains a microprocessor, a clock generator, system controller, the buffer address decoders, memory, bus shapers, elements OR flip-flops, registers, multiplexer, decoder-demultiplexer, the delay elements, the comparison circuit. 2 Il., table 2.

The invention relates to microprocessor technology and can be used in a microprocessor-based control system.

Known microprocessor system consisting of a microprocessor, a clock generator, system controller, decoder memory addresses, memory, permanent memory, bus driver memory, decoder device addresses of the I / o bus structure of input-output, three elements OR first, second and third bus shapers, trigger register, the comparison circuit and the four elements And (A. C. 1418653, CL G 05 B, 1988).

The disadvantage of this system is the e microprocessor system for software management electrics, containing a microprocessor, a clock generator, system controller, the buffer address, the address decoder memory, permanent memory, RAM, bus driver memory, the address decoder device I / o, register, bus shapers I / o, bus driver input, the bus driver youngest addresses, the bus driver senior address, the bus driver records, the bus driver control, trigger, four elements OR three elements, one-shot, two delay elements, decoder, multiplexer and two elements OR (A. C. 1532899, CL G 05 B 19/18,1989).

The disadvantage of this system is the low testability of the software.

The closest in technical essence to the present invention is a system for software control of technological equipment that contains a microprocessor, a clock generator, system controller, the buffer address, the address decoder memory, permanent memory, RAM, bus driver memory, the address decoder device I / o bus shapers I / o in number equal to the number of groups of input and output variables, three elements OR bus form the first and second inputs of the clock generator is connected to a quartz resonator, the third and fourth inputs clock inputs are "Ready" and "Reset" microprocessor systems, respectively, the fifth input of the clock generator is connected to the sync output of the microprocessor, the first and second outputs of the clock generator is connected to the first and second clock inputs of the microprocessor, the third and fourth outputs of the clock generator is connected to the inputs of "Readiness" and "Reset" microprocessor accordingly, the sixth input of the microprocessor is an entry "interrupt Request" microprocessor system, the fifth output of the clock generator is connected to the synchronization input of the system controller, the address outputs of the microprocessor are connected to the inputs of the buffer address, inputs/outputs data of the microprocessor are connected to the inputs/outputs data to the system controller, the control outputs of the microprocessor are connected to the control inputs of the system controller, the second and third outputs of the microprocessor are outputs permissions interrupt and standby microprocessor systems, respectively, the outputs of buffer addresses are address bus microprocessor systems, respectively, inputs/outputs data system controller is a microprocessor data bus Sistine inputs of decoder address memory connected to the address bus of the microprocessor system, the enable input of decoder memory addresses connected to the output of the first element OR the first and second outputs of which are connected to the bits of the control bus of the microprocessor system "Read memory", "memory Write", respectively, the first output of the decoder memory addresses connected to the first input resolution permanent memory, the second output of decoder memory addresses connected to the enable input of RAM, inputs/outputs bus driver memory connected to the data bus of the microprocessor system, the inputs bus driver memory connected to the outputs of RAM, outputs bus driver memory connected to the data inputs of RAM, address inputs constant and memory connected to the address bus of the microprocessor system, the input write memory connected to the discharge control bus microprocessor systems "Write memory", information inputs of the address decoder device input/output connected to the address bus of the microprocessor system, the enable input of the address decoder device input/output connected to the output of the second element OR the first and the second input of which is connected to the discharge control bus of the microprocessor system is and address input/output connected to the first enable inputs of the respective tire shapers I/o, a second enable input bus shapers input/output connected to the discharge control bus "Input from the input device, the input/output bus shapers input/output connected to the data bus of a microprocessor system, groups of inputs tire shapers input/output are the first group of information inputs of a microprocessor system, and their outputs are the first group of information outputs of microprocessor-based systems, information inputs of the register status code is connected to the data bus of the microprocessor system, and the first group of outputs register status code is the second group of information outputs control input vector microprocessor system, informational inputs bus driver of the input vector are the second group of information inputs of the explicit logical conditions of a microprocessor system, the inputs/outputs bus shapers of the input vector and the address of the program connected to the data bus of a microprocessor system, characterized in that it introduced the triggers from second to 11th, forming together with the first trigger group of n triggers explicit and implicit logical conditions, and the register, and the first and second enable inputs puff is iroutes memory the first input of the microprocessor is the input of the capture system, the first enable input bus driver memory connected to the enable input of RAM, input/output permanent memory connected with the data bus of the microprocessor system, the information inputs of the register status code and register connected together, the output register is connected to the information input of the bus driver the address of the program is the access address of the program system, the enable input of the second bus driver the address of the program is connected to the control bus of the microprocessor system, each of the bits of the third group of outputs of the decoder memory addresses state clock inputs connected to the respective triggers explicit and implicit logical group, the first entry permit bus driver input vector, which is the first output of the microprocessor system, the first input of the third element OR, synchronator register, synchronator register status code, which is the second output of the microprocessor control system, the first enable input bus driver the address of the program, the second enable input of bus driver input vector is connected to the bus address information inputs bus driver input vector and are the outputs of the control input vector microprocessor system, the information inputs of flip explicit and implicit logical group connected to the data bus microprocessor systems, third output of the clock generator is connected to the second input of the third element OR the output of which is connected to the inputs of the installation to its original state triggers explicit and implicit logical group setting register and the register status code (patent 2072546 (RF), class. G 05, 19/18, 1997).

The disadvantage of the prototype is the low reliability of operation.

This is because in the prototype there are no technical means of monitoring the performance of conditional transitions that may lead to development of an incorrect sequence of program execution and the issuance of incorrect information in the trigger group explicit and implicit logical conditions. The correctness of branching is ensured by the absence of failures (failures) in the schemes forming the next address in the program counter of the microprocessor is given the value of the relevant characteristic of the operation that you are branching. The result of the operation is recorded in the register of the microprocessor, for example in the case of the battery, and the result value are the so-called flags the wasp etc) But in the prototype validation results of operations in arithmetical-logical unit of the microprocessor and the formation of the subsequent address of the conditional jump is not possible.

In modern microprocessor systems based on processors Intel enterprise are increasingly used tool for monitoring and diagnosing imposed control on odd address bus, information, commands and data are controlled operations in the coprocessor, and so on (Huk M Intel: from 8086 to Pentium II. SPb: Peter, 1998. - 224 S.; Huk M, Pentium II, Pentium Pro and just Pentium. SPb: Peter, 1999. -288 C.).

Is a multi-stage pipeline fetch commands, implemented the "prophecy" of the direction of branching. However, such an important process, as the actual execution of a conditional branch on the value of some bits of the sign, is not yet implemented. This greatly reduces the reliability of functioning and can lead to calculation errors similar to the identified error in the coprocessor floating point (Pentium), which the company Intel is still free substitutes.

In this regard, the present invention is to increase the reliability of the operation.

This objective is achieved in that the system for software control of technological equipment that contains a microprocessor, a clock generator, system controller, the buffer address, the address decoder memory, constant memory, the number of groups of input and output information, three elements OR bus driver input vector machine model, serial driver code, group n trigger logic conditions, where n is the number of tested logical conditions, the code register the condition code register program, and the first and second inputs of the clock generator is connected to a quartz resonator, the third input of the clock generator is the input "Reset" microprocessor system, the fourth input of the clock generator is connected to the sync output of the microprocessor, the first and second outputs of the clock generator is connected to the first and second clock inputs of the microprocessor, the third and fourth outputs of the clock generator is connected to talam "Reset" and "Readiness" of the microprocessor, respectively, the fifth input of the microprocessor is the entrance of "Capture" of a microprocessor system, the sixth input of the microprocessor is an entry "interrupt Request" microprocessor systems, second output of the microprocessor is exiting standby microprocessor systems, third output of the microprocessor is the output resolution of the interrupt of the microprocessor system, the fifth output of the clock generator is connected to the synchronization input of the system controller, the address outputs the data outputs of the system controller, the control outputs of the microprocessor is connected to the control input of the system controller, the control output of the microprocessor Confirmation "capture" is connected to the enable input of the buffer address, the outputs of buffer addresses are address bus microprocessor systems, outputs, inputs data of the system controller is a microprocessor data bus system, the control outputs of the system controller are the control bus of the microprocessor system, the information inputs of the decoder address memory connected to the address bus of the microprocessor system, the enable input of decoder memory addresses connected to the output of the first element OR the first and the second input of which is connected to the discharge control bus microprocessor systems "Read memory", "Memory write", respectively, the first output of the decoder address Namath connected to the first input resolution permanent memory, the second input of which is connected to the discharge control bus microprocessor systems "Read memory", the second output of decoder memory addresses connected to the enable input of RAM, a log record which is connected to the discharge control bus microprocessor systems "memory Write", address whanau memory and input-output faster memory connected to the data bus of a microprocessor system, the information inputs of the address decoder device input-output connected to the address bus of the microprocessor system, the enable input of the address decoder device I / o is connected to the output of the second element OR the first and the second input of which is connected to the discharge control bus microprocessor systems "Input from input devices, Output to the output device," respectively, r bits of the first group of outputs of the address decoder device I / o is connected to the first enable inputs of the respective r tire shapers input-output, a second enable input r of the tire forming I / o is connected to the discharge control bus "Input from the input device, the input-output r tire shapers I / o is connected to the data bus of a microprocessor system, groups of inputs r of the tire forming I / o group are r information inputs of a microprocessor system, and their outputs are a group r informational outputs of the microprocessor system, the outputs of the trigger n trigger logic conditions together with the outputs register status code are a group of outputs of the control input vector machine model and connected to information inputs the program code, triggers from the group r trigger logic conditions connected to the output of the fourth element, OR the first input of which is connected to the fourth output Reset clock generator, the outputs of the register code are the outputs of the program code of the system and connected to information inputs bus driver code, the outputs of which information inputs register the program code connected to the data bus system, the outputs bus driver input vector machine model is connected to the data bus system, the first input of the third element OR connected to the fourth output Reset clock generator.

According to the invention introduced the memory block state machine model, the bus driver automaton model, the trigger ready, the control register write signs, two register signs, multiplexer, decoder-demultiplexer, two accounts of the trigger, the fourth element OR two elements And two delay elements, the case of the comparison and the comparison circuit, and an information input triggers from the group r triggers logical condition and the first group of address inputs of the memory block automaton model that contains one digit, connected to the outputs of the multiplexer, the inputs synchro is-demultiplexer, the enable input of a bus driver program code connected to the first output of the second group of outputs of the address decoder device input / output, the second output of the second group of outputs of which are connected to the synchronization input of the register program code, the third output of the second group of outputs of the address decoder device input / output connected to the enable input of a bus driver input vector machine model, the fourth output of the second group of outputs of the address decoder device input / output connected to the enable input of a bus driver automaton model, the fifth output of the second group of outputs of the address decoder device input / output connected to the inputs of the synchronization register status code and register comparison the outputs of which are connected to the second group of inputs of the comparison circuit and outputs are control program execution system, input reset compare register connected to the input of the reset register status code, and the information inputs of the compare register connected to the data bus system, the outputs register status code is connected to a first group of inputs of the comparison circuit and to the information inputs bus driver automaton model whose outputs are connected to the Istra status code, and the third group of address inputs of the memory block automatic model is connected to the outputs of the register of the program code, the outputs of the memory block automatic model is connected to information inputs of the register status code and are outputs of the control automaton model, the inputs of the synchronization trigger readiness and control register write signs connected to the first output of the third group vychodil decoder address input devices-output, the second output of which is connected to the first input of the fourth element OR the third output of the third group of outputs of the address decoder device I / o is connected to the second input of the third element OR the second input of the fourth element OR connected to the fourth output Reset clock generator, and the output of the fourth element OR connected to the inputs of the reset trigger readiness, case management and record characteristics and the first and second counting triggers, the third input of the fourth element OR is connected to the output of the second delay element, the input of which is connected to the enable input of decoder-demultiplexer and the output of the first delay element, the input of the first delay element connected to the output of the second counting trigger the counting input of which podklyucheniya first and second registers of signs and to the output of the first element And the first input of which is connected to the trigger output of readiness, and the second input of the first element And connected to the discharge control bus microprocessor systems "Write memory", information input control register write characteristics and the first register of the signs connected to the data bus of the microprocessor system, the first group of outputs of the control register write signs connected to the address inputs of the decoder-demultiplexer and an output control rooms logical conditions of the system, the second group of outputs of the control register write signs connected to the address inputs of the multiplexer and an output control rooms of sign systems, the outputs of the first register of the signs connected to information inputs of the multiplexer and the information inputs of the second register signs, and outputs the first control register of the signs of the system, the outputs of the second register characteristics are the outputs of the second register control characteristics of the system, the inputs of resetting the first and second register signs connected to the fourth output Reset clock generator, the output of the comparison circuit is output branch mispredict and connected to the first input of the second element And gotovnosti" clock.

Technical and economic efficiency of the proposed device can be estimated by the magnitude of the increase of reliability of operation due to the control of conditional transitions.

The invention consists, and increase the reliability of operation due to the introduction of controls conditional transitions that allow you to:

a) to record diagnostic information about the results of the operations performed in arithmetical-logical unit of the microprocessor, and the signs of these operations (status word processor);

b) forming a reference code of the linear plot of programs using automata-based model taking into account the characteristic value of the transaction;

C) locking code is actually running the linear section of the program,

g) comparing the reference code of the linear plot and actually executable with the formation of the error signal when the inequality.

The invention is implemented by the following set of structural characteristics of the new elements and relations that determine compliance of the proposed technical solution the criterion of "novelty".

Introduction trigger readiness and the corresponding links allows you to prepare a control means for receiving slto - in the registers of the signs.

The introduction of the control register write characteristics and the corresponding links allows you to configure the control means for estimating the sign and to record it in the trigger logic condition.

The introduction of two registers of signs and their relationships allows the hardware to capture additional diagnostic information (status word processor) with software recording it in the stack, which ensures the control and recording of the desired characteristic, and the control of the operation.

The introduction of the multiplexer and the corresponding relations allows for information indicative of values of the desired characteristics for recording and storing and modifying the state machine model in the memory block automaton model.

Introduction decoder-demultiplexer and the corresponding relationships enables us to provide a record of the desired characteristic in the desired group trigger n trigger logic conditions.

Introduction counting triggers and corresponding relations allows to receive only two signal recording and stack and subsequent withdrawal of readiness - reset trigger readiness.

The introduction of two elements is possible transient commit diagnostic information.

Introduction schema comparison and related links allows you to generate the error signal branching (conditional move) in case of no comparison codes are actually executable line section and the code generated automata model.

The introduction of the memory block state machine model and the corresponding links allows you to store the reference codes of the linear sections formed with regard to code the current plot and the characteristic value (variable branching).

The introduction of the compare register and the corresponding links allows you to record programmatically issued in the scheme code is actually an executable linear plot.

The introduction of new links for register status code allows you to record the reference code of the linear section of the program that is read from the memory block automaton model.

The introduction of new links for code register program allows you to read from the memory block state machine model information corresponding to the program.

Introduction bus driver automaton model and the corresponding relations of the software allows you to enter information from the output of the status register when checked.

The introduction of new spheremania branching from the outputs of the multiplexer.

The introduction of a fourth element OR the corresponding links allows you to reset the trigger readiness in process control and testing.

The introduction of the first element And the corresponding links allows you to generate recording signals indicative of the information in the register features under control of a conditional jump.

The introduction of the second element And the corresponding links you can take the ready signal from the clock generator when an error is detected branching.

Thus, the proposed solution meets the criterion of "significant differences", as in known devices, the analog and the prototype property is not achieved to enhance the reliability of operation due to the absence of this combination of structural features.

Using the proposed system can be obtained positive effect of increasing the reliability of operation due to the control of conditional transitions in the software.

In Fig. 1 shows a functional electric diagram of the proposed system for software control of technological equipment.

In Fig. 2 shows an example of count IV is incorporated: the microprocessor 1, containing the outputs of the address 1.1, inputs/outputs data 1.2, control outputs 1.3; clock inputs of 1.4 and 1.5, the reset input 1.6, sign readiness 1.7, synchronized output 1.8, a clock generator 2, which contains the inputs 2.1 and 2.2 connection of the quartz resonator, the input 2.3 synchronization clock outputs 2.4 and 2.5, the output of 2.6 reset, output ready 2.7 and output system strobe 2.8; system controller 3, containing the inputs/outputs data 3.1, which is the data bus of the microprocessor system, the control outputs 3.2, which is the bus control microprocessor system, the buffer address 4, containing the outputs 4.1, which is the address bus of the microprocessor system, the decoder memory address 5 containing output 5.1 connection permanent memory, output 5.2. connection memory; non-volatile memory 6; RAM 7; the address decoder device I / o 8 containing the first group of output devices I / o 8.1, groups of two outputs 8.2 and 8.3 three, r tire shapers I / o 9.1. . .9.r; the first element, OR 10, the second element OR 11, the bus driver input vector machine model 12, the bus driver code 13, group n trigger logic conditions 14.1...14.n, the register status code 15, the register code progger readiness 20; the control register write signs 21; the first 22 and second 23 registers of signs; the multiplexer 24; decoder-demultiplexer 25, the first 26 and second 27 counting triggers; the fourth element 28, the first element And 29, the first 30 and second 31 delay elements, the compare register 32, the comparison circuit 33, the second And gate 34, the input of the interrupt request 35, exit standby 36; output resolution interrupts 37; group outputs control input vector machine model 38, the output of the program code 39; the outputs of the control automaton model 40; control outputs 41 of the first register signs; control outputs 42 of the second register marks; group r information inputs 43.1. . . 43.r; group r information outputs 44.1...44.r; output control rooms logical conditions 45, outputs, control room indication 46, the reset input 47, the input ready 48, input capture 49, exit branch mispredict 50, the outputs of the execution program 51.

The first 2.1 and 2.2 second inputs of the clock generator 2 is connected to a quartz resonator. The third input of the clock generator 2 is input "Reset" 47 microprocessor systems. The fourth input 2.3 oscillator 2 is connected to the output of the synchronization 1.8 microprocessor 1. The first 2.4 and 2.5 second outputs of the clock generator 2 is on generator 2 is connected to the input "Reset" 1.6 " and "Readiness" 1.7 microprocessor 1, respectively. The fifth input of the microprocessor 1 is the input Capture 49 microprocessor systems. The sixth input of the microprocessor 1 is the input "interrupt Request" 35 microprocessor systems. The second output of the microprocessor 1 is output expectations 36 microprocessor systems. The third output of the microprocessor 1 is the output resolution of the microprocessor interrupt system 37. The fifth output 2.8 clock generator 2 is connected to the synchronization input of the system controller 3. The address outputs 1.1 microprocessor 1 is connected to the input buffer address 4 Address outputs 1.1 microprocessor 1 is connected to the inputs of buffer addresses 4. Outputs inputs data 1.2 microprocessor 1 is connected to the inputs-outputs data to the system controller 3. The control outputs 1.3 microprocessor 1 is connected to the control inputs of the system controller 3. Control output 1.3.1 microprocessor Confirmation "capture" is connected to the enable input of the buffer address 4. The outputs of the buffer address 4 are the address bus 4.1 microprocessor systems. Outputs inputs data to the system controller 3 are 3.1 data bus microprocessor systems. The control outputs of the system controller 3 are the control bus 3.2 microprocessor systems. Information is phratora address memory 5 connected to the output of the first element, OR 10, the first and the second input of which is connected to the discharge 3.2.1, 3.2.2 control bus 3.2 microprocessor systems "Read memory", "memory Write", respectively. The first output 5.1 decoder address memory 5 connected to the first input resolution permanent memory 6, the second input of which is connected to the discharge 3.2.1 control bus 3.2 microprocessor systems "Read memory". The second output 5.2 decoder address memory 5 is connected to the enable input of RAM 7, the input record which is connected to the discharge 3.2.2 control bus 3.2 microprocessor systems "Write memory". Address inputs constant 6 and RAM 7 is connected to the address bus 4.1 microprocessor systems. The outputs of the constant data memory 6 and the input-output RAM 7 is connected to the data bus 3.1 microprocessor systems. The information inputs of the address decoder device 8 input-output connected to the address bus 4.1 microprocessor systems. The enable input of decoder address input devices-output 8 is connected to the output of the second element OR 1.1, the first and the second input of which is connected to the discharge 3.2.3, 3.2.4 control bus 3.2 microprocessor systems "Input from input devices, Output to the output device" with the permission of the appropriate r tire shapers I / o...9 9.1.r. A second enable input r of the tire forming I / o 9.1. ..9.r is connected to the discharge 3.2.3 control bus 3.2 "Input from input devices". Inputs-outputs r tire shapers I / o...9 9.1.r is connected to the data bus 3.1 microprocessor systems. Group inputs r of the tire forming I / o group are r information inputs 43.1... 43.r microprocessor systems, and their outputs are a group r information outputs 44.1...44.r microprocessor systems. The outputs of the trigger n trigger logic conditions 14.1..14.n along with output register status code 15 are a group of 38 outputs control input vector machine model and connected to information inputs bus driver input vector machine model 12. Inputs reset register status code 15 and register the program code 16, triggers from the group r trigger logic conditions 14.1... 14.n connected to the output of the fourth element OR 17, the first input of which is connected to the fourth output 2.6 "Reset" the clock generator 2. The outputs of the register code 16 are the outputs of the program code 39 system and connected to information inputs bus driver code 13, the outputs of which WMO information is RA automaton model 12 is connected to the data bus 3.1 system. The first input of the third element OR 17 is connected to the fourth output 2.6 "Reset" the clock generator 2. The information inputs of the triggers from the group r trigger logic conditions 14.1 14.r and the first group AND0the address inputs of the memory block automaton model 18 that contains one digit, connected to the outputs of the multiplexer 24. Inputs synchronization triggers from the group r trigger logic conditions 14.1...14.n connected to the corresponding outputs of the decoder-demultiplexer 25. The enable input of a bus driver code 13 is connected to the first output 8.2.1 the second group of outputs 8.2 decoder address input devices-output 8, the second output 8.2.2 second group vychodil 8.2 which is connected to the synchronization input of the register code 16. The third output 8.2.3 second group of outputs 8.2 decoder address input devices-output 8 is connected to the enable input of a bus driver input vector machine model 12. The fourth output 8.2.4 second group 8.2 outputs of decoder address input devices-output 8 is connected to the enable input of a bus driver automaton model 19. The fifth output 8.2.5 second group of outputs 8.2 decoder address input devices-output 8 is connected to the inputs of the synchronization code register Southsea outputs control 51 program execution system. Input reset compare register 32 is connected to the input of the reset register status code 15, and the information inputs of the compare register 32 is connected to the data bus 3.1 system. Outputs register status code 15 is connected to the first group of inputs of the comparison circuit 33 and to the information inputs bus driver automaton model 19, the outputs of which are connected to the data bus system 31. The second group A1the address inputs of the memory block automaton model 18 is connected to the outputs of the register status code 15, and the third AND2the group of address inputs of the block Namath automaton model 18 is connected to the outputs of the register code 16. The outputs of the memory block automaton model 18 is connected to information inputs of the register status code 15 and are outputs of the control automaton model 40. Inputs synchronization trigger readiness 20 and control register write signs 21 connected to the first output 8.3.1 third group 8.3 outputs of the address decoder device input-output 8, the second output 8.3.2 which is connected to the first input of the fourth element 28. The third output 8.3.3 third group 8.3 outputs of decoder address input devices-output 8 is connected to the second input of the third element OR 17 Second input chetvertogo connected to the inputs of the reset trigger readiness 20, case management entry signs 21 and the first 22 and second 23 audit triggers. The third input of the fourth element 28 is connected to the output of the second delay element 31, whose input is connected to the enable input of decoder-demultiplexer 25 and the output of the first delay element 30. The input of the first delay element 30 is connected to the output of the second counting trigger 27, the counting input of which is connected to the inverse output of the first counting of the trigger 26. The counting input of the first counting trigger 26 is connected to the inputs of the synchronization of the first 22 and second 23 registers the signs to the exit of the first element And 29, the first input of which is connected to the output trigger ready 20. The second input of the first element And 29 connected to the discharge 3.2.2 control bus 3.2 microprocessor systems "Write memory". The information inputs of the control register write signs 21 and the first register signs 22 is connected to the data bus 3.1 microprocessor systems. The first group of outputs of the control register write signs 21 is connected to the address inputs of the decoder-demultiplexer 25 and is output 45 of the control rooms logical conditions of the system. The second group of outputs of the control register 21 entry signs connected to airespring 22 is connected to information inputs of the multiplexer 29 and the information inputs of the second register signs 22, and is also outputs control 41 of the first register of the characteristics of the system. The outputs of the second register 23 are signs outputs control 42 of the second register of the characteristics of the system. Inputs reset of the first 22 and second 23 register of signs connected to the fourth output 2.6 "Reset" the clock generator 2. The output of the comparison circuit 33 is output 50 branch mispredict and connected to the first input of the second element And 34, the second input of which is a sign of readiness 48 system. The output of the second element And 34 connected to the fifth input "Readiness" of the clock generator 2.

The microprocessor 1 perceives the external clock signals and control signals, and generates the signals address, data and control, reads commands from the permanent 6 or 7 operational memory, executes it, with the possible entry of information and the RAM 7, the output device or receives information from the input device, in response to external control signals. The microprocessor 1 can be implemented, for example, on a standard integrated circuit (IC CR 580 IR 80 And (Microprocessors and microprocessor complexes of integrated circuits: Handbook 2 T. /C.-B. N. Abraitis, N. N. Averianov, A. I. Belous and others; M.: Radio and communication, 1988. T. 1. S. 55-itemnode controller 3 and the signal conditioning system is reset and ready.

The oscillator 2 may be, for example, implemented in standard integrated circuit (IC KP 5801 F (ibid, S. 157-160).

The system controller 3 is designed to provide bidirectional data transfer via the data bus 3.1 and for forming a control bus 3.2 microprocessor systems.

It can be implemented, for example, on a standard integrated circuit (IC CR 580 VK 28 (ibid., S. 160-163).

The buffer address 4 is designed to generate the address bus 4.1, providing its desired load capacity, and also provides off when the activation signal 1.3.1 of control outputs of the microprocessor 1.3 by transferring their outputs in high-impedance state.

The buffer address 4 can be implemented in standard integrated circuits VA (ibid, S. 166-169).

Decoder address memory 5 is used for decryption but allows the output signal of the first element 10 OR the address information from the address bus 4.1 to connect a constant 6 (output 5.1) or operational 7 (release 5.2) memory permissive inputs (inputs sampling of the crystal).

Decoder memory addresses can be implemented, for example, on a standard integral mikre programs and data and delivery of this information when reading it, when activated, signals 5.1 decoder memory 5 and 3.2.1 control bus 3.2.

Permanent memory 6 can be implemented, for example, on a standard integrated circuits RT.

The RAM 7 is used to record and store programs and data only during operation of a microprocessor system. When accessing RAM is activated 5.2 signal decoder memory 5. When writing to memory, in addition, activated signal 3.2.2, and reading this signal is deactivated.

RAM 7 may be implemented, for example, on a standard integrated circuits RU.

Decoder address input devices-output 8 is intended for decoding by allowing the output signal of the second element OR 11 address information for the corresponding connection from the r bus shapers I / o 9.1. . .9.r the corresponding discharge of the first group of outputs 8.1; for connecting bus driver code 13, code register program 16, bus driver input vector machine model 12, tire shaper machine model 19, the register status code 15 and the compare register 32 for the appropriate discharge of the second group is adequate to the discharge of the third group of outputs 8.3.

The address decoder device I/o can be implemented, for example, on a standard integrated circuits ID.

The first element OR 11 is designed to control the enable input of the decoder memory address 5 if activated outputs 3.2.1 (read memory) control bus 3.2 or 3.2.2 (memory write).

The second element OR 12 is designed to control the enable input of the address decoder device I / o 9 if activated outputs 3.2.3 (I) or 3.2.4 (output) control bus 3.2 system.

Bus driver input vector machine model 12 is intended for input to the microprocessor 1 by allowing the 8.2.3 signal from the address decoder device I / o 8 information installed on a group of outputs of the control input vector machine model 38, i.e. information about the value of variables conditional transitions available in the trigger group 12 trigger logic conditions 14.1...14.n, the value of the status code, available in the register status code 15.

Bus driver input vector machine model 12 can be implemented, for example, on a standard integrated circuit WA.

Tire form the address of the device I / o 8 information of the program code, installed on the outputs of the register code 16 and exits the program code 39.

Bus driver code 13 can be implemented, for example, on a standard integrated circuit WA.

Group n trigger logic conditions 14.1...14.n is used for recording the values of logical conditions that are checked during the execution of a program by the conditional branch instructions, with the antics of the multiplexer 24 and the signals generated at the outputs of the decoder 25. In addition, some triggers... 14 14.1. n can be used to record additional variables for which there is no branching, but which can be controlled.

Group n trigger logic conditions 14.1...14.r resets the output signal of the third element OR 17 and forms the input vector machine model, issued on the corresponding outputs 38 when implementing a structured programme similar to the prototype.

Group n trigger logic conditions 14.1...14.r can be implemented, for example, on a standard integrated circuits TM.

Case status code 15 is designed for recording, storing and issuing state of the program, i.e., the current code (executable) linear teaching the operator addresses of devices I / o 8 and is conducted on a first group of inputs of the comparison circuit 33 and the first group of address inputs of the memory block automaton model 18.

Case status code 15 is reset by the output signal of the third element OR 17 and may be implemented, for example, on a standard integrated circuits IR.

Register code 16 is designed for recording, storage and distribution of the program code, i.e. non executable program. This code is written from the data bus 3.1 on 8.2.2 signal from the output of the address decoder device I / o 8 and is output on 39 the program code and the second group of address inputs of the memory block automaton model 18.

Register code 16 may be implemented, for example, on a standard integrated circuits IR.

The third element OR 17 is intended to generate a reset signal group n trigger logic conditions 14.1...14.n register status code 15, register the program code 16 and the compare register 32 or the signal system reset output 2.6 oscillator 2 or the signal 8.3.4 from the output of the address decoder device I / o 8.

The memory block automaton model 18 is designed to store and output the next state depending on the code, the current state - the first group of inputs of the memory block automaton model 18, the value of the variable response is provided subsequent status is issued for informational inputs of the status register 15 and the outputs 40 automaton model.

The memory block automaton model can be implemented, for example, on a standard integrated circuits RT.

Bus driver automaton model 19 is intended for input to the microprocessor 1 of data from output register status code 15 for allowing the 8.2.4 signal from the output of the address decoder device I / o 8.

Bus driver automaton model 19 can be implemented, for example, on a standard integrated circuit WA.

The trigger ready 20 is intended to signal readiness to receive the information on the characteristics (status word PSW) on the first element And 29 signal 8.3.1 from the output of the address decoder device I / o 8, i.e., when the output control information recording characteristics in the control register write signs 21.

The trigger ready 20 is reset by the output signal of the fourth element OR 28.

The trigger ready 20 - trigger D-type, TTL circuits unconnected input D is equivalent to a logical unit. So on the leading edge of the synchronization signal, the trigger 20 is set to be a "unit", forming a signal of logical units on the exit.

The trigger ready 20 can be the signs 21 is designed to receive from the data bus control information recording features: rooms logical conditions on the address inputs of the decoder-demultiplexer 25 and outputs control rooms logical condition 45; non sign - on address inputs of the multiplexer 24 and outputs control room indication 46. This information is recorded during execution by the microprocessor 1 command output on the address, when it is excited by the output 8.3.1 decoder address input devices-output 8.

The control register write signs on 21 may be implemented, for example, on a standard integrated circuits IR.

The first register signs 22 is designed to record information signs with bus data 3.1 the output signal of the first element in the process of implementation of the microprocessor 1 a write command status words (PSW) in the stack is in RAM 7. After you run this command in the first register signs 22 is information about the signs of the last made in arithmetical-logical unit of the microprocessor 1 of the operation. This information is issued for informational inputs of the multiplexer 24 and outputs control 41 of the first register signs.

The first register signs 22 is reset by the signal system reset outputs 2.6 oscillator 2.

The first register signs 22 may be implemented, for example, on a standard integrated circuits IR.

s 22. On the first synchronization signal coming from the output of the first element And 29 in the second register signs 23 is written to zero, because in the original position registers 22, 23 reset signal to the system reset 2.6 outputs of clock generator 2, and in the first register signs 22 shows the state of the accumulator register of the microprocessor 1 after surgery. On the second clock to the second register signs 23 overwritten by the information from the first register signs 22, and in the first register signs 22 provides information on the signs.

The second register signs 23 may be implemented, for example, on a standard integrated circuits IR.

The multiplexer 24 is connected to information inputs trigger n trigger logic conditions 14.1...14.n from the output of the first register signs 22 in accordance with the address signals installed on the second group of outputs of the control register write signs 21.

The multiplexer 24 may be implemented, for example, on a standard integrated circuits CP.

Decoder-demultiplexer 25 is designed to generate the write clock C is 14.1...14.n based on the output signal of the first delay element 30 in accordance with the address established the first group of outputs of the control register write signs 21.

Decoder-demultiplexer 25 may be implemented, for example, on a standard integrated circuits ID.

The first 26 and second 27 counting triggers are designed to secure the passage of two signals output of the first element And 29 to form a synchronizing pulse for recording values of logical conditions. On the first pulse at the output of the first element And 29 is set to the first counter trigger 26, and its inverse outputs a logical zero. On the second pulse at the output of the first element And 29 of the first counting trigger 26 is reset, its inverted output is set to logical unit, so install a second counting trigger 27 and generates at its output a signal of logical units. The first 26 and second 27 counting triggers are reset by the output signal of the fourth element OR 28.

The first 26 and second 27 counting triggers can be implemented, for example, on a standard integrated circuits TM, which penverne outputs connected to information inputs.

The fourth element 28 is designed to generate a signal sbrotator address of the device I / o 8, either upon receipt of the signal from the output of the second delay element.

The first item 29 is intended to generate a synchronization signal of the first 22 and second 23 registers the signs and the counting signal to the first counting trigger 26 in that case, if the trigger is ready 20 is installed on the control bus 3.2 there is a signal 3.2.2 record in memory, i.e., at the time of writing the status word (PSW) in the stack area of RAM 7.

The first delay element 30 is designed to delay the signal from the second counting trigger 27 to the decoder-demultiplexer 25 and the second delay element 31 at a time determined by the necessity of completing transient recording information in the second register signs 23, change the state of the multiplexer 24.

The second delay element 31 is designed to delay the output signal of the first delay element 30 at a time determined by the necessity of completing transients when writing information to a group of n trigger logic conditions 14.1...14.n.

The first 30 and second 31 delay elements can be implemented, for example, through serial connection of the required number of logic elements.

Register sravnenitel decoder addresses of devices I / o 8 in the process of execution by the microprocessor 1 corresponding command output and delivery of this information to a second group of inputs of the comparison circuit 33.

The compare register 32 is reset by the output signal of the third element OR 17 and may be implemented, for example, on a standard integrated circuits IR.

The comparison circuit 33 is designed to compare the numbers actually executable line section that is installed on the outputs of the compare register 32 and a status code generated automata model and installed on the outputs of the register status code 15.

The comparison circuit 33 may be implemented, for example, on a standard integrated circuits SP.

The second And gate 34 is intended to generate a ready signal to the appropriate input of the clock generator 2 in the case, if there is an external ready signal 48 and the output of the comparison circuit logical unit, i.e., the no branch mispredict. In the case of branch mispredict the ready signal is removed, and the process of instruction execution is terminated.

Input interrupt request 35 is designed to receive the external signal interrupt request.

Output expectations 36 is intended to signal expectations, which is activated if you do not activate the logon readiness of the clock generator 2.

Output resolution interrupts 37 presor 1 enters the interrupt mode.

The group of outputs of the control input vector machine model 38 is designed to transmit information about the state of the Boolean condition at a given time and code the current state.

Exit code 39 is designed for issuing non executable program.

The outputs of the control automaton model 40 are designed to transmit information about the next state of the automaton model.

Control outputs of the first register signs 41 are designed to transmit information about the meaning of the signs available in the register 41.

Control outputs of the second register signs 42 are designed to transmit information about the controlled transactions available in the second register signs 23.

Group r information inputs 43.1 43...r is for entering information in a microprocessor system with process equipment through the bus shapers...9 9.1.r.

The group r of information outputs 44.1...44.r is designed for generating the information processing equipment through the bus shapers...9 9.1. r.

The outputs of the control rooms logical conditions 45 are designed to transmit information about the number of the logical conditions for posleduushie for subsequent control.

The reset input 47 is designed to receive an external reset signal to reset the microprocessor system.

Entrance readiness 48 is designed to receive the external signal readiness.

Input capture 49 is designed to receive the request signal to the direct memory access.

The error output branch 50 is designed to generate an error signal branching with the purpose of increase of reliability of functioning.

The outputs of the execution program 51 intended to issue signals rooms actually executable linear plots to control, for example, some of the watchdog timer. Before beginning program execution exits 51 is reset to zero, and after the end of the program they will also be reset to zero.

Evaluate technical and economic effectiveness of the proposed microprocessor systems.

Let the probability of failure when executing q. Then the reliability of functioning of the system when executing a conditional branch can be estimated by the value (1-q). Let the probability of a failure (refusal) of means of control in the formation of the error signal conditionals qk. Then the accurate functioning of the system correspond to the situation: 1) bisbeeite control

(l-q)(1-qk)+q(1-qk).

Thus, increasing the reliability of operation due to the control of a single conditional jump can be estimated by the value of

< / BR>
In addition, an increased amount of diagnostic information due to the results of operations on the outputs 42, and optionally monitored and unconditional jumps.

System for software control of technological equipment operates as follows.

a) Normal operation.

In this mode, the microprocessor is the same as the prototype. After power-clock generator 2 starts to form two non-overlapping clock sequence, it outputs 2.4 and 2.5 are fed to the inputs 1.4 and 1.5 of the microprocessor 1. Frequency stability is ensured by connecting to the inputs of the clock generator 2.1 and 2.2 of the quartz resonator. The microprocessor 1 starts generating output signals 1) after signal "Reset" input of 1.6, and pre-external signal Reset is input 47 of a microprocessor system, strobiles in the clock generator 2, and with its release 2.6 is supplied to the corresponding input of the microprocessor is it through the second element And 34, the second input is activated after a reset Abdoulaye registers 15, 32 through the OR element 17, the output of the comparison circuit 33, to the appropriate input of the clock generator 2, and the output 2.7 oscillator 2 strobirovaniya the ready signal received at the input of 1.7 microprocessor 1. If the input waiting 48 has a logical signal "0", the output 36 is set to a logical signal "1" indicating that the microprocessor 1 is in the idle state.

The microprocessor 1 generates a status word on the outputs/inputs data 1.2 sync output 1.8, which is fed to the input 2.3 clock generator 2, the output of 2.8 system which gate is supplied to the synchronization input of the system controller 3. On the system gate in the system controller 3 writes the status word with vychodil/inputs data 1.2 microprocessor 1. The status word and information on the control outputs 1.3 microprocessor 1 system controller 3 form the control bus 3.2 microprocessor systems. The system controller 3 generates the data bus 3.1 microprocessor systems and provides bidirectional data transmission on it. The address bus 4.1 microprocessor system address sigmatropic begins reading and executing the program, recorded in the permanent memory 6, starting with zero addresses (after software reset the counter of the microprocessor 1 is set to zero). Decoder memory address 5 activates its output 5.1, as the address bus of the microprocessor system 4.1 exhibited address permanent memory 6 (after reset is zero), and the control bus 3.2 is the active signal 3.2.1 reading memory, and therefore the element OR 11 activates the enable input of decoder address memory 5. Active level output 5.1 decoder memory address 5 connects non-volatile memory 6 according to the first enable input. According to the second enable input constant to namati 6 connects the signal read 3.2.1 with control bus 3.2.

Commands and data are read into the microprocessor 1 in accordance with the address displayed in the address bus 4.1 for Example, can run the bootstrap program from the external storage device into RAM 7. To write information in the memory 7 is activated recording output 3.2.2 control bus 32 microprocessor systems, and, accordingly, the output of 5.2 decoder address memory 5, as the address bus 41 in this case, set the address of the RAM 7. When this input resolution RAM 7 to the active written from the data bus 3.2 the corresponding cell of the RAM 7.

When reading RAM 7 microprocessor system works similarly, except that is not activated output 3.2.2 control bus 3.2, activates the output reading 3.2.1 control bus 3.2. Information from the RAM 7 is read to the data bus of the microprocessor system 3.1, through the system controller 3 outputs/inputs 1.7 microprocessor 1 and the microprocessor 1 according to the addresses displayed in the address bus 4.1.

Thus, the program is executed the control of technological equipment. If necessary, navigate to the routine of the RAM 7 is used as the stack.

The microprocessor then enters the information from their discrete information inputs 43.1. ..43.r or outputs data to their information outputs 44.1...44.r. When the input/output data active signal levels input 3.2.3 or 3.2.4 conclusion (input or output) output element OR 11 activates the enable input of the address decoder device input/output 8, which deshifriral address of the device I/o, set on the address bus 4.1, when the input/output of information with inputs 43 (inputs 44) is activated one of the outputs group outputs 8.1 connecting one of the g bus formirovaniya 3.2.3 the second enable input, moreover, when the activation signal input 3.2.3 bus shapers input/output 9 are converted into input mode input 43, otherwise - mode output at outputs 44. So, including where you can enter the program from the external storage into the main memory 7 by using additional hardware.

Microprocessor system can be translated in the interrupt mode by applying a signal of logical "1" at the input 35, at the same time, if interrupt enabled, removed the enable signal interrupt output 37. This mode is proposed in the microprocessor system is not considered. The logical signal "1" at the input of the capture of 34 microprocessor 1 translates the outputs of the address 1.1 and inputs/outputs data 1.2 in the state of high impedance, generates at the output 1.3.2 confirmation signal capture, which translates the inputs/outputs 3.1 and outputs 3.2 system controller 3 in a state of high impedance, in the same condition with the first and second enable inputs are translated into outputs 4.1 buffer address. Capture mode in this microprocessor-based system is not used.

The microprocessor can enter the information from analog sensors. In this part of the group of inputs 43 is used for removing information from uname Executive bodies with additional technical means.

b) the Mode of implementation of the discipline of software and hardware unification of control algorithms to control branching.

In this mode, the microprocessor executes the control program, equipment, controlling the sequence of its implementation on the basis of finite-automata-based model-checking branching. Decomposition of finite-automata-based model is provided as in the prototype. The difference lies in the process of formation of the information intended for entry in the trigger logic conditions 14. Before executing the conditional transition microprocessor executes the command output (for example, OUT port N) but the address of the trigger readiness 20 (the program further includes display commands). When this occurs, output 8.3.1 decoder address input devices-output 8. Before the beginning of the system, the trigger ready 20 reset signal to the system reset output 2.6 generator 2 through the fourth element 28. The trigger ready 20 is installed on the leading edge of the signal 8.3.1, because at its input D logical unit (for TTL logic unconnected input is equivalent to a logical unit, for other types of circuits it is necessary to connect the D input to IP which is in the control register. The trigger output is ready 20 activates the first input element And 29 preparing it for operation. The element 29 is triggered when the data output from the microprocessor to write to the memory 7, that is, when the excitation signal 3.2.2 "Write memory" on the control bus 3.2. This signal Udet excited and when executing the write command in the stack status word processor, for example, PUSH PSW. This status word and stores information about the signs of the last made in arithmetical-logical unit of processor operations. Thus, it is necessary to perform the required to perform a conditional jump operation (for example, subtraction of operand operand), set the trigger ready 20 command output, carrying information about the variable number and the number of the characteristic stored in the register 21, to perform a write command in the stack status words. By the last command in the stack (in RAM 7) record the contents of the accumulator and the contents of register characteristics of the microprocessor, i.e., two bytes, followed by the signal recording 3.2.2. Therefore, the contents of the battery at the first signal recording 3.2.2 in addition to the entries in the stack will be written in the first register signs 22. At the same time in the second Regis is before you begin signal system reset, 2.6 - zero information. In addition, the output signal from the element 29 will be on the leading edge of the accounts of the trigger 26, also zeroed before working signal system reset 2.6 through fourth element 28. On the second signal recording 3.2.2 on the data bus is given the contents of register characteristics of the microprocessor, which, in addition to the entries in the corresponding cell stack, the output signal from the element 29 will be recorded in the first register signs 22, the contents of which will be overwritten in the second register signs 23 simultaneously. Thus, information on the results of operations prior to the team of conditional transition - the contents of the accumulator of the microprocessor, the contents of register characteristics of the microprocessor installed on the respective outputs 42, 41. In addition, information about the number of logical conditions and the number of scanned characteristic is already installed on the respective outputs 45, 46 from the outputs of the control register write signs 21. Information about the contents of the first register signs 22 is supplied to the information inputs of the multiplexer 24, the address input of which receives the ID numbers of the characteristic of the register 21, the output of multiplexer 24 is set theorising reset the first counter trigger 26 and installing a second countable trigger 27 (the signal from the inverted output of the counting trigger 26), therefore activates the output of the second counting trigger 27. With a delay determined by the necessity of completing transient recording of data in the register 22, change the state of the multiplexer 24 that transmits information about the signs for informational inputs n trigger logic conditions 14, is excited by the output of the first delay element 30. This leads to the prompting of the enable input of decoder-demultiplexer 25, which in turn leads to the excitation of one of its n outputs, which is determined by the address information received from the first group of outputs of the control register write signs 21. Thus, excited by the output of the decoder-demultiplexer 25, which corresponds to the variable number of logical conditions in this program. Therefore, information about the appropriate sign will be written from the outputs of the multiplexer 24 in the trigger group trigger logic conditions 14, the number of which corresponds to the variable number of logical conditions in the program.

Then, with a delay defined by the required completion time of transient processes when recording information in the trigger group n trigger logic conditions 14.1-14. n state change memory automatiste 20 and the first 26 and second 27 counting triggers, preparing a scheme to receive regular information on the signs. Address information to the memory automaton model 18 formed: the first group of address inputs of the code of the current state (with output register 15), the zero input information from the output of the multiplexer 24 (the value of the variable branching), the second group of inputs of the code of an executable program with output register status code of the program 16, in which before you begin the program you write the code executable by the command output, which is excited by the output 8.2.2 decoder address input devices-output 8. Thus, at the output of the memory block automaton model 18 is the code for the new line section of the program management of technological equipment in accordance with the value of the conditional jump. To restore the value of the stack pointer, you must execute the appropriate command, for example, a POP PSW.

Next, the microprocessor executes the command conditional transition, after which the microprocessor prior to execution of a new linear section of the program executes the command output code line section, available in the program (field, for example, the corresponding pre-contrast I / o 8. This code from the data bus into the register 32 comparison signal at its output the information received from the output 8.2.5 decoder address input devices-output. This signal provides the information from the output of the memory block automaton model 18 in the register status code 15. Thus, the register status code 15 is the number of States defined automata-based model program: code of the previous state and the value of the variable branching (for this code), and in the compare register 32 is the status code, which actually took over the program after you run the command branch. When malfunction-free operation of a microprocessor system, these codes should be the same, i.e. at the output of the comparison circuit 33 must be a logical unit. Otherwise, if it was taken wrong, at the output of the comparison circuit is formed by a logical zero, and through the second And gate 34 tone corresponding input of the clock generator 2 will be removed, which will lead to the reset input of readiness 1.7 microprocessor 1. The ready signal is analyzed by the microprocessor 1 before execution of the next instruction, so the transient changes of the States of the inputs of the comparison circuit 33 is tvline 50 will be set to zero the error signal branching.

Information about the code of the current line segment and the values of the variables of the program are given to the group of outputs of the control input vector machine model 38, information about the code of an executable program is issued to the inputs of the program 39, information about the following code line section (for the given state of the output of the multiplexer 24) is issued at the output of the control automaton model 40. Together with information on the outputs 41 control register signs and outputs control 42 of the second register signs, the outputs of the control rooms logical conditions 45 and outputs control room indication of 46 this information can be used to control the control means, and to control the computational process.

The microprocessor 1 can utilize the information available in the register status code 15. This is done by command input address bus driver automaton model 19. Activates the output 8.2.4 decoder addresses of the devices and I / o 8, which enable input connects the bus driver automaton model 19 that transmits information from the outputs of the memory block automaton model 18 on the data bus 3.1, and then to the microprocessor.

The microprocessor 1 can use the info the user code 13. Activates the output 8.2.1 decoder address input devices-output 8, which enable input connects the bus driver code 13 that transmits information from the outputs of the register code 16 on the data bus 3.1 and further to the microprocessor.

To improve the reliability of operation of a microprocessor system, perhaps twice the operation before branching. On the first execution is fixed signs similar to that described above, and the second is the actual branching.

The microprocessor can check the input vector machine model, installed on the outlet 38 and represents the concatenation (concatenation) of the code of logical conditions on the n outputs of the trigger logic conditions 14.1-14.n code and the current state of the outputs of the status register 15. When the corresponding information is transmitted on the data bus 32 via a bus driver input vector machine model 12 for allowing the signal 8.2.3 decoder addresses of devices I / o entering the command input address bus driver input vector machine model 12. The trigger logic condition 14.1-14n and the register status code 15 can be Ostwestfalen address, what is with the beginning of the regular testing program.

Before beginning work or testing another program registers status code 15 and comparison 32 reset by the output of the third element OR 17.

To control the unconditional transitions the microprocessor is the same as the above command produces output compare register 32, the result will happen again the comparison code is actually executed line section (in the compare register 32) and the code obtained from the output of the memory block automaton model 18 and recorded in the register status code 15.

The outputs of the control program execution 51 external equipment using, for example, the watchdog timer can evaluate the allowable intervals of program execution since the installation code of the first line section (beginning of program) until reset compare register 32 (end of program).

It is also possible to control other operations results - not only in front of the conditional transitions. To do this in an arbitrary point in the program you want to run commands similar to the above commands, providing record information in the registers of signs 22, 23, and in the group of n triggers log the Le error detection branching can be reset and begins executing the test program, including testing of controls. The correct formation of the signals at the outputs of the control input vector machine model 38 is checked by entering information via a bus driver input vector machine model 12; on the outputs of the program code 39-by entering information via a bus driver automaton model 19; on the outputs of the execution control program 51, the outputs of the control rooms characteristic 46, the outputs of the control rooms logic level 45, the outputs of the control 41 of the first register of the signs, the outputs of the control 42 of the second register signs can be checked by connecting with additional technical means through the inputs in the group r information inputs 43.1...43.r.

To resolve failures perhaps the repeated operation before branching. When an error is detected branching with additional technical means, signalling the state of the outputs of the execution control program 51, initiates a process of repeating the operation, after which the error was detected branching.

When testing controls can be used the reset signal 8.3.4 group outputs 8.3 decoder device I / o 8, when PR is my first 21 and second 22 registers signs, can be compared with the feature information recorded in the stack is in RAM 7.

Consider the example of a specific implementation of a system for software control of technological equipment.

The distribution ports in octal code: 2008- the compare register 32 (for recording non-running line section); 3008- case management entry signs 21. Room signs: the sign (S)-1112, zero (z)-1102auxiliary carry (AC)-1002, parity (P)-0102, transfer (S)-0002.

The distribution of bits of information in the control register by writing signs: the sign - bits 7,6,5; number of variable bits 4,3,2,1,0.

Let the graph of an executable program has the form shown in Fig.2.

On the graph (Fig.2) edges are linear areas marked in octal codes of their rooms; the arc is labeled with the values of variables that describe the branching program. Then the fragments of a program for control of technological equipment with control conditional Language (Assembler-80) can be described by table 1. In table 1 circled those commands that are entered to control.

The count and the SS="ptx2">

For example, the program is being executed with zero number, so with the register code 16 is reset to zero (Fig. 1)

In the initial state register status code 15 and the compare register 32 is reset by the signal system reset 2.6. Reset and control register write signs 21, the first 22 and second 23 registers signs. Then the address inputs of the block pameti automaton model 18 is also set to zero. The code does not depend on the value of a variable, therefore, recorded in two rows, although at the output of the multiplexer 24 in the initial state is zero. Therefore, the output code is the next state 0012. After the start of the program with the label M0(PL. 1) the microprocessor outputs the code next state 0018address 2008i.e. it uses the output 8.2.5 decoder address input devices-output 8, the compare register 32 is recorded code 0012and in case the status code 15 - information from the output of the memory block automaton model 18. The output of the comparison circuit as in the initial state, supported by the logical unit.

After Wynonna linear program fragment (PL.2) the microprocessor writes the control register write indication code which means that will be checked symptom 1102(zero-z), and this well is there such operation will subtract from the contents of the register - battery (A) the contents of register ().

Before performing the actual branching PUSH PSW loading registers signs 22, 23. If the command is executed branching JNZ Ml variable x0-0 (result of the subtraction operation is nonzero), then jumps to the label Ml. Reset stack pointer command POP PSW, then again you set the compare register code 0012. Because the output of the memory block of the Autonomous model 18 in the row has also 0012if indeed x0=0, which is fixed at the output of the multiplexer 24 and recorded in the trigger 14.1 group n trigger logic conditions 14, when executing commands MVI 001, OUT of 200 will also compare the information. In the case of a branch mispredict information in the compare register 32 and the register status code 15 after executing the corresponding commands will be different that will cause the error signal branching 50. If the command is executed branching JNZ Ml variable, x0=1 (the result of the operation is zero), then run the following command POP PSW - restores the value of the stack pointer. The label M6 is fixed to the passage of the second line section (0102learn if indeed X0= 1, which is fixed at the output of the multiplexer 24 and recorded in the trigger 14.1 group n trigger logic conditions 19, when performing this commit also happens comparison information. Otherwise the same as the above will be fixed error branching.

It should be borne in mind that after the write commands in the control register write signs 21 to execute the command PUSH PSW should not be commands that write to memory in order to avoid incorrect entries in the registers of signs 22, 23.

Next, the control of branching is the same as the above.

Unconditional jumps are controlled by comparing successive States, recorded from the outputs of the memory block automaton model 18 in the register status code 15 with the actual executable code of the linear section in the compare register 32.

When working with some other program register the program code 16 displays the code and from the memory block automaton model 18 is read corresponding to the program information table.2 shows the program with zero number - bits in the address and7and6).

To control the results of the operation at an arbitrary point in the program after aemula sign and number the additional variable; the team OUT of 300, and the commit command in the passage of the corresponding linear plot.

System for software control of technological equipment (the system), containing a microprocessor, a clock generator, system controller, the buffer address, the address decoder memory, permanent memory, RAM, the address decoder device I / o, r tire shapers I / o, where r is the number of groups of input and output information, three elements OR bus driver input vector machine model, serial driver code, group n trigger logic conditions, where n is the number of tested logical conditions, the code register the condition code register program moreover, the first and second inputs of the clock generator is connected to a quartz resonator, the third input of the clock generator is the input "Reset" the system, the fourth input of the clock generator is connected to the sync output of the microprocessor, the first and second outputs of the clock generator is connected to the first and second clock inputs of the microprocessor, the third and fourth outputs of the clock generator is connected to the input "Reset" and "Readiness" of the microprocessor, respectively, the fifth input high performance embedded is istemi, the second output of the microprocessor is the output of the standby system, the third output of the microprocessor is the output resolution of the interrupt system, the fifth output of the clock generator is connected to the synchronization input of the system controller, the address outputs of the microprocessor are connected to the inputs of the buffer address, outputs the data inputs of the microprocessor are connected to the inputs-outputs data to the system controller, the control outputs of the microprocessor are connected to the control inputs of the system controller, the control output of the microprocessor Confirmation "capture" is connected to the enable input of the buffer address, the outputs of buffer addresses are address bus system, outputs the input data to the system controller are the data bus system, the control outputs of the system controller are the control bus systems, information inputs of the decoder address memory connected to the address bus of the system, the enable input of decoder memory addresses connected to the output of the first element OR the first and the second input of which is connected to the discharge of the tire management system "Read memory", "memory Write", respectively, the first output of the decoder memory addresses connected to the first input resolution permanent memory, the second input is resa memory connected to the enable input of RAM, the log record which is connected to the discharge control bus system "Entry in the memory, the address inputs constant and memory connected to the address bus of the system outputs data to permanent memory and input-output memory connected to the data bus system, the information inputs of the address decoder device input / output connected to the address bus of the system, the enable input of the address decoder device I / o is connected to the output of the second element OR the first and the second input of which is connected to the discharge control bus system Input from input devices, Output from the output unit, respectively, r bits of the first group of outputs of the address decoder device I / o is connected to the first enable inputs of the respective r tire shapers I / o, a second enable input r of the tire forming I / o is connected to the discharge control bus "Input from the input device, the input-output r tire shapers I / o is connected to the data bus system, groups of inputs r of the tire forming I / o group are r information system inputs, and their outputs are a group r information system outputs, the outputs of the trigger n trigger l is ora automaton model and connected to information inputs bus driver input vector machine model, inputs reset register status code and register the program code, triggers from the group of n trigger logic conditions connected to the output of the third element OR the first input of which is connected to the third output Reset clock generator, the outputs of the register code are the outputs of the program code of the system and connected to information inputs bus driver code, the outputs of which information inputs register the program code connected to the data bus system, the outputs bus driver input vector machine model is connected to the data bus system, wherein the entered block of memory automaton model, tire shaper machine model, trigger readiness, case management entry signs, two register signs, multiplexer, decoder-demultiplexer, two accounts of the trigger, the fourth element OR two elements And two delay elements, the case of the comparison and the comparison circuit, and an information input triggers from the group of n trigger logic conditions and the first group of address inputs of the memory block automaton model that contains one digit, connected to the outputs of the multiplexer, the inputs of the synchronization triggers from the group of n triggers log the driver program code connected to the first output of the second group of outputs of the address decoder device I / o, the second output of the second group of outputs of which are connected to the synchronization input of the register program code, the third output of the second group of outputs of the address decoder device input / output connected to the enable input of a bus driver input vector machine model, the fourth output of the second group of outputs of the address decoder device input / output connected to the enable input of a bus driver automaton model, the fifth output of the second group of outputs of the address decoder device input / output connected to the inputs of the synchronization register status code and the compare register, the outputs of which are connected to the second group of inputs of the comparison circuit and outputs are control program execution system, input reset compare register connected to the input of the reset register status code, and the information inputs of the compare register connected to the data bus system, the outputs register status code is connected to a first group of inputs of the comparison circuit and to the information inputs bus driver automaton model, the outputs of which are connected to the data bus system, the second group of address inputs of the memory block automatic model is connected to the outputs of the register status code, and the third propanate automatic model is connected to information inputs of the register status code and are outputs of the control automaton model, inputs synchronization trigger readiness and control register write signs connected to the first output of the third group of outputs of the address decoder device input / output, the second output of which is connected to the first input of the fourth element OR the third output of the third group of outputs of the address decoder device I / o is connected to the second input of the third element OR the second input of the fourth element OR is connected to the third output Reset clock generator, and the output of the fourth element OR connected to the inputs of the reset trigger readiness, case management and record characteristics and the first and second counting triggers, the third input of the fourth element OR is connected to the output of the second delay element, the input of which is connected to the enable input of decoder-demultiplexer and the output of the first delay element, the input of the first delay element connected to the output of the second counting trigger the counting input of which is connected to the inverse output of the first counting trigger the counting input of the first counting trigger connected to the inputs of the synchronization of the first and second registers of signs and to the output of the first element And the first input of which is connected to the output trigger ready, and vtoro the control register write characteristics and the first register of the signs connected to the data bus system, the first group of outputs of the control register write signs connected to the address inputs of the decoder-demultiplexer and an output control rooms logical conditions of the system, the second group of outputs of the control register write signs connected to the address inputs of the multiplexer and an output control rooms of the sign system, the outputs of the first register of the signs connected to information inputs of the multiplexer and the information inputs of the second register signs, and also outputs the first control register of the signs of the system, the outputs of the second register characteristics are the outputs of the second register control characteristics of the system, the inputs of resetting the first and second registers of the signs connected to the third output Reset clock generator, the output of the comparison circuit is output branch mispredict and connected to the first input of the second element And a second input which is the input system readiness, and the output of the second element And is connected to the fifth input "Readiness" of the clock generator.

 

Same patents:

The invention relates to the field of radio electronics

The invention relates to the field of radio electronics

FIELD: electrical engineering; systems for running check and control of one or more power consumers.

SUBSTANCE: proposed system for running check and control of set of power consumers, including domestic appliances, that incorporates provision for easy access to remote communication facilities at minimal set of power consumers and for their easy installation for operating under domestic conditions has its power consumers connected to first communication network through adequate interface facilities for exchanging information and/or instructions where transceiving means connected to mentioned first communication network are used to organize channel communications with second remote network and/or remote terminal. Novelty is that mentioned transceiving means are coupled with one of mentioned power consumers share one of interface facilities connected to mentioned power consumer.

EFFECT: enhanced effectiveness in operation with high performance characteristics.

18 cl, 3 dwg, 1 tbl

FIELD: pressure regulator, namely regulator power saving operation method and system providing selective turning on and off separate components of regulator in order to reduce power consumption.

SUBSTANCE: controller and each separate sensor are activated when it is necessary to read sensor data for sampling period. It reduces power value consumed by pressure regulator system. Additional actions for saving power are realized due to using battery pickup for controlling capacitance of battery of pressure regulator and due to changing operation mode of pressure regulator to power saving mode as battery capacitance decreases.

EFFECT: increased time period of pressure regulator maintenance due to its operation in mode of power saving.

47 cl, 19 dwg

FIELD: technology for automatic modeling of system for controlling process, wherein elements of user interface are organized in tree-like structure, reflecting topography of elements in process control system.

SUBSTANCE: each element is assigned to at least one input window, having a set of attributes for setting up and/or monitoring target device, controlled in system for controlling process. Current organization of tree-like structure is recorded as project, and list of all windows, opened during one and the same operation, and also attributes, are recorded as work session, by means of which state of elements is restored during repeated loading of process control system.

EFFECT: improvement of complicated structure of model of real system, positioning of involved graphical elements and information transfer.

3 cl, 6 dwg

FIELD: automation of processes with usage of field devices.

SUBSTANCE: method is realized in control device by means of operation program, which for parameterization in dialog mode is connected to field device via data transfer bus, and which has no access to device description, which describes behavior of field device in autonomous mode. Technical result is achieved because operation program connects to copy of software program of device executed in field device, realizing imitation of field device in dialog mode.

EFFECT: simplification and lower costs of programming.

8 cl, 3 dwg

FIELD: computer engineering.

SUBSTANCE: recharge unit emits infrared light from infrared unit in response to recharge request signal received from robot via wireless transceiver, and sends infrared radiation signal in accordance with infrared light radiation. The self-propelled robot communicates with the recharge unit using various data and sends recharge request signal to the recharge unit when accumulator charge level drops below a threshold level and moves back towards the recharge unit using image data input from camera unit as response to infrared radiation signal sent by the recharge unit. The robot has microprocessor for controlling robot movements for providing return to the recharge unit by processing data of infrared light position on picture introduced from camera unit when detecting infrared light presence in the picture.

EFFECT: accelerated return to recharge unit.

16, cl, 2 dwg

FIELD: automation of processes.

SUBSTANCE: method is claimed for transmitting measurement data between two measuring transformers, made with possible transmission of digital data according to "master - slave" principle through two communication connections in control system which is used as master device, and analog signals. Digital signals are also transmitted between both measuring transformers through additional communication connection, received digital signals are researched at least based on one characteristic value of measurements, required for processing in measuring transformer-receiver.

EFFECT: simplification and increased profitability of data transmission.

17 cl, 1 dwg

FIELD: physics.

SUBSTANCE: field instrument is connected to a control unit via a data bus, the control unit requests personal identifier of the field instrument periodically, and compares it to the stored identifier, and if the identifier differs an alarm or warning message is issued, and the requested identifier is saved to the databank with a timing mark.

EFFECT: eliminates unauthorised manipulation of field instruments.

11 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: electronic measuring instrument contains first processor (21) which executes processing of measured values during first processing cycles using first algorithm, and second processor (25) implementing coordination of tasks including initialisation of the first processor (21). The second processor (25) during time intervals exceeding first processing cycle reads from the first processor (21) control data record and based on this record executes first algorithm to check function correctness of the first processor.

EFFECT: creation of electronic measuring instrument with high probability of hardware faults detecting.

9 cl, 2 dwg

FIELD: physics; measurement.

SUBSTANCE: proposed device for measuring a process parametre of a production process has a sensor for measuring the process parametre and generating an output signal. A mode selector is meant for selecting operation modes. At least one operating mode is linked to the operating range of the sensor. A circuit for correcting the output signal of the sensor is used, in accordance with at least one operating mode, as well as for generating the output signal for the transmission device, which is the measured process parametre.

EFFECT: more accurate measurement of a process parametre of a production process.

34 cl, 5 dwg

FIELD: automation.

SUBSTANCE: particular group of inventions relates to redundant system and automation method for technical device management. Technical result is achieved by that in redundant system of automation, and also in operating procedure of such automation system there are provided two automation instruments, which are outfitted by common memory block, where there are stored automation tool condition data, herewith memory block is implemented in the form of "Reflective Memories". Hereby, automation instruments allows immediate access to common database, and in case of failure of main automation instrument it takes place smooth shifting to standby automation instrument.

EFFECT: increase in automation system productivity.

10 cl, 1 dwg

FIELD: tire industry.

SUBSTANCE: proposed plant contains great number of working units operating successively. Plant is furnished with central processor made for setting successive execution of great number of operations at working stations. Each working station contains at least one unit of indicated working units according to one or several set sequences of tire types. Plant includes also local processor connected with each working station and made for determining type corresponding to drum found in each of said working units. Local processor provides selection of definite procedure from preset group of procedures for each of said working units designed for type of tire corresponding to drum to be used in operation. Invention reduces to minimum downtimes for changing type of tire to be manufactured and makes it possible to manufacture lots of tires of different types without changing equipment producing tire semifinished products.

EFFECT: provision of automatic manufacturing of different type tires.

9 cl, 3 dwg

FIELD: ferrous metallurgy; nonferrous metallurgy; methods of automated control over ore mining and dressing production.

SUBSTANCE: the invention is pertaining to the field of ferrous and nonferrous metallurgy, in particular, to the method of automated control over ore mining and dressing production by means of the branched computer network. The technical result of the invention is an improved quality and effectiveness of the control. The method provides for a measurement within the preset time intervals of an electrical power consumption (PC) by equipment of the technological link (TL) of mining, TL of bucking and TL of iron-ore concentrate production per 1 ton of the product, mains voltage and determination of the correcting coefficient considering the effect of the mains voltage value. On the basis of statistical data for the equipment of the TL of mining, TL of ore bucking and TL of an iron-ore concentrate production considering mechanical and chemical properties of the raw material and the number of units of operating equipment they introduce in the controlling system the boundary parameters (BP) of acceptable values of PC used for production of 1 ton of the products at the fixed main voltage. At the stage of processing by the TL of mining the initial ore is weighted and averaged for bringing of the mechanical and chemical parameters to the preset boundary parameters for processing by the following technological links. At the stage of ore processing by TL of bucking they check the chemical composition and mechanical properties of an intermediate product. At a stage of processing of ore by TL of production of the iron-ore concentrate they determine amount of products of the preset chemical composition produced from 1 ton of the ore, For each link of TL fix the number of the equipment units operating in parallel. Then make a comparison of the power consumed by each TL for production of 1 ton of products with the boundary parameters acceptable PC values per 1 ton of the products for the data of the initial ore composition, parameters of the TL products and a quantity of the units of the equipment in parallel operating in composition of TL. Determine the value of deviations and multiply by the coefficient considering the effect of the mains voltage value. If the measured values of PC exceed at the indicated TLs preset boundary parameters (BP)of acceptable values of PC per 1 ton of the products fix the operating irregularity of the equipment of the particular TL. Analyze the dynamics of the gained deviations rise time and by the obtained results of the analysis determine the sequence and the volume of diagnosing of the particular unit of the TL equipment. After that step-by-step transfer the TL equipment in a diagnostic mode of operation, conduct its diagnosing and issue a command to change the mode of operation of the particular units of the TL equipment or to cease their operation.

EFFECT: the invention ensures an improved quality and effectiveness of the control.

1 dwg

FIELD: automatics and computer science, possible use for developing solutions for tasks for controlling modes of expansive electric energy based systems.

SUBSTANCE: in control system consisting of several sub-systems, connected by means of communication with computer machine, and optimization module connected thereto, computer machine is selected as computer machine of upper level, and each subsystem is provided with computing machine of lower level, herein optimization module and block for calculating functional characteristics of current subsystem are realized, while system is also provided with means for upper level communication and means for lower level communication, computing machines of lower level through communication means of upper level are connected to computing machine of upper level and through communication means of lower level are connected to subsystems.

EFFECT: decreased total amount of information transferred while controlling modes of electric energy based systems, increased speed of operations.

4 cl, 2 dwg

FIELD: engineering of systems for automatic control over technological processes.

SUBSTANCE: in the method appropriate for invention at least one controlling computing machine is utilized and a certain amount of field devices, while status signals and control signals between at least a portion of field devices and controlling computing machine are transferred using TCP/IP protocol via communication channel, preferably for radio-communication and/or Internet. System for controlling process appropriate for invention has controlling computing machine with Web-server, computing machine of client with Internet browser, and also multiple indicators and positioning devices; system for controlling process is preferably services by means of Internet through personal computer of client.

EFFECT: improved universality of software used for servicing and observing.

2 cl, 3 dwg

FIELD: engineering of controlling and adjusting systems for controlling technological processes.

SUBSTANCE: complex contains workstations and servers based on personal electronic computer machines, connected as a local area Ethernet network, and also controllers and functional modules. Programmable logical integral circuits, built into each functional module, support programming of practically any algorithms for processing signals and control, adequate for tasks, assigned by engineer to current module. Three variants of system engineering are possible on basis of means included in complex: centralized control, local control, distributed control. In all three variants central microprocessor module controlled by software performs primary configuring of functional modules, information exchange, control and diagnostics of software and hardware means.

EFFECT: expanded functional capabilities, increased reliability, improved maintainability.

14 cl, 19 dwg

FIELD: computer systems engineering, welding systems, possible use for providing welding architecture to make possible interactive realization of remote configuration, monitoring, control and business operations in distributed environment, wherein welding processes are performed.

SUBSTANCE: system includes at least one welding device, operatively connected to network server, network interface and network for exchanging data with at least one remote system. Remote system includes at least one remote interface for exchanging data with network architecture. Remote system is made with possible request of at least one HTTP socket for setting up connection to welding device through network, loading at least one application from welding device and communication with at least one welding application socket through at least one application for exchanging information between welding device and remote system. At least one appropriate includes at least one of components: welding configuration component, welding monitoring component and welding control component. Method for provision of distributed welding architecture includes stages, at which: welding device is connected to network interface. For setting up network connection through network interface to remote system, at least one socket is used: HTTP socket or welding application socket, where HTTP socket is used for exchanging data with remote systems. Structure of data, providing welding protocol, includes at least one of following fields: field of options/flags, field of order of messages, message status field, data length field, data field, server commands field, server command identifier field, server command arguments field, machine field, machine address field, field of identifier of method/property and field for arguments of method/property.

EFFECT: decreased time and labor costs related to technical maintenance and adjustment of multiple welding devices and systems.

6 cl, 22 dwg

FIELD: connecting controller may be used in gas transportation systems.

SUBSTANCE: connecting controller contains electric interconnection, which connects a set of input ports to processor and memory. In accordance to invention, marked data may be grouped in time and space by means of central computer using attributes. Processor may utilize aforementioned data to constantly monitor, determine parameters and control the whole gas transportation system.

EFFECT: controller precisely distributes system events in time and space, using marked data for this purpose, resulting in increased efficiency of system, control over repairing of breakdown, capacity for planning of advance technical maintenance and routine maintenance.

5 cl, 6 dwg

FIELD: electrical communication networks, radio technique, computing technique.

SUBSTANCE: apparatus for controlling system of objects includes power conductor connected to autonomous electric power source; adapters connected between power conductor and objects. Adapters forming together with objects control circuits are programmed for setting timing of data receiving. Power conductor serves simultaneously for transmitting data. Adapters are made with possibility of taking noises into account. Adapter connected between power conductor and autonomous electric power source is made with possibility of simultaneous transmission of data between all other adapters while taking into account time moments of noise occurring and with possibility of regulating voltage of electric power source. Adapter for such apparatus is also offered in description of invention.

EFFECT: improved quality of control process.

2 cl, 7 dwg

FIELD: the invention refers to automated control systems.

SUBSTANCE: it may be used for management of industrial-technological processes of an enterprise of gas and oil industry with controlling inputs at the place of their origin. The invention allows to control the industrial-technological process at each management level together with industrial-technological indexes and control the values of evaluations of indexes of effectiveness which so, as the industrial-technological indexes are compared with permissible borders.

EFFECT: increases effectiveness of management due to operative local response at effectiveness reduction on a part of the industrial-technological process of the enterprise.

1 dwg

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