A method of manufacturing a powerful drop transistor

 

(57) Abstract:

Use: electronic semiconductor technology, in methods to create powerful silicon, DMAP transistor with a vertical structure. The inventive method is characterized by the presence of a new set and sequence of technological operations: capacity of an additional layer of silicon nitride on the polysilicon protective coating, forming a layer of thermal silicon dioxide protective coating of a certain thickness, the local growing an additional layer of thermal silicon dioxide of a certain thickness in the Windows of the protective coating over stokovye regions of the transistor cells before deposition of interlayer dielectric on the front side of the substrate, removing the protective cover from the front side of the substrate and forming a gate dielectric of thermal silicon dioxide, passivated phosphorothioate glass, and the gate electrode of the low-resistance polysilicon or refractory metal between additional local layer of thermal silicon dioxide. The technical result of the invention is to improve the resistance of these devices to the effects of ionizing radiation (primarily on the destination. 1 C. p. F.-ly, 5 Il., table 1.

The invention relates to electronic semiconductor technology, in particular to methods of creating powerful silicon, DMAP transistor with a vertical structure.

Known typical approach to the formation of the structure of the active region is a powerful DMAP transistors are adopted as the method-analogue, which is based on the following combination and sequence of the basic technological operations: forming a protective coating of thermal silicon dioxide and a low-resistance polysilicon (typically doped with phosphorus) on the front side of the original silicon PP+or RR+the substrate of the first conductivity type; etching Windows in the protective coating for the formation of transistor cells and a common gate node in the active region of the structure; the creation of a high-resistance layer of the substrate, each transistor cell shunt and channel regions of the second conductivity type and stokovoj region of the first conductivity type; deposition of interlayer dielectric (usually made of pyrolytic silicon dioxide, doped with phosphorus) on the front side of the substrate; opening contact Windows of the source and the bolt in the interlayer dielectric; the formation of the IU is illinoi side (U.S. patent 4970173 "Method of making high voltage vertical field effect transistor with improved safe operating area, published 13.11.1990, In this case, the gate node, which includes the gate dielectric of thermal silicon dioxide of a thickness of dunderand the gate electrode of the low-resistance polysilicon, is formed from a protective coating at the initial stage of the technological route and bypass, channel and ishikawae region of the transistor cells are created later by the sequential introduction of dopants into the substrate and subsequent diffusion redistribution of embedded impurities by using the previously formed gate node as a protective mask during ion implantation or diffusion spin impurities in the substrate. Finally implemented the so-called "drop structure with samozavestna relative to the source electrode of the gate", which is the Foundation of the modern series, but produced commercial devices, in which the induced channel of the first conductivity type formed on the ends of the channel regions adjacent to the gate dielectric, with the application of positive potential to the gate electrode. The disadvantage of DMAP structure manufactured by the method similar is the fact that it is alloyed shunt region (layer) beyond Kahn is me part of stock p-n junction, and, as a result, to decrease the density of the layout of structural elements in the active region of device structures and to reduce the breakdown voltage of the drain.

As the prototype is set to an improved version of the technological process of manufacturing DMAP transistor with a vertical structure, in accordance with which the shunt layer is formed after the creation of the channel regions of transistor cells and a fully fit within their borders (European patent A "Process for accomplishment of power MOS transistors with vertical current flow and transistor thus obtained, published 22.04.1992,) ceteris paribus prototype method provides a higher density layout of structural elements in the active region of DMAP structure and a higher breakdown voltage drain compared to analogue. However, prototype, and other known modifications of the prototype and how similar is not allowed to create powerful MOS-transistors with acceptable modern electronic equipment special purpose level resistance to ionizing radiation, which is a major drawback. Low radiation resistance of such devices due to the following reasons:

- influence and channel regions of transistor cells, leading to degradation of the initial properties of the gate dielectric;

- inability to use any additional measures to improve the radiation resistance of gate dielectric, in particular passivation gate dielectric phosphorothioate glass (in this case, when followed by passivation of high-temperature processes phosphorus diffuses from the glass in the gate dielectric to a greater depth, which leads to a sharp increase in leakage current gate to reduce the breakdown voltage of the dielectric, and often to its full breakdown);

- lack of use as the gate electrode instead of the polysilicon any other alternative material.

The purpose of the present invention improve the stability of these devices to the effects of ionizing radiation (primarily gamma radiation) to the level of requirements of modern electronic equipment for special purposes.

This objective is achieved in that in the known method of manufacturing drop transistor, including forming a protective coating of thermal silicon dioxide and polysilicon on the front side of the nom coverage for the formation of transistor cells and a gate node in the active region patterns, the creation of a high-resistance layer of the substrate channel regions of the transistor cells of the second type conductivity and inside the channel regions shunt layers of the second conductivity type and stokovyh regions of the first conductivity type, the deposition of interlayer dielectric on the front side of the substrate, the opening of the contact Windows of the source and the bolt in the interlayer dielectric, forming metal electrodes and source and gate on the front side of the substrate and the metal drain electrode on its rear side, in the protective coating on the polysilicon additionally grow a layer of silicon nitride, a layer of thermal silicon dioxide protective coating is formed thick , before deposition of interlayer dielectric in the Windows of the protective coating over stokovye regions of the transistor cells locally grown an extra layer of thermal silicon dioxide of a thickness of dLok2dunderthen remove the protective covering from the front side of the substrate and formed between the additional local layer of thermal silicon dioxide in place of the remote protective cover gate dielectric thickness dunderof thermal silicon dioxide, passivated phosphorothioate glass, and electtion shows that the inventive method is characterized by the presence of a new combination and sequence of technological operations: capacity of an additional layer of silicon nitride on the polysilicon protective coating; forming a layer of thermal silicon dioxide protective coating of a certain thickness; local growing an additional layer of thermal silicon dioxide of a certain thickness in the Windows of the protective coating over stokovye regions of the transistor cells before deposition of interlayer dielectric on the front side of the substrate; forming a gate dielectric of thermal silicon dioxide and the gate electrode of the low-resistance polysilicon or refractory metal between additional local layer of thermal silicon dioxide after removal of the protective coating on the front side of the substrate; a gate dielectric passivation phosphorothioate glass. Thus, the claimed method meets the criteria of the invention of "novelty."

Forming a gate node device structures after you create a channel, shunt and stokovyh regions of the transistor cells allows you to:

to avoid degradation of the initial properties of the gate dielectric and salvatory site;

- use as necessary as the gate electrode in addition to polysilicon and other alternative materials, including refractory metals and their silicides;

to hold the gate dielectric passivation phosphorothioate glass to associate coming from the gate electrode and formed directly on the gate dielectric under the action of ionizing radiation by moving charges in a stationary complexes;

and, as a result, to create the necessary prerequisites for the formation of radiation-resistant gate node device structures. Local growing an additional layer of thermal silicon dioxide in the Windows of the protective coating over stokovye regions of the transistor cells in the claimed method allows you to selectively remove the remaining after etching window of the cover from the front side of the substrate and to form on this site gate node of DMAP-patterns, that is, to make the instrument structure, different from DMAP structure with samozavestna relative to the source electrode of the gate", what a gate electrode on the magnitude of the error of combining may go beyond the gate dielectric and partially rasnow capacity dmop-structure At the local thickness of the layer of thermal silicon dioxide block over stokovye regions of the transistor cells are 2-3 times greater than the thickness of the gate dielectric dunder, that is, when specified in the claims conditions dLok2dunderadditional increase of input capacitance can be minimized.

Building an additional layer of silicon nitride on the polysilicon protective coating enables the formation of a local layer of thermal silicon dioxide in the Windows of the protective coating over stokovye regions of the transistor cells, that is, the protective coating in the present method in addition to its traditional role is to serve as a protective mask when serial unedr drop dopants in the substrate, and performs specific, not characteristic of the prototype function. The need to comply with the conditions where the thickness of thermal silicon dioxide under polyctenium protective coating, due to the fact that in the process of removing remaining after etching of the Windows part of the protective coating on the front side of the substrate, the geometric dimensions of additional local layer of thermal silicon dioxide in the Windows of the protective coating over stokovye regions of the transistor cells did not undergo significant changes. High selectivity when removing the remaining portion of the protective coating with the front storeyi new combination and sequence of technological operations provide the ability to create powerful silicon, DMAP transistor with a vertical structure, equivalent DMAP transistors with samozavestna relative to the source electrode of the shutter on marketable end options, but having compared to devices formed by the method prototype, enhanced functionality, namely a higher radiation resistance, that is, shows a new technical property. Therefore, the claimed method meets the criterion of "inventive step".

This invention also essential, as it provides a significant technical effect, namely:

- the possibility of increasing the radiation resistance of the commercially produced powerful commercial DMAP transistor with a vertical structure through improvement in the basic process of their manufacture;

- create a new generation of powerful silicon, DMAP transistors and based on them - a new generation of electronic equipment that meet current and future requirements for weight and size parameters, power parameters, reliability, durability and resistance to special factors.

Fig. 1, 2, 3, 4, 5 shows the major steps in making a powerful silicon, DMAP transistor with a Vert is Delica with lower alloyed and low-alloy upper layers of the first conductivity type;

2 is a three-layer protective coating;

3 - layer thermal silicon dioxide protective coating;

4 - layer polysilicon protective coating;

5 - layer silicon nitride protective coating;

6 - through window in the protective coating;

7 channel region of the transistor cells of the second type conductivity;

8 - shunt alloy layer in the transistor cells of the second type conductivity;

9 - ishikawae region of the transistor cells of the first type conductivity;

10 - local thermal layers of silicon dioxide in the Windows of the protective coating over stokovye regions of the transistor cells;

11 - gate dielectric of thermal silicon dioxide, passivated phosphorothioate glass;

12 is a gate electrode of the low-resistance polysilicon or refractory metal;

13 - interlayer dielectric;

14 - pin open source opened in the interlayer dielectric and the local layer of thermal silicon dioxide;

15 - metal source electrode;

16 - electrode metal flow.

Example

The proposed method was used in the manufacture of powerful switching p-channel drop transistor with a vertical structure of the front side of the original silicon PP+the substrate (1) with the orientation of the crystallographic axes in the plane (100), consisting of the lower alloyed p+-layer with a resistivity of p+l= 0.005 Ohm/cm and the upper epitaxial p-layer withp= 5...6 Ohm/cm and a thickness of dp=15...17 μm, in the active region of device structures (chips, crystals) form a protective coating (2), consisting of a layer of silicon dioxide (3) the thickness of the layer of polysilicon (4) thickness of 0.3...0.6 μm and a layer of silicon nitride (5) thickness of 0.2. ..0.3 microns - Fig.1 (peripheral part of the device structures with elements of regional protection stock p-n junction not shown). A layer of silicon dioxide (3) was formed by thermal oxidation of the silicon substrate in an environment of dry oxygen or water vapor at a temperature of 900... 1000oWith, and polysilicon (4) and silicon nitride (5) were obtained respectively from monosilane mixture and the mixture dichlorsilane and ammonia at a temperature of the working zone of the furnace 6255oC and 770+10oC. Then, by photolithography in protective cover (2) was exposed through a window (6) in the shape of a square 16x16 μm, separated from each other at a distance of 16 μm, and the successive introduction of impurities into the substrate through the window (6) in the protective coating with subsequent diffusion processing is camping the p-channel region (7) of transistor cells with surface resistance Rsp= 40050 Ω/ and a thickness of dp= 30,5 μm and the inside of the channel regions - shunt R+-layer (8) with surface resistance Rsp+= 8010 Ω/ and a thickness of dp+=1,20,4 μm and ishikawae p+region (9) with Rs+= 255 Ω/ and a thickness of dp+l=0,450,1 ám Fig.2 (each instrument structure, size 4,h,32 μm contained about 14,000 transistor cells). Channel p-region formed by implantation of boron ions with an energy of E=50...100 Kev and a dose of Q=12...16 ICC/cm2with the subsequent distillation is introduced impurities at T=1150oWith over 250 minutes in a nitrogen atmosphere, and oxygen. Shunt layer was formed by diffusion of boron from the boron nitride at T=925oWith over 40 minutes, followed by diffusion redistribution of embedded impurities at T=900 950...oWith over 30...40 minutes in an atmosphere of nitrogen and oxygen. Ishikawae p+-the field of transistor cells formed by introducing arsenic ions with an energy of E=20...25 Kev and a dose Q=800...1000 ICC/cm2with the subsequent distillation is introduced impurities at T=1000oWith over 25. . . 30 minutes in oxygen atmosphere. After that, thermal oxidation of the silicon substrate (1) in a medium dry oxygen and water vapor at T=950 1050...oWith Windows (6) above stokovye areas t>is OK= 0,3. . . 0.5 µm (Fig.2), the layer-by-layer etching of silicon nitride (5), polysilicon (4) and silicon dioxide (3) remove remaining after etching window (6) of the cover (2) from the front side of the substrate (Fig. 3), thermal oxidation opened between additional local layer of thermal silicon dioxide (10) parts of the silicon substrate at T=950... 970oWith in an environment of dry oxygen and water vapor in place of the protective coating formed gate dielectric (11) the thickness of the diffusion of phosphorus from metaphosphate aluminum at T=950... 970oWith a nitrogen atmosphere was passivatable gate dielectric phosphorothioate glass (Fig.4 and 5 FSS not shown) on the front side of the substrate besieged magnetron molybdenum with a thickness of 0.2...0.25 μm or doped with phosphorus polysilicon thickness 0,6...0,7 µm and photolithography were formed from them over the gate dielectric, the gate electrode (12) instrument patterns (Fig. 4), was applied on the front side of the substrate interlayer dielectric (13) with a thickness of 0.8...1.4 µm of pyrolytic silicon dioxide, doped with phosphorus (Fig. 4), was opened in the interlayer dielectric (13) and the underlying additional local layer of thermal silicon dioxide (what Elenium on the front side of the substrate besieged the aluminum layer with a thickness of 2 to 4 microns and a photolithography formed from it the source electrode (15) of the instrument structure and contact pads of the source and gate (Fig. 5 not shown) for connection to the instrument structure (crystal, chip) external aluminum conclusions.

A drain electrode (16) on the rear side of the substrate formed with the brazing of the crystal to heat the surface of the sintered body CT 57 at T=400...450oWith a nitrogen atmosphere using a gold strip with a thickness of 15...20 μm (Fig.5).

Using the same set of photomasks and the original silicon substrate of the same liposomial were additionally produced samples of high-power p-channel DMAP transistors in the prototype method, as well as by the present method, but without the intermediate layer of polysilicon protective coating. Electrophysical parameters and dimensions of structural elements of the device structures were identical to those described above. In dmop-transistors manufactured according to the method prototype, gate node formed at the initial stage of the technological process of the protective coating, which consisted of thermal silicon dioxide thickness and doped with phosphorus layer of polysilicon with a thickness of 0.5. ..0.6 microns, with a layer of thermal silicon dioxide is formed exactly the same as the gate dielectric in the present method, but did not piscivorous fosforos the elk possible as for subsequent passivation of high temperature (>1000o(C) the process of forming channel regions of transistor cells phosphorus deeply penetrated into the gate dielectric, which led to a sharp decrease of the breakdown voltage of the dielectric, and a sharp increase in leakage currents of the gate. The use in the claimed method of the protective coating without polysilicon was possible, however, difficulties arose with the implementation of the local thickness of the layer of thermal silicon dioxide over stokovye regions of the transistor cells more than 0.3 μm.

Electrical parameters of DMAP transistors manufactured by the present and the method prototype, shown in the table. All devices are made using the same set of masks, were mounted in a hermetically sealed metal-ceramic housing with use strip conclusions and flat flange type CT-57, had a total length (width) of the channel is about 105 cm and identical marginal protection stock p-n junction. The table shows that for a comparable electrical parameters produced by the present method the devices significantly surpass DMAP transistors manufactured according to the method prototype, resistance to specify gamma radiation dose of 105happy.

Technical and economic efficiency of the proposed method in comparison with the prototype consists of:

a) create a powerful silicon, DMAP transistors, equivalent as possible on the final parameters of modern commercial DMAP transistors with samozavestna relative to the source electrode of the gate, but with a substantially higher radiation resistance, i.e. enhanced functionality;

b) the possibility of increasing the radiation resistance of the commercially produced powerful commercial DMAP transistor with a vertical structure through improvement in the basic process of their manufacture;

) create a new generation of powerful silicon, DMAP transistor with a vertical structure on the basis of a new generation of electronic equipment that meet current and future requirements for weight and size parameters, power parameters, reliability, durability and resistance to special factors.

1. A method of manufacturing a powerful drop transistor, including forming a protective coating of thermal silicon dioxide and polysilicon on the front side of shodokai for the formation of transistor cells and a gate node in the active region patterns, the creation of a high-resistance layer of the substrate channel regions of the transistor cells of the second type conductivity and inside the channel regions shunt layers of the second conductivity type and stokovyh regions of the first conductivity type, the deposition of interlayer dielectric on the front side of the substrate, the opening of the contact Windows of the source and the bolt in the interlayer dielectric, forming metal electrodes and source and gate on the front side of the substrate and the metal drain electrode on its rear side, wherein the protective coating on the polysilicon additionally grow a layer of silicon nitride, a layer of thermal silicon dioxide protective coating is formed of a thickness of dSiO20,3 dunderbefore deposition of interlayer dielectric in the Windows of the protective coating over stokovye regions of the transistor cells locally grown an extra layer of thermal silicon dioxide of a thickness of dLok2dunderthen remove the protective covering from the front side of the substrate and formed between the additional local layer of thermal silicon dioxide in place of the remote protective cover gate dielectric thickness dunderof thermal silicon dioxide, pasilla.

 

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