A method of manufacturing a solid-state device
(57) Abstract:The invention relates to semiconductor electronics and can be used in the manufacture of solid-state devices and their electrodes. The method includes forming contact pads (CP) on the substrate (P), coating the resulting structure of the dielectric layer (D), delete D over KP and attaching to the CP of the conductor. Additionally, the method provides for abandonment is not filled with the material of the Windows in KP during its formation and abandonment On Windows if you remove it over KP. The several conditions on the square Windows in the CP and specific friction materials with each other, allows increasing the mechanical strength of the structure "CP - P" due to the interaction of the material with KP D in Windows. The invention allows to increase the breakout pads attached to the conductor from the substrate, which increases the reliability of the device. 2 Il. The invention relates to semiconductor electronics and can be used in the manufacture of solid-state devices and their electrodes.A known method of manufacturing a solid-state device, comprising forming on the surface of the substrate contact pads of the conductive materialand to passivate the surface of the substrate .Significant viscosity of the compound when filling, deformation during solidification, is different from the substrate material and guides thermal expansion coefficient lead to additional mechanical stress on the contact and the conductor pads, which reduces the reliability of the device. Maintaining reliability characteristics by increasing the area of contact of the conductor with ground forces to use conductors of large cross-sectional area. This leads to increase the area of contact pads and its parasitic capacitance. These factors limit the application of this method.The closest set of features is a method of manufacturing a solid-state device , which also form the contact area of conductive material on part of the substrate surface, then cover the surface of the substrate and contact pads pestiviruses dielectric layer, the specific (per unit area) adhesive force with which the substrate is greater specific force of adhesion with the substrate contact pads, then remove the insulator on the contact pad and attach to the pad conditioner, breakout which is rebora choice of cross-sectional area of the conductor is determined only by the density flowing through it current, to reduce the cross-sectional area of the conductor and, therefore, the area of the contact pads and its parasitic electric capacity.Small adhesive force contact area with the substrate often leads to exfoliation that removes the device from the system.The claimed invention is intended to increase the efforts of the separation pad from the substrate, and in its implementation may be improved in reliability of the device.The above task is solved in that in the known method of manufacturing a solid-state device, comprising forming on part of the surface of the substrate contact pads of conductive material, coating the surface of the substrate and the pad dielectric layer, the specific strength of adhesion with the substrate more specific force of adhesion with the substrate contact pads PL-premoving dielectric over the contact pad and attach to the ground conductor, the specific adhesive force with which the material sitemmorePL-paccording to the invention during the formation of contact pads within its area leave at least one window, empty conductive material, and when in the AMI area pads inside the external borders of the SPLsatisfy the conditions
where Rabout- the perimeter of the window; dPLthe thickness of the pad;PL-d- the specific strength of coupling pads with dielectric; Smoand Sm- contact area of the conductor, respectively, with the dielectric in the Windows to the material of the contact pads;d- the specific strength of coupling a conductor with the dielectric Windows.Obtained by carrying out the invention the technical result, namely improving the reliability of the solid-state device, is achieved due to the fact that the presence of pad boxes filled with a dielectric having a relatively large specific bond strength with the substrate material and the material of the pad, under the conditions (1) and (2) leads to an increase in the efforts of the separation pad from the substrate.Thus, in the method prototype force of the separation pad from the backing sheet
F1= SPLPL-p. (3)
In the proposed method the force of the separation pad from the backing sheet
F2= (SPL-S0)PL-p+SbPL-d, (4)
the nd with the dielectric. To achieve a positive effect should be condition
which is ensured by the inequality (1) is the first condition of the claims.In the proposed method window in the pad can get into the area of the contact pad with a conductor that causes compared with the prototype breakout forces f1of the conductor to the contact area because of less, in most cases, the specific strength of coupling a conductor with dielectricdin the window compared to the percentage cohesive strength of the conductor material padsm. To this decrease did not hinder the achievement of positive effect obtained in the proposed method the power of separation of the conductor from the contact pads with Windows
must be greater than the force of the separation pad from the substrate in the prototype, i.e.F1< f2.This condition is ensured by the inequality (2) is the second condition of the claims.In Fig.1 shows a General top view of the solid-state device, the manufacture of which implemented the proposed method, Fig.2 - section ecogeochemistry in boxes 3, Explorer 5.When the implementation of the proposed way leave the window 3 in the area 2 and the dielectric fill them with implementation of the conditions (1) and (2), the reduction of the friction pad with the substrate 1 due to losses in the area of their grip on the amount of square Windows abundantly compensated by the force of adhesion sites with the dielectric, with whom she is in contact with the side surfaces of the 3 Windows. The breakout pads 2 from the substrate 1 increases and approaches the breakout of the conductor 5 from the platform 2. Despite a possible reduction in the strength of coupling a conductor with ground, this power is subject to the condition (2) exceeds the force of adhesion sites with the substrate in the device manufactured by the method of the prototype. All this leads to an increase efforts fracture patterns "background - space - Explorer" and ultimately, to improving the reliability of the solid-state device.Example. When implementing the invention in the process of manufacturing the solid-state device on the surface of silicon oxide, thermally grown on a silicon substrate, an aluminum layer thickness of 2.5 μm was formed on 8 identical pads rectangular shape with dimensions of h μm2. Within each square with the distance between adjacent edges of the Windows in rows of 4 μm and inter-row distance of 4 μm. In another implementation of the invention within each site was formed 96 such as Windows, arranged in 12 rows and 8 boxes in a row with a distance between adjacent edges of the window 6 μm. Surface of the substrate together with the grounds were covered with pyrolytic silicon oxide, which after removing it from the sites remained in boxes. For each site method thermocompression joined guidewire diameter of 50 μm. The average pullout force platform measured by highly sensitive dynamometer, was for the first implementation 15,1110-3N, for the second - 13,4510-3N when the slew rate pull force of no more than 10-3N/S. For comparison, the average force of the separation pad in the form of a solid rectangle of the same size was 11,3710-3H under the same conditions of measurement.LITERATURE
1. The design and technology of integrated circuits. / Koledov L. A., Volkov, C. A., N. Dokuchaev.And. and other edited Kolegova L. A. - M.: the High. HQ., 1984, S. 183.2. Ibid - S. 170 and 171 prototype. A method of manufacturing a solid-state device, comprising forming on part of the surface of the substrate contact pads of conductive material, the surface coating sing friction with the substrate contact padsPL-premoving dielectric over the contact pad and attach to the ground conductor, the specific adhesive force with which the material sitemmorePL-p, characterized in that when forming the contact pads within its area leave at least one window, not filled with a conductive material, and deleting dielectric over the contact pad leave it in the box, with a square window Saboutand in common with Windows square pads inside the external borders of the SPLsatisfy the conditions
where Rabout- the perimeter of the window;
dPLthe thickness of the ground;
PL-d- the specific strength of coupling pads with dielectric;
Smoand Sm- contact area of the conductor, respectively, with the dielectric in the Windows to the material of the contact pads;
d- the specific strength of coupling a conductor with the dielectric Windows.
FIELD: micro- and nanoelectronics, micro- and nanomechanics where insulated conductors are used.
SUBSTANCE: proposed method for filling pockets in solid body with conducting material includes coating of solid-body surface, bottom, and side walls of mentioned pockets with first layer that functions as barrier material preventing diffusion of mentioned conducting material in solid body; application of second layer onto first one that functions as wetting layer for conducting material; application of third layer by way of physical or chemical deposition onto third one from gas phase that has in its composition mentioned conducting material; coating of third layer with fourth one that also incorporates conducting material; melting of conducting material by heating and profile leveling; material melting by heating is conducted after applying third layer and fourth layer is applied by any method of physical deposition from gas phase, chemical deposition from gas phase, chemical deposition from solution, electrochemical deposition, or chemical-mechanical deposition.
EFFECT: facilitated procedure, enlarged functional capabilities.
12 cl, 17 dwg
SUBSTANCE: invention is attributed to microelectronics and can be used in production of semiconductor devices and integral circuits. Essence of invention: in the method of attaching silicon chip to chip holder, chip seating surface is successively sputtered with two titan-germanium metals, and chip to chip holder soldering is carried out at temperature of 280-300°C.
EFFECT: improvement of chip with chip-holder contact reliability and stability of attachment process.
SUBSTANCE: method involves notching in bulk of a silicon wafer and silicone removing from the wafer back to uncover notch bottoms. Notching enables silicone pattern formation to represent hollow cell walls that is followed with wall-through oxidation to form a dielectric SiO2 conduit system. Silicon removing from the back of the wafer can be conducted by the deep plasma etch process.
EFFECT: high strength of the insulating element which can be used for manufacturing various MEMS devices in bulk of a standard silicon wafer.
2 cl, 13 dwg
SUBSTANCE: in manufacturing method of multi-level copper metallisation of VLSIC, which involves application operations of metal and dielectric layers, photolithography and selective etching of those layers, chemical mechanical polishing of dielectric layers, to plate of silicium, which is coated with dielectric material with vertical conductors of underlying structure, which protrude on its surface, there applied is multi-layered conducting film consisting of adhesive barrier, etched and auxiliary layers; grooves are formed in auxiliary layer before etched layers by electrochemical method; copper horizontal conductors are grown inside grooves in open sections of etched layer till grooves are fully filled; the second auxiliary layer is applied to surface of plate, and in that layer holes are made to the surface of horizontal copper conductors; vertical copper conductors are grown by electrochemical method in open sections of horizontal conductors till holes for vertical conductors are fully filled; then, auxiliary layers are removed; conducting layers between horizontal copper conductors are removed; dielectric layers are applied to surface of the plate by smoothing and filling methods, and then dielectric material layers are removed above vertical conductors by means of chemical and mechanical polishing method.
EFFECT: improving quality of copper conductors.
16 cl, 11 dwg, 1 tbl
FIELD: instrument making.
SUBSTANCE: invention relates to semiconductor devices production process, in particular to technology of making contacts with lowered resistance. In method of semiconductor device making contacts are formed on basis of platinum. For this film of platinum with thickness of 35-45 nm is applied by electron-beam evaporation on silicon substrate, heated prior to 350 °C, at rate of deposition of 5 nm/min. Then heat treated in three stages: 1 step is carried out at temperature of 200 °C for 15 minutes, 2 step is carried out at temperature of 300 °C for 10 minutes and 3 stage is at 550 °C for 15 min in forming gas, with mixture of gases N2:H2=9:1.
EFFECT: proposed method of semiconductor device making provides reduced contact resistance, high technological effectiveness, improved parameters of devices, high quality and yield.
1 cl, 1 tbl
SUBSTANCE: invention relates to the field of semiconductor production technology, namely to a technology of low-resistance silicide layers formation. The method of semiconductor devices manufacture includes formation of an amorphous layer by silicon ion implantation on the silicon plate with the energy of 50 keV and dose⋅ of 5⋅1015 cm-2, at the substrate temperature of 25°C. Prior to the palladium layer application, the substrate is sequentially etched in nitric, sulfuric and hydrofluoric acid, then washed with deionized water. The palladium layer is applied at a temperature of 25-100°C, with a thickness of 0.1 microns at a rate of 1.5 nm/sec. After application of the palladium layer, heat-treated under vacuum is conducted at a pressure of (2-8)⋅ 105 mm Hg, temperature of 250°C for 20-30 minutes. As a result, palladium silicide Pd2Si is formed.
EFFECT: invention reduces drag, improves process efficiency, improves parameters, improves quality and increases yield percentage.
SUBSTANCE: method of increasing the threshold barrier voltage of a transistor based on gallium nitride (GaN), which includes creating gate p-GaN mesa on the surface of the silicon wafer with epitaxial heterostructure of GaN/AlGaN/GaN type, inter-instrument mesa-isolation, forming ohmic contacts to the areas of the transistor drain and source, forming a two-layer resistive mask by lithographic methods, cleaning of the surface of the semiconductor, deposition of thin films of gate metallization, removing of the plate from the vacuum chamber of the evaporator, removal of the resistive mask, prior to the evaporation of thin films of gate metallization the plate is subjected to treatment in an atmosphere of atomic hydrogen for t=10-60 seconds at a temperature of t=20-150°C and flow density of hydrogen atoms on the surface of the plate, equal to 1013-1016 at. cm-2 c-1.
EFFECT: increase in the threshold barrier voltage of the GaN transistor when applying barrier metal films to the p-GaN gate area with a high electronic work function.
5 cl, 3 dwg