Circuit device with a number of electronic circuit components

 

(57) Abstract:

The invention relates to a circuit device with a number of electronic circuit components, which can be translated to its original state. The technical result is the ability to return the information content of the selected circuit components on the value of a logical "zero" without increasing circuit cost and area schemes. The device contains an electronic circuit components, the circuit of the sampling gate circuit, an address decoder, a control scheme that allows the switch, a switching transistor, a sensor device. 3 C.p. f-crystals, 2 Il.

The invention relates to a circuit device with a number of electronic circuit components, operating condition which can be translated to its original state, accordingly, the erase state, in which the content of the circuit component is equal to a logical "zero".

For various reasons it may be necessary to erase individual registers or all of the contents of the semiconductor memory device integrated on a plate of a microprocessor or other circuit component. When using cards with microprocessor-based is able to provide active protective measures, to prevent reading of sensitive data, such as hackers, even in cases where a disabled clock software of the microprocessor. When including all registers of the microprocessor, as a rule, pre-load a certain amount, in which data processing is replaced with different information content, which may also contain private or personal data. To preload registers are given a certain amount they are usually separately stipulated by the reset input. This reset input leads, for example, to the switching transistor, which causes the subject to remember the value of the register to a specific level. In the semiconductor storage device, random access with a large number of memory cells when the supply of a separate reset input of each memory cell would significantly increase the required space required. In addition, this principle requires high your power to reset the mass storage device, so both must be managed h transistors. Such a device would be contrary both to wish to get the maximum possible density integration Polop the eat control. In addition, as an active protective measures against unauthorized access to private data, you can also use that with the microprocessor sequentially addressed all necessary memory and then each is considered to be the memory cell is rewritten to the value of a logical "zero". However, this solution is not always successfully, to prevent unauthorized access to information, so as to delay the clock obespechenie, the microprocessor stops and is unable to perform the job.

From US-And 4928266 known circuit device to activate automatically return the information content of the selected circuit components on the value of a logical "zero" containing a number of electronic circuit components made with the possibility of transfer of the operating status via a given Manager or the information signal supplied to the respective circuit component in the erase state, in which the information content of circuit component takes a value of logical "zero", and for sequential time control of all circuit components provided the sampling frame, running after appoointed the number of circuit components, each trigger stage is configured to activate or trigger for issuing a control signal to the corresponding circuit component using the unlocking signal is generated immediately prior unlocking step, and unlocking stage after the filing of a control signal to the corresponding circuit component is made with the possibility of issuing an enabling signal to control or activate directly the next trigger level.

In EP-A 0574094 disclosed chain "available from flashing" schemes, which are administered sequentially with a time delay, with the first one activates the starting signal is supplied to the starting circuit. In addition, the source reveals a simplified version of "free from flashing" of the schema that contains a ring oscillator, which performs the function of creating the clock pulses, which serve to limit the time of erasing, and a counter for counting the number issued by the clock pulses, and the counter m-bits for counting the number of groups of memory cells.

In WO-A 8202274 disclosed a device for automatically erasing the information content of the data banks with special willcalifornia in the data Bank and then in the second stage erase all programming information in the data Bank. This is a special circuit device is used primarily to erase the data Bank before the unauthorized access to or before an act of sabotage without physical destruction. Circuit device has activated the emergency button bistable trigger output signal which activates the address generators controlled by system clock cycle, i.e., all addresses are generated, which can be related devices remembering information. The address generators are parallel to each other.

In DE-A 4135767 shows a device for protecting data from unauthorized access in a control block operating at a coin-operated machines. When you try opening protects the control unit housing this action is detected by means of sensors. Sensors that capture mechanical or chemical influences, as well as the change in ambient temperature and operating voltage, is connected with the sensor device, which has its own power. When attempting penetration into the control unit deletes data related to data storage parts with schema erase.

The basis of the invention lies task is to create a schema specified is performed independently return the information content of the selected circuit components on the value of a logical "zero" without a substantial increase in the required area or circuit costs.

The problem is solved in that in a circuit device to activate automatically return the information content of the selected circuit components on the value of a logical "zero" containing a number of electronic circuit components made with the possibility of transfer of the operating status via a given Manager or the information signal supplied to the respective circuit component in the erase state, in which the information content of circuit component takes a value of logical "zero", and for sequential time control of all circuit components provided the sampling frame, running after start automatically and containing series-connected to each other unlocking steps the number which corresponds to the number of circuit components, each enabling circuit is configured to activate or trigger for issuing a control signal to the corresponding circuit component using the unlocking signal is generated immediately prior unlocking step, and unlocking stage after the filing of a control signal to the corresponding circuit companiesa her stage unlocking, according to the invention, each unlocking step includes the gate circuit consisting

from the enabling switch is made with the possibility of inclusion by enabling signal applied to line enabling signal when the enable signal has a logic level "unit", and with the possibility of locking at the level of the enabling signal equal to a logical "zero",

from the switching transistor with the appropriate governing output connected with the allow switch

- from the control Manager o priklauso of the driver transistor made with the possibility of opening the switching transistor to control the respective circuit component when the driver signal at the input of the driver is equal to a logical "one", and with the possibility of locking the switching transistor when the driver signal at the input of the driver is equal to a logical "zero",

moreover, the circuit device is manufactured with the capability of issuing from the switching transistor when it is open, unlocking signal that controls the return or erasing the information content of the circuit component to the value of a logical "zero", and then issue the drive is To erase the elements of the storage device provided by the data bus, which provides information signal for recording the information content in the elements of the storage device when activation of the second control circuit in the elements of the storage device is written using included before her opening stages of the first drive circuit is a logical "zero" on the data bus, and thus the elements of the storage device are in the erased state.

The basis of the invention based on the idea to provide for erasing information in a separate circuit components, such as registers and memory cells of semiconductor memory devices independently controllable drive circuit, which works similarly to known mechanical chain of dominoes. After the initial shock management scheme according to the invention operates separately and completely independently of external clock security control device, such as a microprocessor, which can be stopped in case of unauthorized access, so that it is able calmly to read the private information, in particular, are especially vulnerable static semiconductor saponi the supply of unacceptable deviations from the permitted operational status of the control device or circuit component, creates an enable signal, which gives rise to a chain of dominoes, i.e. the control scheme. As a response to the issue of enabling signal is reset or erased by first unlocking step, which involves an enabling signal, the first circuit component selected from a variety of circuit components of circuit devices, which should be erased, for example a battery or a register of the microprocessor, and then, once powered the first unlocking step, you create the following, the second enabling signal, which opens the next stage unlocking, for example, to activate the address decoder and the subsequent erase group addressed memory cells of the semiconductor memory device. This process is followed by other enabling signals in accordance with the desired number subject to the control circuit components.

In a preferred embodiment of the invention can be provided that each circuit component is attached to the corresponding single opening degree control pattern.

In a preferred embodiment, the circuit device according to the invention provides the output signal for recording information in the circuit components. After the opening of the circuit component with the given opening degree control pattern is recorded, for example, circuit components on the data bus is a logical "zero", so that the circuit component is translated thus in the erased state. In a particularly preferred embodiment, for example, on all lines of the data bus is supplied to a logical "zero"; with the help of a control circuit are opened one after another in time of the individual circuit components which are connected with the data bus in response to the opening written sequentially in time the value of a logical "zero" with the data bus in a separate circuit components. In contrast to the known from the previous prior art solutions, in which each circuit component, respectively, each cell of the storage device requires a large area of the reset transistor to create a sufficiently large signal reset circuit device according to the invention has the advantage that it requires a much smaller area. Compared to other known prior art solution, in which the address detector equipped with an additional circuit, which allows Tolsa your power and data bus for simultaneous translation of all cells of the storage device is a logical "zero", circuit device according to the invention has the advantage that the data bus must provide a significantly lower your power as circuit components, respectively, of the memory cells of the memory device are controlled in sequence and not simultaneously for each other.

In another preferred embodiment of the invention with a particularly simple circuit implementation of the control scheme provides that an enabling signal is issued by the last opening degree of the second control circuit, is supplied via the feedback loop to the input of the first opening stages of the second drive circuit.

In a particularly preferred embodiment of the invention provides that the circuit components are memory storage devices of one register and/or programmable semiconductor memory device. This gives the advantage that the unlocking stage, attached to the cells of the memory device register are included before unlocking levels that are assigned to the memory cells programmable semiconductor memory device. Thus, after starting the control scheme using the enabling signal is of Istria support your power data bus. This sequence of unlocking steps has the advantage because feeding signals to the memory cells of a dynamic semiconductor memory with random access (RAM) only with additional circuit cost can be recognized, when fully worked separate opening degree control pattern; due to the dependence of addressing a memory cell or group of memory cells from the corresponding previous addresses cannot be uniquely determined, which can be managed groups is actually the "first" or "last".

Another advantage of the circuit device according to the invention by analogy with a mechanical chain of dominoes is that for a sequence in time management of individual unlocking steps necessary only the respective inverter stage unlocking, and, in addition, each preceding stage unlocking cycles, respectively actuates the appropriate next step.

In a particularly preferred embodiment of the invention provides that the start of the flow diagram is on their own by supplying the enabling signal to the first unlocking story given circuit provided in the device control device for electronic control of one or more circuit components and which determines the deviation from the permitted operational status of the controller and in response to the deviation from the permitted operational status outputs an enable signal to the first enabling step for self-activation of the control circuit. For a simple circuit implementation can be provided that the sensor circuit is given clock support and/or supply of the supply voltage control device and measures the deviation of the feeding stroke of the working cycle and when there is a deviation of the operating voltage and/or working stroke generates an enable signal and outputs it to the first enabling step for self-starting, respectively activating the drive circuit. To do this, touch the scheme may have a diagram of the voltage detector, which measures the excess or decrease of the supply voltage specified upper, respectively the lower limit values of the supply voltage. On the other hand, a sensor circuit may have a diagram of the frequency detector, which measures the excess or decrease the supply of tact specified upper, respectively the lower limit values of the supply cycle. Thus, it is possible to detect unauthorized access to private data, for example in the presence of very high or very low voltage or too high or too low frequency clock cycle, and used to automatically start the drive circuit.

In order obesience content subject to the control circuit components, you can use regulation to provide a stop continuing releases are subject to the effects of circuit components at a very low driver power data bus. Therefore, in a preferred embodiment of the invention is provided preferably attached to the control scheme the control scheme, which is incorrect when the data bus, respectively, the data driver provides a new activation of the control circuit. Only after reaching the steady state continues the consistent return to its original state information content of all circuit components, i.e., the control circuit stops, and then re-activated. In this case a simple circuit implementation can be provided that the control scheme takes the information signals from the data bus, and measures the deviation from the zero value for short-term shutdown and then a new independent activation of the control scheme.

In a particularly preferred embodiment provides that at least one of the circuit components is performed on a semiconductor substrate of a semiconductor storage device with proizvol number produced recordings and read the content located in the flow path or selection information, and attached semiconductor memory device enabling the level of the control scheme directly affects the address circuitry for addressing at least one memory cell, the circuit inlet and information selection switches to the issuance of zero values on the addressed memory cell. For this purpose, at least part of circuit components may be combined into a group of memory cells of a semiconductor memory device, which with the help of a control circuit can be independently addressed each other to reset the information content of the memory cells on the value of a logical "zero". Based on the available schemes decoding conventional semiconductor memory device, random access sequential addressing by using the unlocking of the speed control circuit according to the invention is very simple. In the existing semiconductor memory devices, random access on the basis of the control circuit according to the invention there is no need to create additional, in some cases, complex logic components. For control, catoche common to all memory cells of the control scheme with the appropriate number of unlocking steps. Only after will be addressed first group of cells, i.e., when the corresponding lines of said memory cells are in an active state, is addressing the next group of cells of a semiconductor memory with random access. Thereby limiting the capacitive load of the data bus. If in contrast, all of the registers and the memory cells of semiconductor memory devices would have opened at the same time, the data bus should have a much greater your ability to allow rapid overturning in the worst case all memory cells of the semiconductor memory device.

In a particular preferred application of the circuit device according to the invention, it refers to is located inside the housing of an electronic card of a semiconductor integrated circuit, which along with the semiconductor memory device, random access contains other functional units, in particular, the constant of the semiconductor storage device and/or electrically erasable semiconductor memory device.

Dalmeny using drawings, showing:

Fig. 1 is a block diagram schematic of a device with a control scheme according to the exemplary embodiment of the invention;

Fig.2 is a block diagram schematic of the control attached to the control scheme of Fig. 1.

It is shown in Fig.1 and 2 an exemplary embodiment of the circuit device 1 according to the invention has a number of electronic circuit components 2, 3, 4 and 5, the operating status can be changed by a given control signal 6, 7, 8 and 9 are supplied to the respective circuit components 2 to 5, in the initial state, respectively, in the erase state, in which the information content of the corresponding circuit component 2 - 5 assumes the value of logical "zero". Circuit component 4 contains performed on the semiconductor substrate of the semiconductor storage device with random access (static RAM) with the first group of memory cells 10 and 11. Circuit component 5 contains all executed on the same semiconductor substrate of a semiconductor storage device with random access (static RAM) with the second group of memory cells 12 and 13. Memory cell 10 to 13, made with the possibility of addressing by the address circuit 14 in the form itself investedin) and other address lines 17 (address bits from two to n) of the address bus 18, for any number of records and reads using supplied to the 20 data bus with 8 lines DB [0] DB [7] data to eight bit data schema 19 input and retrieval of data, as is known in the art and therefore does not require a detailed description. Circuit component 2 is, for example, a register for temporarily storing data, the circuit component 3 is, for example, also used for temporarily storing data of the battery, in this case 2 and the battery 3 also given integral is performed on the semiconductor substrate to the microprocessor (control device), which for clarity is not shown in Fig.1 and 2. Decoding the addresses of the memory cells 10 to 13 is performed using 8 lines 21, 21', 22, 22', 23, 23', 24, 24', which is electrically connected to the address decoder 14. Along with is shown in Fig.1 schematic components 2 to 5 can be provided by any other circuit components, which can also be translated by means of the control signal in the initial state, respectively, in the erase state in which the content takes the logical value "zero".

To control the content of all circuit components in EIT is 5, 25A with series one after another unlocking steps 26, 27, 28, 29, the number of which corresponds to the number of eligible control circuit components, each circuit component 2 - 5 attached to the corresponding trigger stage 26 - 29 of the control circuit 25, 25A respectively. Each unlocking step includes the gate circuit consisting of the switching transistors 30, 31, 32, 33 and drivers 38, 39, 40, 41, Directors of their respective control pins 34, 35, 36, 37 switching transistors 30 and 33, the input of which is fed the appropriate driver signal 42, 43, 44, 45. When the level of the driver signal equal to the logical value "unit" opens respectively controlled switching transistor 30 is 33, while at a level equal to the value of a logical "zero" corresponding to the transistor conducts. Each trigger level 26 - 29 contains further permitting the switch 47, 48, 49, 50, which are enabled by the enabling signal 53 is supplied through line 52 enabling signal as soon as the enable signal has a logic level "unit", and at the level of the enabling signal 53, is equal to the value of a logical "zero", is closed. To activate the drive circuit 25 thus hamnah components 2 - 5 is a logical "zero" enable signal is transferred to the logical value "unit". When the enabling signal 53 at the level of logical "zero" control logic 25 is deactivated.

Consisting of two circuit parts 25 and 25A management scheme according to the exemplary embodiment operates as follows. To activate the drive circuit 25 is given an enable signal 53, i.e., the level of the enabling signal 53 from the level of the logical "zero" is translated into a logic level "units" and he unlocks the switching transistor 30, the first unlocking step 26 to the control circuit component 2. Using issued switching transistor 30 unlocking signal 6 is triggered register 2 and the activation of the reset, respectively erasing content on the value of a logical "zero". This is followed by a driver signal 43 in line 54, which is activated by the second unlocking step 27 of the control circuit 25 and erased the content triggered from the second unlocking step 27 circuit component 3. After unlocking stage 27 generates a driver signal 46a in the line 46 through the valve 62 is NOT-AND the inverter 63, which opens all other the storage device 10 is 13 through the address decoder 14 is one of the memory cells 10 - 13 always remains active.

To explain the principle part 25A of the control scheme in the following it is assumed that the first works under the action of the address decoder 14 group 4 memory cells.

Then in the active cell 12 and 13 of the memory correspond to the logical values of the tires 20 of the data stored on the data lines DB[0] DB[7]. Thus, the information content of the cells 12 and 13 of the memory automatically overwritten on attached to the bus 20 data values of zero, which corresponds to erasing the information content of the memory cells. Then through the line 51 to the driver 41 unlocking the next stage 29 is another driver signal 45, which unlocks the switching transistor 33 unlocking stage 29 for issuing a control signal 9. The control signal 9 is used to control the cells 12 and 13 are schematic component 5, resulting in the information content of the cells 12 and 13 of the memory is overwritten on the bus 20 data is a logical "zero". Thus, the automatically groups, sequentially in time are addressed to all of the cells 10, 11, 12, 13 memory with random access and correspond to the value Loga simple way by means of a hierarchically organized schemas decoding memory with random access by using the control circuit 25A according to the invention, so it is necessary to provide only a single additional logic circuits that are easy to implement. Only once addressed a group of cells 10 and 11 of the memory, i.e., the corresponding lines of the words are in an active state, addressed the following group of cells 12 and 13 of the memory storage device with random access. Thus, the limit capacitive load bus 20 data. If, in contrast, would simultaneously open all of the cells 10 to 13, the memory storage device with random access, the tire 20 data would be significantly more your ability, so in the worst case to be able to quickly transfer all the memory cells of a memory device with random access to the logical value "zero". Bus 20 data directly after running the erase process is translated to a specific value, for example all lines of the data bus are transferred to the logical value "zero".

Issued at the end of the control circuit 25 of the last trigger circuit 29, a driver signal is fed back to the input stage unlocking 28.

In Fig.2 shows in detail the attached upravlayemaya circuit 25, if, for example, if too short prescribed time passing driver power bus 20, data is insufficient to transfer register, respectively, the memory cell storage devices with random access to the logical value "zero", so that the circuit that feeds the data bus does not have sufficient your power, i.e., despite the ongoing management of circuit components of the driver circuit 19 with the data bus in the memory cell is written "wrong" values other than zero. In this case, the circuit 55 of the regulation provides that an enable signal 53 to start the drive circuit 25 briefly again translated into a logic level "zero" and then on the level of logical "unit", in order to cause some re-start starts a chain of dominoes. Provided for this scheme 55 regulation contains the valves 56, 57 are NOT-OR, to the inputs of which are connected to the bus line 20 data, the valve 58 is NOT-AND, the inputs of which are connected to the outputs of gates 56 and 57 are NOT-OR, inverter 59 to the input of which is supplied as an enable signal 53, and the valve 60 is NOT-OR, the input of which is connected to the output of the inverter 59 and the output of gate 58 is NOT, AND which output line 62 is estrov 2 and 3, accordingly, line choice words for the memory cells 10 - 13 storage devices with random access. After activation of the control circuit 25, i.e., when the enable signal is set to logical "unit", all lines of the bus 20, data are transferred to a logical zero. If under certain conditions the driver of the bus capacity 20 insufficient data to serial tipping memory cells 10 - 13 memory with random access, using the schema 55 regulation stops further unlocking, respectively, the reset of the memory cells at too low your power data bus, and a serial addressing is continued only when the level of bus 20 data changes back to a stable value of a logical "zero". Thus, at the output of gate 58 is NOT-AND given the logical signal "unit", when only one bus line 20 data takes a value of logical "unit". Thus the output of gate 60 is NOT-OR generates a signal of logic "zero" and through the line 61, briefly turn off the control circuit 25, while the bus 20 data again does not take the value of a logical "zero". Thus, after a certain predetermined period of time, the control circuit 25 again sa is odvod and selection information, has a value of logical "unit".

1. Circuit device to activate automatically return the information content of the selected circuit components on the value of a logical "zero" containing a number of electronic circuit components made with the possibility of transfer of the operating status via a given Manager or the information signal supplied to the respective circuit component in the erase state, in which the information content of circuit component takes a value of logical "zero", and for sequential time control of all circuit components provided the sampling frame, running after start automatically and containing series-connected to each other unlocking stage, the number of which corresponds to the number of circuit components, each trigger stage is configured to activate or trigger for issuing a control signal to the corresponding circuit component using the unlocking signal is generated immediately prior unlocking step, and unlocking stage after the filing of a control signal to the corresponding shenyuan the next stage unlocking, characterized in that each of unlocking step includes the gate circuit consisting of the enabling switch is made with the possibility of inclusion by enabling signal applied to line enabling signal when the enable signal has a logic level "unit", and with the possibility of locking at the level of the enabling signal equal to a logical "zero", the switching transistor with the appropriate governing output connected with the allow switch, and from the control Manager output switching transistor driver, is made with the possibility of opening the switching transistor to control the respective circuit component when the driver input driver equal to a logical "one", and with the possibility of locking the switching transistor when the driver signal at the input of the driver is equal to a logical "zero", and the circuit device is manufactured with the capability of issuing from the switching transistor when it is open, unlocking signal that controls the return or erasing the information content of the circuit component to the value of a logical "zero", and then with the possibility of issuing driver signal at the input of p. 1, wherein the electronic circuit components contain one performed on the semiconductor substrate of the semiconductor memory device is a random access memory location that the circuit device also includes a data bus with the data lines, the address decoder to control the memory cells to carry out with any frequency of read and write is applied to the data bus eight-bit data schema input and output data and control scheme, containing valves are NOT-OR with inputs and outputs, the inputs of which are connected lines of the data bus, the valve is NOT-AND with inputs and outputs, the inputs of which are connected to the outputs of gates is NOT-OR, inverter, on which side of the input enable signal, and the following valves are NOT-OR with inputs and outputs, the inputs of which is connected to the output of the inverter and the output of gate NOT, AND which output line is connected to the address decoder so that the sampling frame is briefly turned off when the line data bus assumes the value of logical "unit" and thus at the output of the following valves are NOT-OR a signal is generated with a value of logical "zero".

3. Circuit device under item 1 or 2, characterized in that provided for the La electronic control one or more circuit components and enabled prior to sampling design, moreover, a sensor device is configured to register the deviation from the permitted operational status of the control device or circuit component with the ability to provide in response to the deviation from the permitted operating state of the enabling signal at the first trigger level for automatic activation of the sampling scheme.

4. Circuit device according to one of paragraphs. 1-3, characterized in that it is placed on the semiconductor integrated circuit inside the electronic card.

 

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