A memory cell of a static nvr

 

(57) Abstract:

The invention relates to a memory cell of a static NVR. The technical result is the ability of the specified cell to remain in a state of high current in a locked state for a long time. The cell contains a bistable (BIMOS) transistor, two resistors, two transistors, two bit bus, two bus words. 8 C.p. f-crystals, 2 Il.

The invention relates to a memory cell of a static NVR.

Known memory cells are static memory devices, random access (static NVR), in which the trigger is to remember the values of the potential, which represent the logical state. When this trigger is executed on four field-effect transistors. The memory cell includes, in addition, two of the selection transistor, which are used for writing and reading the memory cell, the gates of which are connected with the bus of the words static NVR, and connecting the trigger with a pair of bit buses. In General, therefore, we are talking about a 6-transistor memory cell. Also known implementation of a trigger with two field effect transistors so that we obtain a 4-transistor zapominayuschaya has a small footprint.

This problem is solved due to memory cells of a static NVR according to paragraph 1 of the claims. At the same time to remember the two logic States instead of trigger is a bistable field-effect transistor. One logical state is locked, and the other logic state is open bistable transistor.

Under the bistable field-effect transistor here should be understood transistor, which has gisterezisnoi characteristic current-voltage of the gate so that it is only through the application of appropriate positive or, respectively, a suitable negative threshold voltage shifts from the closed state to the high current and Vice versa. Values of gate voltage value between the both threshold voltages do not cause any state changes. Bistable transistor is so controlled voltage pulses, which are only briefly exceed the absolute value of the corresponding (positive or negative) threshold voltage.

Fig. 2 depicts the course mentioned hysteresis function bistable field-effect transistor, and the voltage of the drain-source UDStakes the to and which during operation of the bistable transistor must not fall below the minimum value. On the abscissa the applied voltage gate-source UGSand on the ordinate - logarithmically drain current I. the Positive threshold voltage denoted as UE.

From the work of authors N. Kistler, E. V. Ploeg, J. Woo, and J. Plummer "Breakdown Voltage of Submicron MOSFETs in Fully Depleted SOI" in Microelectronic Manufacturing and Relaibility, issue 1802 (1992), page 202, etc. known field-effect transistor, which can be used according to the invention as a bistable field-effect transistor. In this publication is described fully depleted (i.e. in a non-conductive state with little in their field of channel no free charge carriers) n-channel field-effect transistor with a horizontal structure, which is made using CPV technology (silicon on insulator). The channel is floating, i.e. not connected with any permanent capacity.

Often the substrate, which is a bistable transistor, connected to the potential of the substrate. Then is necessary to achieve the floating area of the channel, so that it was isolated from the substrate. In the case of the aforementioned prior art, this occurs through the use of CPV technology. Bistable transistor may, however, differently than in the above urbnet substrate in a simple way. Bistable transistor with such a vertical structure may, for example, be manufactured by molecular beam epitaxy. Thus can be achieved in the channel length is less than 10 nanometers. In experiments it was found that the length of the channel is less than 100 nm, for example 85 nm, is particularly suitable for manufacturing a bistable transistor with a vertical structure.

Important to make a bistable transistor is that its channel region in the locked state has been depleted. In the state of high current, i.e. when the application of gate voltage exceeding the positive threshold voltage, then there is a breakdown of the transistor due to impact ionization are freed charge carriers. When the channel lengths larger than 1 μm, sufficient depletion achievable through the use of low-alloyed impurity region of the channel. The shorter the length of the channel allows the channel region of higher concentrations of the alloying substances. Depletion can be achieved, in particular, by expanding the barrier layer is locked p-n junction with an applied voltage drain-source. For shorter channel lengths, also at lower voltage drain-source (for example, the CSOs current.

Described hysteresis effect is as follows: if the voltage of the drain-source bistable field-effect transistor is located above mentioned minimum value, which is determined by the applied technology and the size of transistor bistable field-effect transistor by increasing its voltage gate-source to values above also establish a positive threshold voltage, can also be translated from the locked state to the conducting or, respectively, the status of high current. In this state, high current, it remains also when voltage gate-source decreases again to values below a positive threshold voltage, as long as it does not fall below the minimum voltage drain-source. Only when a sufficient negative voltage gate-source at which the voltage becomes lower than the negative threshold value, the transistor again conducts. (These notes refer to the bistable transistors n-channel type. In the case of p-channel transistors fairly appropriate).

Corresponding to the invention, the memory cell operates on the following principle, pricesare, for example, logical units, bistable transistor due to the application of a suitable gate voltage (which exceeded the positive threshold voltage voltage gate-source) through the first bit of the bus is transferred into its state of high current. It will be saved, if the voltage of the gate-source again takes values below a positive threshold voltage. The second logical value, such as a logical zero is written, when by application of sufficient negative voltage gate-source (and dropping below a negative threshold voltage) bistable transistor is translated from its state of high current in a locked state. Thus, bistable transistor is controlled by voltage pulses.

Reading memory cells possibly due to the fact that the second output channel is connected with a second bit bus. She then, in accordance with the state of the bistable transistor is charging or to the value of the first or second potential.

Since according to the invention instead of trigger in the level of technology, which includes four transistor or two transistors and two resistors, used the local solutions can be saved at least one transistor and one resistor, due to what turns out less need for storage space of the cell.

If recording in a memory cell and to read from the memory cells provided respectively in the first and second field-effect transistor, with the bistable field-effect transistor is obtained 3-transistor memory cell instead of the known 6 - or 4-transistor storage cells.

Is preferred, if the first bit coincides with the second bit bus, i.e. if there is only one bit. Through it then occurs as an entry in a cell, and reading out from the memory cells. Corresponding to the invention a memory cell thus can contain either a two bit bus and one bus words to control the first and second transistors, or only a single bit bus and one bus words to control the first and second transistors. Of course, it is also possible that there is a two bit bus, two bus words.

Preferably, if the shutter bistable transistor via a second resistor is connected to a third potential, which ensures that he at any time of vremeni CLASS="ptx2">

The closest analogue of the present invention is to publish Reisch, M. "On bistable behavior and open-base breakdown of bipolar transistors in the avalanche regime-modeling and applications" in IEEE Transactions on electron devices, volume 39, number 39, June 1, 1992, pages 1398-1409, JR.

In the specified publication describes a memory cell of a static NVR (Fig. 9) on the basis of the bistable transistor. To one terminal of the bistable transistor summed potential VCC. The basic output of bistable transistor is connected via used as another switch transistor to the bit bus. Unlike technical solutions for specified publication, in which the bistable transistor bipolar transistor is used, the claimed invention is applied to a field transistor.

In the following the invention is described in more detail in the examples with figures showing:

Fig. 1 - form of execution corresponding to the invention of memory cells,

Fig. 2 - historiska characteristic of the bistable field-effect transistor with Fig.1.

Fig. 1 shows a bistable field-effect transistor BIMOS (Bi-MOS), the first output channel D which is connected to the first output potential VCC and the second vioviolence invention bistable field-effect transistor BIMOS transistor is n-channel type. Assume that the first potential VCC is greater than the second potential (ground). For example, both potential VCC, the ground can be a potential supply of the integrated circuit, part of which is a memory cell of a static NVR. The second potential (ground) may be in this case, the reference potential. Because it is common that the first potential VCC is greater than the second potential, in this example, the first output channel D bistable field-effect transistor BIMOS is its drain, and the second output channel S - its source.

Needless to say, it is possible to perform memory cell with the bistable field-effect transistor BIMOS p-channel type, in which the first potential VCC must be chosen smaller than the second potential (ground).

The gate G bistable field-effect transistor BIMOS in Fig.1 is connected through the first field-effect transistor T1, which in this exemplary embodiment is an n-channel, first the bit-line BL1. The first field-effect transistor T1 is controlled through the first bus words WL1, which is connected to its gate.

The second output channel S bistable field-effect transistor BIMOS through the second field-effect transistor T2 is made with the possibility of connection with W the th field-effect transistor T2 is controlled through the second bus words WL2, which is connected to its gate.

The first transistor T1 and second transistor T2 may also be p-channel, so that their management must potentials of both tyres words WL1, WL2.

Gate G bistable field-effect transistor BIMOS open when the first transistor T1 and second transistor T2 is applied through the second resistor R2, the third potential V3, which in this exemplary embodiment is equal to the second potential (ground). Through the second resistor R2 ensures that the gate G in any of the time points are not "floating", that is, never has an undefined potential. The value of the third potential V3 should be selected so that when open the first transistor T1 and second transistor T2 voltage gate-source UGSbistable field-effect transistor BIMOS does not exceed the positive threshold voltage UEand is not less than the negative threshold voltage UXat which the transition occurs from a state of maximum current flow in the locked state (see Fig.2). The second resistor R2 in this case may fall away, but the memory cell due to the floating gate G can be error-prone functionates in a memory cell:

The potential at the second output channel S can, as will be shown below, to take two values - on the one hand, the value of the first potential VCC minus at least already described minimum value voltage drain-sourceDSwhich is necessary for maintaining the state of the high current. On the other hand, the value of the second ground potential. Which of the two values will be taken depends on whether the bistable field-effect transistor BIMOS in the locked state or in a state leakage maximum current. In this state of high current bistable field-effect transistor BIMOS corresponds to, for example, memorized logical unit, and the locked state is memorized logical zero.

Suppose that through the second bus words WL2 of the second field-effect transistor T2 must be locked away. In the present exemplary embodiment, this occurs so that the second bus words WL2 has the potential, which is inverted relative to the first potential VCC, i.e. it has a similar magnitude, but opposite sign. Suppose that the bistable field-effect transistor BIMOS is initially in its locked state (i.e. the memory cell stored, for example, the logical is therefore, its, the first resistor R1 is applied to the second potential (ground).

If now the first field-effect transistor T1 due to the charge of the first bus words WL1 to the value of the first potential VCC is opened (the state leakage maximum current), in the memory cell may be written to the new memory value (e.g., logical unit). To do this, before opening the first transistor T1 is charge the first bit bus BL1 to capacity (which may be equal to, for example, the first potential VCC), which after a connection is established with the gate G bistable field-effect transistor BIMOS his charges so that the lowering below a positive threshold voltage (VEbistable field-effect transistor BIMOS.

Due to the intrinsic properties of the bistable field-effect transistor BIMOS he remains in a state leakage maximum current if the first field-effect transistor T1 is closed and gate G bistable field-effect transistor BIMOS through the second resistor R2 is again applied to the second potential (ground). It is important that the state leakage maximum current voltage drain-source UDSnever dropped below mentioned minimum value. This can be achieved is S="ptx2">

A new generation of stored logic state is possible only when the bistable field-effect transistor BIMOS again locked. This is due to the fact that the first bit BL1 is brought to a negative potential which lies below the negative threshold hysteresis UXbistable field-effect transistor BIMOS. If then the first field-effect transistor T1 is opened, the potential at the gate G with the bistable field-effect transistor BIMOS corresponds approximately to that bit on the bus BL. Bistable field-effect transistor BIMOS is closed and through the first resistor R1 to the second output channel S again applied second potential (ground).

2) Reading a memory cell:

Assume that the first field-effect transistor T1 is locked. Reading occurs through the second field-effect transistor T2. If it opens, the second bit BL2 is charged to a potential at the second output channel S. thus advantageous if before the opening of the second field-effect transistor T2, the second bit BL2 pre-charged up to the value of the second potential (ground). In fact, if the second output channel S is applied to the second potential (ground) (bistable field-effect transistor BIMOS locked), noproject this on the second output channel S applied first potential VCC minus the voltage drain-source bistable field-effect transistor BIMOS (he then opened), the second bit BL2 through the bistable field-effect transistor BIMOS and second field-effect transistor T2 is charging. Due to this, the potential at the second output channel's short falls slightly, however, due to this bistable field-effect transistor BIMOS opens up even more (because its voltage drain-source UDSdue to this growing) so that the overcharge second bit bus BL2 even more accelerated.

With proper choice of parameters (the value of the first resistor R1 in the field of thereom) memory cell with an open bistable field-effect transistor BIMOS has only a small quiescent current (as of the second field-effect transistor T2 is closed and the reading takes place), while, on the other hand, when reading a memory cell can be achieved by a high charging current for bit bus BL, which flows through the bistable field-effect transistor BIMOS. The second bit BL2, as described above, the pre-charged up to the value of the second potential (ground) so that the charging current never flows through the first resistor R1. The parameters of the resistor R1 is selected so that the voltage between the first potential VCC and the second potential (ground) in the locked state falls mainly on zakresami. In the state leakage maximum current in contrast to the second output channel S is applied to the difference between the first potential VCC and a minimum voltage value of the drain-source.

By reading through the second transistor T2 state of the memory storage cell, i.e. the state of the bistable field-effect transistor BIMOS (locked state or the condition of high current), remains unchanged. The status memory can be achieved only through the first field-effect transistor T1 and the first bit bus BL1.

To open when the first field effect transistor T1 between the gate G bistable field-effect transistor BIMOS and the second potential (ground) flowed only a small current, a second resistor R2 should be chosen if possible resistance.

In the invention proposed preferred option 3-transistor static memory cells NVR. Experiments with vertical bistable field-effect transistor BIMOS showed that he remains a long time in a state of maximum current flow and in the locked position, while its gate G is applied to the second ground potential. Experimentally podtverzdeniye be passed without changes.

1. A memory cell of a static NVR containing bistable (BIMOS) transistor connected to the first bit bus (BL1) through the first transistor (T1) and coupled with the first output potential (VCC), characterized in that the bistable (BIMOS) transistor is bistable field-effect transistor, the first output channel (D) which is connected to the first output potential (VCC), a second output channel (S) connected via the first resistor (R1) to the second potential (ground) and the gate (G) of the bistable field-effect transistor (BIMOS) is connected via the first transistor (T1) with the first bit bus (BL1), while the second output channel (S) made with the possibility of connection through the second transistor (T2) to the second bit bus.

2. A memory cell under item 1, characterized in that the gate (G) of the bistable field-effect transistor (BIMOS) is connected via a second resistor (R2) with the third potential (V3).

3. A memory cell according to any one of paragraphs.1 and 2, characterized in that before the process of reading the second bit (BL2) is pre-charged up to the value of the second potential (ground).

4. A memory cell according to any one of paragraphs.1-3, characterized in that during the process of recording the first bit (BL1) has come eat, both of the potential of different polarity have the same value as the first potential (VCC).

6. A memory cell according to any one of paragraphs.1-5, characterized in that the first transistor (T1) is the first field-effect transistor (T1),the gate of which is connected to the first bus words (WL1).

7. A memory cell according to any one of paragraphs.1-6, characterized in that the second transistor (T2) is the second field-effect transistor (T2), the gate of which is connected with the second bus words (WL2).

8. A memory cell under item 7, characterized in that the first bus words (WL1) is identical to the second bus words (WL2).

9. A memory cell according to any one of paragraphs.1-7, characterized in that the first bit (BL1) is identical to the second bit bus (BL2).

 

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