Analog-to-digital converter

 

(57) Abstract:

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code. The technical result is to increase the performance of your device, which is achieved by applying optimal matching code, taking into account the statistical characteristics of the converted signal. The device contains a schema comparison, digital to analog converters, pulse generator, the register, the trigger shaper codes. 3 Il., table 1.

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code.

Known N-bit ADC reading, containing the divider reference voltage, 2Nstrobing voltage Comparators (KN), the decoder, the XOR, the register (Fedorov, B. Taurus C. A. Chip DAC and ADC: operations, parameters, applications. - M.: Energoatomizdat, 1990. - S. 151, Fig.3.17).

The disadvantage of the ADC reading is difficult, because to build an N-bit ADC requires 2NComparators and voltage divider navjot maximum performance, the transformation is carried out for one cycle.

The closest in technical essence to the present invention is successive approximation ADC, containing a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage, and the output connected to the first input register of the successive approximation (RPA), the first outputs of which are connected to the inputs of the digital to analogue Converter (DAC), and are simultaneously outputs of the ADC, the DAC output is connected to the second input of the comparison circuit, the second input of the successive approximation register is the second ADC input, a third input connected to the output element And the second output to the second input of this element And, the first input of which is connected to the generator output clock pulses (Chernov Century, Device I / o analog information to digital systems of data collection and processing. - M.: Mashinostroenie, 1988. - S. 85, Fig.57) (prototype).

The disadvantage of this device is low speed. The conversion process always takes N clock cycles, where N is the ADC. In addition, the algorithm selection code (half division) optimal only in the case when the probabilities of all possible combinations is even increasing the number of digital to analog converters and schema comparison and applying optimal matching code, taking into account the statistical characteristics of the converted voltage.

The technical result is achieved by the successive approximation ADC, containing a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage, and the first input device and the second input connected to the output of the digital to analogue Converter, the pulse generator, put the trigger shaper codes, additional digital-analog converters and the same number of additional schemes comparison, the first inputs are combined and connected to the first input device, a second input connected to the output of the respective d / a converters, and outputs connected to respective first inputs of the driver code, the first group of outputs which is the first output device, each group of outputs of the driver code is connected to the appropriate inputs of the register, the first group of outputs of the register are connected to the inputs of the first analog-to-digital Converter and the second inputs of the driver code, the rest of the group of outputs of the register are connected to the inputs of sogod trigger, which is the second output device connected to the first control input of the register and the control input of the pulse generator, the output of which is connected with the second Manager of the input register and Gating inputs schema comparison, the last output of the shaper codes connected with the second input of the trigger.

A structural scheme of the device differs from the known fact that it introduced the trigger shaper codes, additional digital-analog converters and the same number of schemes comparison, which are standard nodes analog and digital computers. Driver code can be implemented on programmable logic arrays or as a permanent storage device. However, despite the fact that the blocks are standard nodes analog and digital computing techniques, their introduction, as well as the emergence of new functional connections between them and the existing units gives the chance to appear in the device to a new property. Namely, the ADC can reduce the conversion time of the measured value due to the parallel comparison of the input to be converted voltage with multiple reference naprjazhennejshie. The optimal procedure code selection can be made using methods known in theory of automatic control and Troubleshooting (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under.ed. I. A. Ushakov. - M.: Radio and communication, 1981, - 280 C. ). Comparing the input voltage with several supporting and applying best practices can reduce the time spent on the selection code corresponding to the input voltage and, consequently, to increase the speed of the ADC.

Structural diagram of the ADC is shown in Fig.1, where 1 - comparison circuit; 2 - analog Converter (DAC); 3 - clock; 4 - the register; 5 - trigger; 6 - shaper codes.

Comparison circuit 1 is intended to compare the input to be converted voltage UIand voltage output of the corresponding DAC 2 - UDAC. If UI>UDACat the output of the comparison circuit 1 appears a signal corresponding to a logical unit, otherwise a logic zero. Schema comparison 1 strobilus leading edge of the pulses from generator 3, to ensure a more reliable operation of the device. DAC 2 is designed to convert the clock 3 is designed to synchronize the operation of the device. Register 4 is designed to remember the current codes coming from the output of the shaper codes 6, in the process of selection of the output code. The trigger 5 is designed for fixing the beginning of the conversion process and its completion. When submitting its first input signal "start" trigger 5 is set in one state and starts the conversion process. When the signal of logical units on the last output of the shaper codes 6 trigger 5 is set in the zero state and the conversion process ends.

Shaper codes 6 is designed to implement the process of selection code in the conversion process. Consider the process of selecting the code on one particular example. Let the ADC is equal to four, and the ADC contains two of the comparison circuit 1 and two digital to analogue Converter 2 (M=2). The process of selection code can be represented as a graph shown in Fig.2. In accordance with Fig. 2, initially, at the address inputs of the first DAC 2 (upper diagram in Fig.1) code is set to 9, and the address inputs of the second DAC 2 (bottom diagram in Fig.1) code is set to 6 (the top of the root vertex). The second inputs of the circuits of comparison 1 set voltage corresponding codes 6 and 9. Hereafter The Paragraph 2. The outputs of the circuits of comparison 1 at the same time, depending on the input voltage, there are three possible combinations: 00 - when the input voltage UIless than the voltage applied on the first and second DAC 2 (UI<Uand UI<U); 10 - when the input voltage is above the voltage received from the second DAC, but less than the voltage received from the first DAC (UI<Uand UI<U); 11 - when the input voltage is above the voltage applied as the first and the second DAC 2. Further, depending on the values of the codes in the output circuits of comparison 1 there is a transition on the corresponding arc of the graph. For example, if code 00 takes you to the top 2-5 and respectively to the inputs of the DAC 2 must be set accordingly code number 2 (lower scheme DAC) and number 5 (upper circuit DAC). The code selection process is terminated upon reaching the hanging vertices. As the output code corresponding to the input voltage UIis the code shown in Fig.2 rectangles. The table shows how the driver code 6 must convert the codes supplied to its inputs.

Consider, for example, 4, 5, 6 rows of table 1. In the 4th hundred the odes shaper codes 6, set code corresponding to the digit 9. In this case, if the output of the 1-St and 2-nd of the comparison circuit will be zero (the 4th row of the table), then the first output driver code 6 code set corresponding to the number 5 (4th row, 5th column of the table), and the second outputs set code corresponding to the number 2 (4th row, 6th column of the table). Ie provides the transition from the top 6-9 to the top 2-5 00 arc (Fig.2). In the last column of the 4th row (corresponding to the signal value of the last output of the shaper codes 6) in this case is zero, which indicates that the hanging top is not achieved and the conversion process should be continued.

Shaper codes 6 may be implemented as a permanent memory (ROM) in the input address inputs of the ROM, and outputs information outputs) or programmable logic arrays.

It should be noted that the process of selection code does not necessarily have to match what is shown in Fig.2. If you know the likelihood of the individual code combinations, it is possible to find such a sequence, which would provide a minimum average time of conversion or any jugoplastika search code combinations, corresponding to the input voltage). Algorithms for solving such problems are considered, for example, in the book "Paszkowski, C. the problem of optimal detection and search failures in REA. - M.: Radio and communication, 1981, - 280 C.".

Consider the operation of the device when the procedure code selection in accordance with Fig.2 for the next case. ADC - N=4. The device contains two of the comparison circuit 1 and two DACS (M=2). The maximum output voltage of the DAC - 10 V For 4-bit ADC in this case, the quantization step is equal to U = 10V/24= 10V/16 = of 0.625 V. This means that when applying to the input of the DAC 2 stake, corresponding, for example, the number 9, the output of this DAC will appear a voltage UDAC=90,625=5,625 V.

Let the ADC input voltage UI=3,2 V.

The operation of the device and, therefore, the process of converting the input voltage into the code begins with the filing of the second input device "start" and, respectively, to the first input of the trigger 5 of the pulse (in the initial state, the trigger 5 is in the zero state). The trigger 5 is transferred in one state and its output appears a level corresponding to a logical unit. Upon receipt of the leading edge of the voltage drop from output to trigger the output register 4 will be established code of zero, which goes to the second inputs of the former (codes 6. According to the table (lines 1-3), regardless code output circuits of comparison 1, the first group of outputs of the driver code 6 code appears in the number 9 (lines 1-3, column 5 of the table), and the second group of outputs code number 6 (lines 1-3, column 6 of the table).

After the transition of the trigger 6 in one state level logical units of its output is supplied also to the control input of the pulse generator 3, and its output is starting to get a pulse on the second control input (input record) register 4. In case 4 on the trailing edge of the first pulse from the pulse generator 3 to the first group of inputs will be recorded code number 9, and the second group of input code number 6. This corresponds to the root vertex 6-9 graph in Fig.2.

Code number 9 from the first output register 4 will arrive at the input of the first DAC 2 (upper diagram of Fig. 2) and its output appears the voltage UCAP= 90,625=5,625 V. second output register 4 to the inputs of the second DAC 2 (bottom of the diagram, Fig. 2) enter the code number 6 and its output will appear a voltage UCAP= 60,625= 3,75 V. using schema compare 1 compares the voltage outputs of the corresponding DAC input napryajenie 1 on the leading edge of this pulse is fixed to the comparison results. In this case, the input voltage is less than the output voltage and the first and second DAC 2 and the output circuits of the comparison will be a logic level zero.

So, at the first inputs of the driver code 6 will be a combination of 00, and the second outputs code number 9 (with the first group of outputs of register 4). In accordance with the table (line 4), then on the first outputs of the shaper codes 6 set code number 5 (line 4, column 5 of the table), and the second outputs code number 2 (line 4, column 6 of the table). In Fig.2 this corresponds to a transition from vertex 6-9 in the top 2-5 conditionally 00. On the trailing edge of the second pulse from the pulse generator 3 codes numbers 2 and 5 will be written to the corresponding bit of the register 4, which in the future will be transferred to the respective inputs of the DAC 2. The output of the first DAC (upper circuit, Fig. 1) appears the voltage UCAP=50,625=3,125 V, and the output of the second DAC 2 (bottom of the diagram, Fig.1) appears the voltage UCAP=20,625 is 1.25 V. In this case we have UI>UCAPand UI>UCAP. Therefore, the output schema comparison 1 combination 11. Given that the second inputs of the former (code 6 has a code number 5, the first outputs of the shaper codes 6 poyavitstso logical unit (line 9, column 7 of the table). This signal is sent to the second input of the trigger 5 and install it to the zero state. At the output of the trigger 5 will set a level corresponding to a logical zero, which turns off the pulse generator 3. The process of converting the input voltage into the code on this end. The output from the first output of the driver code 6 will be the result of the conversion, i.e., the code number 5.

From the previous description it follows that the conversion process was over in about two stroke operation. Two bars will also be required when converting a voltage corresponding to the code numbers 6, 7, 8, 9. For other codes, the conversion time will be three steps (Fig.2).

Increasing the number of DAC and schema comparison, you can improve the performance of the device. In Fig.3 the graph shows the process of selection code for ADC, containing 4 of the comparison circuit and 4 DACS. In this case, codes 6, 7, 8 can be obtained within one cycle of the device codes 2, 3, 4, 5, 9, 10, 11, 12 for two bars and codes 0, 1, 13, 14, 15 for three quantum devices.

Thus, the proposed device allows to reduce the conversion time of the analog voltage in the code and, therefore, improve the performance of the device the device regardless of the level of the input voltage).

The cost of equipment and the performance of the proposed ADC occupies an intermediate position between the ADC reading and successive approximation ADCS. Increasing or decreasing the number of DAC and schema comparison, you can get the settings to performance, which is an additional positive feature. The average conversion time can be reduced by applying optimal matching code. Selecting the driver code 6 in a separate chip, with the possibility of replacement, you can find selection procedure code in such a way as to ensure maximum performance under the given statistical characteristics of the signal.

Analog-to-digital Converter comprising a comparison circuit, the first input of which is fed to the input of the converted voltage and the first input device and the second input connected to the output of the digital to analogue Converter, the pulse generator, characterized in that it introduced the trigger shaper codes, additional digital-analog converters and the same number of additional schemes comparison, the first inputs are combined and connected to the first input of the second vhodni the first inputs of the driver code, the first group of outputs which is the first output device, each group of outputs of the driver code is connected to the appropriate inputs of the register, the first group of outputs of the register are connected to the inputs of the first digital to analog Converter and the second inputs of the driver code, the rest of the group of outputs of the register is connected to inputs of respective digital to analog converters, the first input of the trigger is the second input device, the trigger output, which is the second output device connected to the first control input of the register and the control input of the pulse generator, the output of which is connected with the second Manager of the input register and Gating inputs schema comparison, the last output of the shaper codes connected with the second input of the trigger.

 

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