Analog-to-digital converter

 

(57) Abstract:

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code. The technical result is to increase speed, which is achieved by applying the optimal logical procedure code selection, taking into account the statistical characteristics of the converted signal and the settling time voltage output digital to analogue Converter. The device comprises a comparison circuit, a d / a Converter, one-shot, register, counter, trigger, pulse generator, a permanent storage device. table 2., 2 Il.

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code.

Known analog-to-digital Converter (ADC) the witness of the type with a voltage comparator, oscillator, item, count, voltage reference and digital-to-analogue Converter (DAC) (microelectronic device automation: Educational. manual for schools/ A. A. Sazonov, V. I. Nikolaev and others ; Ed. by A. A. Sazonova. - M.: Energoatomizdat, 1991. - S. 153, areopagitou voltage.

The closest in technical essence to the present invention is successive approximation ADC, containing a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage, and the output connected to the first input register of the successive approximation (RPA), the first outputs of which are connected to the inputs of the digital to analogue Converter (DAC) and are simultaneously outputs of the ADC, the DAC output is connected to the second input of the comparison circuit, the second input of the successive approximation register is the second ADC input, a third input connected to the output element And the second output to the second input of this element And, the first input of which is connected to the generator output clock pulses (Chernov Century, Device I / o analog information to digital systems of data collection and processing. - M.: Mashinostroenie, 1988. - S. 85, Fig.57. Functional diagram and the timing diagram of the ADC successive approximation). Successive approximation ADC is characterized by the following features. During code selection method is used half of the division, but the principle of half-fission does not take into account the statistical characteristics of the input analog signal. The process is p=NtDACwhere tDAC- time setting voltage at the DAC output, when changing the code at its input. As tDACtake the value equal to its maximum value of tCapMan(corresponding to the feed input of the DAC zero after the maximum code for a given DAC), i.e., is not taken into account the different time of the output voltage at the DAC output for different codes.

The disadvantage of this device is a low speed, because it does not takes into account statistical characteristics of the signal and the settling time voltage output digital to analogue Converter.

The technical result improved ADC performance through the application of optimal logical procedure of selection of the output code, taking into account the statistical characteristics of the signal and the temporal characteristics of the DAC (the settling time of the input voltage).

The technical result is achieved by the successive approximation ADC, containing a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage and the first input device and the second input connected to the output of the DAC, the inputs of which are connected to the outputs of regionthis and a persistent storage device (ROM), first, the outputs of which are connected to first inputs of the register, the first address inputs connected to the outputs of the register and the second address input coupled to the output of the comparison circuit, the first input of the trigger is the second input device, the trigger output, which is the second output device, connected to the first input of one-shot, the second input register and a control input of the pulse generator, the output of which is connected to a second input of the trigger and the first input of the subtractive counter, the output of which is connected to a second input of one-shot, the output of which is connected with the third input register and a second input of subtractive counter, the third input of which is connected to the second outputs of the permanent storage device, the third output of which is connected to the third input of the trigger.

A structural scheme of the device differs from the known fact that it introduced the trigger, one-shot, subtractive counter and a persistent storage device (ROM), which are standard nodes analog and digital computers. As the trigger can be used with chip TV, subtractive counter - IE, ROM - RE, the one-shot - AG (Avanesyan, R., Levshin Century. P. And the entered units are standard nodes analog and digital computers, their introduction, as well as the emergence of new functional connections between them and the existing units gives the chance to appear in the device to a new property. Namely, the ADC can reduce the conversion time of the measured value by applying optimal matching code which takes into account the probabilistic characteristics of the measured value and the temporal characteristics of the digital to analogue Converter (settling time output voltage). The optimal procedure code selection can be made using methods known in theory of automatic control and Troubleshooting (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under. editor I. A. Ushakov. - M.: Radio and communication, 1981. - 280 C.). The optimal procedure can reduce the time spent on the selection code corresponding to the input voltage and, consequently, to increase the speed of the ADC.

Structural diagram of the ADC is shown in Fig.1, where 1 - comparison circuit; 2 - analog Converter (DAC); 3 - one-shot; 4 - the register; 5 - subtractive counter; 6 - trigger; 7 - pulse generator; 8 - permanent memory (ROM).

Comparison circuit 1 PR is SUB>. In the case when UI>UDACat the output of the comparison circuit 1 appears a signal corresponding to a logical unit, otherwise a logic zero. DAC 2 is designed to convert a digital code supplied to its input, the corresponding output level of the analog voltage. The one-shot 3 is designed to generate a pulse when applying for his first or second inputs of the pulse front (after the next cycle comparison). On the trailing edge of this pulse to the register 4 and subtractive counter 5 is overwritten with the new values from the ROM 8. Register 4 is designed to store the current value of the output code conversion. Subtractive counter 5 is designed to generate a time interval corresponding to the time of establishing the voltage at the DAC output 2 for the current code. After recording in the counter 5 a number on his first (subtractive) input start receiving pulses from the output of the pulse generator 7. When the counter 5 at the output you receive a level corresponding to a logical unit, which indicates that the voltage at the DAC output has reached a steady-state value. Let for this code TO thei(submitted to the DAC input) time ustanovlenija in the counter 5, you must record the number of TSCequal to NSC= Ti/t. The trigger 6 is designed for fixing the beginning and end of the conversion process. When submitting its first input pulse trigger 6 passes in one state and starts the conversion process.

At the end of the conversion process, the trigger 6 is reset to the zero state by a negative pulse from the pulse generator 7 for admission to the third input of the trigger 6 single signal from the third output of the ROM. The pulse generator 7 is designed to supply pulses to the first (subtractive) the subtractive input of the counter 5. He starts feeding on its control input voltage corresponding to a logical unit, the output of the trigger 6. The ROM 8 is intended for storage of digital codes used in the procedure of selection of the output code corresponding to the input analog voltage UI. In ROM 8 also stores the values of the delays for all codes used (corresponding to the time of establishing the voltage at the DAC output 2).

Consider the optimal procedure code selection in the process of analog-to-digital conversion for 4-bit ADC (N = 4).

The number of possible codes m is for the distribution function of the input voltage UIthe probability that this code will match the input voltage will be equal to the value given in the table.1 (this data corresponds to a normal distribution).

Assume also that the time for establishing the voltage at the DAC output 2 proportional to the input code, i.e., if the input of the DAC was filed code equal to 8 (1000), the subtractive counter 5 must record the number 8 (usually large code values correspond to large values of the time response of the DAC).

You need to find such a sequence of selection code, which provided the minimum average time of conversion. This problem corresponds to the problem of construction of optimal programs of diagnosis, i.e., the search control object only defective item (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under. editor I. A. Ushakov. - M.: Radio and communication, 1981. - S. 50-84). Using the corresponding algorithm for constructing an optimal search strategy, obtain that in this case it is expedient selection code producing in accordance with the program displayed in the graph shown in Fig.2. The average conversion time in this case will be 1,76 tCapMan, DG is using serial approximation is 4tCapManthe proposed device in this case can improve the speed of the ADC more than twice.

In accordance with Fig.2 the first should be checked code equal to 8 (1000). If the voltage on the DAC output 2 will be larger than the input voltage (UI<U), then the following must be checked code 6 (OO) - transition is on the left branch of the graph extending from the first vertex and is marked with 0. If the voltage on the DAC output 2 will be less than the input voltage (UI>UDAC), then the following must be checked code 10 (1010) - the transition is on the right branch of the graph extending from the first vertex and is marked with 1. Upon reaching the hanging vertices, or vertices, in which there is no left branch, the code selection process ends. As a result of the conversion is taken code shown in Fig. 2 in the rectangle.

The contents of the ROM 8 for this procedure, the selection code shown in table.2.

The selection program code recorded in the ROM 8 in the form of a sequence of words. The addresses of the words listed in the second column "Address". Address value is given in decimal form, and binary (in parentheses). In binary write address bits allocated, use code used in this step, the selection of the output code (the table shows the decimal value of this code and in parentheses is its binary representation). The "Delay" contains a number that is proportional to the time response of the DAC 2 for the appropriate code from the "Code" field (in this case assumed that this time is proportional to the current code selection). The "Sign of the end" specifies the time the end of the program code selection. The execution of the program ends, if this field will contain the unit. In this case, the "Delay" can contain any non-zero value.

Consider the operation of the device when the procedure code selection in accordance with Fig.2 and the data table.2 for the next case. ADC - 4. The input voltage range is 10 V For 4-bit ADC in this case, the quantization step is equal to U=10V/24=10V/16= of 0.625 V. This means that when applying to the input of the DAC-2 code, for example, equal to 4, its output will be a voltage UDAC=40,625=2,5 V. Assume that the ADC input voltage UI=6,3 V

In the initial state, the trigger 6 is in the zero state. When applying for his first entrance (START) pulse he goes into a single Veni, the corresponding logical unit. On the leading edge of this pulse register 4 is set to zero. Zero code with its output fed to the first address inputs of the ROM 8. Depending on what the logical level at the output of the comparison circuit 1 (which goes to the senior address digit ROM 8), will be selected word from the ROM 8 to the address 0 (0 0000) or 16 (1 0000). As follows from the table.2 (1-I or the 17-th line), first and second outputs of the ROM 8 in any case, the code appears equal to 8 (1000).

The differential voltage output of the trigger 6 will also be at the first input of the one-shot 3 and its output will generate a pulse that arrives at the first input of subtractive counter 5 and the third input of the register 4. On the trailing edge of this pulse to the counter 5 and the register 4 is written information outputs of the ROM 8, in this case they will be recorded code number 8 (1000).

Code from the output of the register 4 will arrive at the inputs of the DAC 2 and its output will appear a voltage UDAC= 80,625= 5V. This voltage will go to the second input of the comparison circuit 1, to the first input of which is filed convert the input voltage (for example made UI=6,3 V). Since UI> UDACat the output of the comparison circuit will be level, and, accordingly, the outputs of the ROM 8 code appears 10 (1010) (25th row in the table.2), which corresponds to Fig. 2, according to which after the code 8 code 10 is used when UI> UDAC.

At the transition of the trigger 6 in one state level logical units of its output is supplied also to the control input of the pulse generator 7, so that it begins to generate rectangular pulses at the first (subtractive) the subtractive input of the counter 5. In subtractive counter 5 in this case, write the number 8, so after 8 pulses the contents of it will be zero (it is assumed that during this time of the previous phase comparison is completed and the next value of the output code is defined). When zeroing subtractive counter 5 at its output appears the level of logical units, which will go to the second input of the one-shot 3. On the leading edge of this difference, the one-shot generates the output pulse on the trailing edge of which the contents of the outputs of the ROM 8 will be recorded in the register 4 and subtractive counter 5. In this case, and in case 4 and subtractive counter 5 will be recorded code number 10 (1010).

DAC output 2 this will bring up the voltage UDAC=100,625=6,25 V. Since it is assumed that UI= 6,3 V, hence UI>UDACand neither of the first and second outputs of the ROM 8 is the code number 11 (1011) (27-th row in the table.2).

After receipt of ten pulses from the generator 7 to the subtractive counter 5 contents will be equal to zero, its output will appear impulse that starts the one-shot 3. On the trailing edge of this pulse to the counter 5 and the register 4 is written code number 11 (1011).

After that, the voltage at the DAC output will be equal to UDAC=110,625=6,875 V. In this case, UI<Uand the output of the comparison circuit is a logic level zero. The address inputs of the ROM 8 and the code will number 10 (0 1011), which corresponds to 12-th row in the table.2.

In the last column of this row in this case, the recorded unit. This means that on the third output ROM 8 will receive a level corresponding to a logical unit, which goes to the third input of the trigger 6 and the negative edge of the pulse from generator 7 trigger 6 will be set in the zero state (the gate of the third input trigger 6 negative edge of the pulse from generator 7 is necessary in order to eliminate the reset trigger 6 in the zero state due to transients in ROM 8). The conversion process is completed, while in case 4 will be written to the final output code (in this case, the number 10 (1011)), and which goes on myhome conversion in this case. The delay was performed with analysis codes 8 and 10. Let the time of the output signal of the ADC for the maximum value of the code 15 is equal to tCapMan. Then the settling time for the code 8 will be twice less: tCAP=tCapMan8/16=0.5 to tCapManand for code 10-tCAP=tCapManl0/16=of 0.625 tCapMan. Thus, the total conversion time is equal to TCRtCAP+tCAP= (0,5+of 0.625)tCapMan= 1,125 tCapMan. For successive approximation ADC TCR= 4tCapMan. Thus, the conversion time is reduced by more than twice.

There may be occasions when time analog-to-digital conversion using the proposed device will be greater than when using successive approximation ADC, for example, if codes 1 and 15. If code 15 the conversion time TCR= 4,25 tCapManhowever , as follows from the table.1, the probability of this event is small enough. On average, the conversion time will be TCR= 1,76 tCapMan.

Thus, the proposed ADC can reduce the conversion time by applying optimal matching code and taking into account the time of establishing the voltage at the DAC output.

Anathema voltage and the first input device, and to the second input connected to the output of the digital to analogue Converter, the inputs of which are connected to the outputs of the register are the outputs of the device, the pulse generator, characterized in that it introduced trigger the one-shot, subtractive counter and a persistent storage device, the first outputs of which are connected to first inputs of the register, the first address inputs connected to the outputs of the register and the second address input coupled to the output of the comparison circuit, the first input of the trigger is the second input device, the trigger output, which is the second output device, connected to the first input of one-shot, the second input register and a control input of the pulse generator, the output of which is connected to a second input of the trigger and the first input of the subtractive counter, the output of which is connected to a second input of one-shot, the output of which is connected with the third input register and a second input of subtractive counter, the third input of which is connected to the second outputs of the permanent storage device, the third output of which is connected to the third input of the trigger.

 

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