Device for frame synchronization

 

(57) Abstract:

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal. The device frame synchronization contains the decoder of synchronously, environment unit, generating equipment, as well as the newly introduced random access memory device, the device configuration and diagnostics, the storage device criteria input in synchronism, and the storage device criteria exit synchronism. Device for frame synchronization allows you to synchronize the various transmission information with asynchronous merging of digital streams of the first to fourth levels recommended by the International Consultative Committee on Telephony and Telegraphy (CCITT Blue Book), as well as custom transmission of information, organized in conjunction with radio-relay lines, called radiosistemi, while significantly reducing equipment, which is the technical result achieved when implementing the present invention. 3 Il.

The invention relates to techniques for digital communication, namely, devices for the cyclic synchroblog synchronization [1, 2], comprising: a shift register, a detector clock cycle, the analyzer matches the clock generating equipment, elements, AND, OR, the inputs and outputs of the devices that are connected in a certain way.

The closest to the technical nature of the claimed invention is selected as a prototype of the device frame synchronization [3], containing the Recognizer synchronously consisting of a shift register and decoder blocks retention and retrieval of synchronism, power generating equipment, the unit selection clock frequency, channel allocator, the inputs and outputs of the device.

The disadvantages of this device are:

- the impossibility of the same device to synchronize the various transmission information with asynchronous merging of digital streams of the first to fourth levels recommended by the International Consultative Committee on Telephony and Telegraphy (CCITT Blue Book), as well as custom transmission of information, organized in conjunction with radio-relay lines, called radiosistemi;

- significant hardware costs, because the distribution of the positions of synchronously on the large length of the cycle (a few you who are waiting decoder and shift register, when you synchronize the digital transmission of information with different structures, without re-developing device frame synchronization.

An object of the invention is enhanced functionality, allowing synchronization of the various transmission information with asynchronous merging of digital streams of the first to fourth levels recommended by the International Consultative Committee on Telephony and Telegraphy (CCITT Blue Book), as well as custom transmission of information, organized in conjunction with radio-relay lines, called radiosistemi, and reducing equipment.

This task is solved in that the device for frame synchronization, containing the decoder of synchronously, generating equipment (TH), environment unit (FU), and clock input devices for frame synchronization (CA) connected to the respective input of the decoder synchronously and with the respective input, and the information input from the respective input of the decoder synchronously, the output end of synchronously which is connected with the corresponding input and the respective input FU, and the output response with the appropriate whoi is output having a synchronization device for CA address 0 - N outputs the SECOND address are output devices for CA, introduced random access memory (RAM) device configuration and diagnostics (UND), the storage device criteria (UHC) input in synchronism, the storage device criteria (UHC) output from the synchronism, with address 0 - N inputs of RAM connected with address 0-N outputs, and inputs the write, read, select, with the corresponding outputs of UND, the input-output end of the cycle the RAM is connected with the corresponding input, with zero input-output UND and an output end of the cycle the device for the CA, the input-output end of synchronously, the position of synchronously, values synchronously RAM connected to respective inputs of the decoder synchronously and respectively with the first, second and third inputs-outputs UND, clock output settings and exit setup to "0" which is connected to the corresponding inputs, clock output records UND respectively connected with a clock input write UHC input in synchronism and UHC exit synchronism, the first outputs of the write-enable and read permissions UND connected respectively with the entry permit and entry permit reading UHC input in synchronism, the second outputs resolution recording is of onosma, information 0 - N outputs configuration AND connected to respective inputs of UHC input in synchronism and UHC exit synchronism, 0 - N, the outputs of which are respectively connected with corresponding inputs UND, 0 - N outputs settings UHC input in synchronism respectively connected with the first 0 - N inputs FU, the second 0 - N inputs of which are connected with 0 - N outputs settings UHC output from the synchronism information 0 - N inputs and outputs, the inputs of the mode selection, the new address, set to "0", write, read, settings UND are the corresponding inputs of the device for the CA, the input mode is selected AND connected with the respective input.

Device configuration and diagnostics (UND) contains the first and eleventh inverters, from the first to the fourteenth two-input And gates of the first and second input elements OR the first and second triggers, gates of the first, second and third blocks of gates, the input of the first inverter is connected to the inputs of the first and second elements, OR is the entry mode selection of UND, the output of the first inverter is connected to the inputs of the first to sixth and tenth elements And input the new address UND is another input of the first element Anouki "0" UND is another input of the second element, And the output of which is connected to the inputs of the installation in the "0" of the first and second triggers, and is output setup to "0" UND, input recording UND is the input of the second inverter, the output of which is connected to another input of the third element And the input read UND is the input of the third inverter, the output of which is connected to another input of the fourth element And the input of the fourth inverter is connected to another input of the sixth element And is input settings UND, the output of the third element And is connected to the input of the eighth element And the input of the fifth inverter whose output is the output records UND, the fourth output element And is connected to another input of the first element OR the output of which is connected to the inputs of the ninth, tenth, and twelfth items And the sixth inverter, the output of the fifth element And is connected to other inputs of the seventh, eighth and ninth elements And the output of the sixth element And connected to the input of the eleventh element, And the other input of the twelfth element And another input of the second element OR the output of which is connected to the input of the seventh inverter whose output is the output of the selection of UND, the output of the sixth inverter connected to another input of the eleventh element, And and is output Teniente And is output cycles recording UND, the output of the ninth element And is connected to the inputs of the thirteenth and fourteenth elements And the outputs of the tenth and eleventh elements And are connected respectively to the control inputs of gates of the first and second block valves, the output of the twelfth element And connected to the input of the eighth inverter, the output of which is connected to control inputs of the gates of the third block of gates, the output of the first flip-flop connected to the input of the ninth inverter, the output of which is connected to another input of the thirteenth element And to the input of the second trigger, and is the first output recording resolution UND, the output of the second trigger connected to another input of the fourteenth element And the second output recording resolution of UND, the output of the fourteenth element And connected to the input of the eleventh inverter whose output is the second output of the read permissions UND, the output of the thirteenth element And connected to the input of the tenth inverter whose output is the first output of the read permissions UND, combined in pairs 0 - N outputs managed and appropriate inputs unmanaged gates of the first block valves are information 0 - N inputs-outputs UND, United pairwise zero, first, second and treude zero, first, second and third inputs-outputs UND, 0 - N outputs unmanaged gates of the first block valves connected to the zero, first, second and third inputs of the second controllable valves block valves and are the corresponding information 0 - N outputs settings UND, 0 - N inputs controllable valves of the first block valves connected to the zero, first, second and third outputs of gates of the third block valves and are 0 - N inputs AND outputs unmanaged second valves block valves connected to respective inputs of the third controllable valves block valves.

The novelty of technical solutions is available in the claimed device new circuit elements: operational storage device configuration and diagnostics, storage criteria input in synchronism, a storage device criteria exit synchronism.

Thus, the invention meets the criterion of "novelty."

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional units known. However, their introduction into the device for frame synchronization with the above links gives amatya costs and expand its functionality, ensuring the development of a single device synchronization of a large number of digital transmission of information.

Thus, the invention meets the criterion of "Inventive step", as it is for the expert is not obvious from the prior art.

The invention can be used in digital transmission systems higher-order Association with asynchronous digital stream.

Thus, the invention meets the criterion of "Industrial applicability".

In Fig.1 shows a structural electrical diagram of the device for frame synchronization, and Fig.2 is an electric diagram of the device configuration and diagnostics; Fig. 3 is a circuit diagram of the storage criteria input in synchronism and out of synchronism.

Device for frame synchronization (Fig.1) contains a random access memory 1 (RAM) device configuration and diagnostics 2 (UND), the storage device criteria (UHC) input in synchronism 3, the storage device criteria (UHC) output from the synchronism 4, the decoder synchronously 5, environment unit 6 (FU), generating equipment 7 (TH), and the clock input of the device for the cycle of sin is d - with the respective input of the decoder synchronously 5, the output end of synchronously (exit CSC) which is connected to the corresponding inputs of the FIRST and FU, and the output response (output IC) with the appropriate sign-FU, the zero output state (output DC"0") which is connected with the corresponding input, and the other output of the availability of synchronization (output PHASE) is the output device for the CA, address 0 - N outputs TH are the outputs of the device, the address 0 to N inputs of RAM connected with address 0 - N outputs, and recording inputs (input WE)read (input OE), select (log CE) RAM - with the corresponding outputs of UND, the input-output end of the cycle (output CC) RAM is connected with the corresponding input is ON and a zero input-output UND and an output end of the cycle the device for the CA, the input-output end of synchronously (CSC), the position of synchronously (UCS), the values of synchronously (PCC) RAM connected to respective inputs of the decoder synchronously and respectively with the first, second and third inputs-outputs UND, clock output settings (output T) and the installation exit to "0" (output RES) which is connected to the corresponding inputs, clock output write (output RG-WE) UND respectively connected with a clock input write (inputs WE) uhk I(output RG1-OE) UND connected respectively to the inputs of the write-enable (input EC) and read permissions (input OE) UHC input in synchronism, the second outputs of the write-enable (output RG2-EC) and read permissions (output RG2-OE) UND connected respectively to the inputs of the write-enable (input EC) and read permissions (input OE) UHC output from the synchronism information 0 - N outputs configuration AND connected to respective inputs of UHC input in synchronism and UHC exit synchronism, 0 - N, the outputs of which are respectively connected with corresponding inputs UND, 0 - N outputs settings UHC input in synchronism respectively connected with the first 0 - N inputs FU, second 0 - N inputs of which are connected with 0 - N outputs settings UHC output from the synchronism information 0 - N input-output, input mode selection (input settings/SLAVE), new address (input), set to "0" (input RES), write (log CE), read (input OE), settings (input setup RAM/RG) UND are the corresponding inputs of the device for the CA, the input mode is selected AND connected with the respective input.

Device configuration and diagnostics (UND) contains the first and eleventh inverters 8 - 18, from the first to the fourteenth input elements And 19 - 32, first and second input elements OR 33 and 34, the first and second triggers 35 and 36, the valves of the first, second and third block is tsya input mode selection UND, the output of the first inverter 8 is connected to the inputs of the first to sixth and tenth elements And 19 - 24 and 28, the input of the new address (input) UND is another input of the first element And 19, the output of which is connected to the input of the seventh element And 25 and is clocked output settings (output T) UND, input set to "0" (input RES) UND is another input of the second element 20, the output of which is connected to the inputs of the installation in the "0" of the first and second triggers 35, 36 and is output setup to "0" (output RES) UND, input recording (input WE) UND is the input of the second inverter 9, the output of which is connected to another input of the third element And 21, the input read (input OE) UND is the input of the third inverter 10, the output of which is connected to another input of the fourth element And 22, the input of the fourth inverter is connected to another input of the sixth element 24 And is input settings UND (input settings RAM/RG), the output of the third element And 21 is connected to the inputs of the eighth element 26 And the input of the fifth inverter 12, the output of which is a recording output (output WE) UND, the output of the fourth element And 22 connected to another input of the first element OR 33, the output of which is connected to the inputs of the ninth, tenth, and twelfth items And 27, 28 and 30 and the sixth inverter 13, Vistula element And 24 connected to the input of the eleventh element And 29, the other input of the twelfth elements And 30 and the other input of the second element OR 34, the output of which is connected to the input of the seventh inverter 14, the output of which is output select (output CE) UND, the output of the sixth inverter 13 is connected to another input of the eleventh element And 29 and is output read (output OE) UND, the output of the seventh element And 25 is connected to the clock inputs of the first and second triggers 35 and 36, the output of the eighth element And 26 is the output of clock cycles write (output RG-WE) UND, the output of the ninth element And 27 is connected to the inputs of the thirteenth and fourteenth elements 31 and 32, the outputs of the tenth and eleventh elements 28 and 29 are connected respectively to the control inputs of gates of the first and second block valves 37 and 38, the output of the twelfth item And 30 connected to the input of the eighth inverter 15, the output of which is connected to control inputs of the gates of the third block valves 39, the output of the first flip-flop 35 is connected to the input of the ninth inverter 16, the output of which is connected to another input of the thirteenth element And 31, input of the second trigger 36 and is the first output of the write-enable (output RG1-EC) UND, the output of the second trigger 36 is connected to another input of the element 32 and the second output permission zaporog is the second access authorization reader (exit RG2-OE) UND, the output of the thirteenth element 31 is connected to the input of the tenth inverter 17, the output of which is the first access authorization reader (output RG 1st) UND, combined in pairs 0 - N outputs managed and appropriate inputs unmanaged gates of the first block valves 37 are information 0 - N inputs-outputs AND combined in pairs of zero, first, second and third outputs of the controllable valves and the corresponding inputs unmanaged second valves block valves 38 are zero, first, second and third inputs - outputs UND, 0 - N outputs unmanaged gates of the first block valve 37 is connected to the zero, first, second and third inputs of the second controllable valves block valves 38 and are relevant information 0 - N outputs settings UND, 0 - N inputs controllable valves of the first block valve 37 is connected to the zero, first, second and third outputs of gates of the third block valves 39 and are 0 - N inputs AND outputs unmanaged gates of the second block valve 38 connected to respective inputs of the third controllable valves block valves 39.

The storage device criteria (UHC) input in synchronism, and the storage device criteria (UHC) vichadero remember connected with information 0 - N inputs settings UHC input in synchronism (out of synchronism), enabling inputs (inputs EC) triggers memory connected to the input of the write-enable (input EC) UHC input in synchronism (out of synchronism), the clock inputs of flip memorization is connected with a clock input write (input WE) UHC input in synchronism (out of synchronism), 0 - N, the outputs of the triggers memory connected to respective information 0 - N inputs controllable valves, and 0 - N outputs settings UHC input in synchronism (out of synchronism), the control inputs of gates connected to the enable input read (input OE), and 0 - N outputs of gates with 0 - N outputs UHC input in synchronism (out of synchronism).

Device for frame synchronization works as follows.

Device for frame synchronization (CA) has two modes of operation. The first mode of operation and diagnosis, the second mode of operation. In the first mode, the input device settings and diagnostics 2 (UND) receives signals from the controller working in conjunction with the personal electronic computing machine (PC). Mode settings and diagnostics allowed the signal Log. "0", which is fed to the input selection mode AND,Oh, the fifth, sixth and tenth elements And 19 - 24 and 28. The Signal Log. "1", input settings UND, enables configuration random access memory device 1 (RAM), and the signal Log. "1" output of the sixth element, And 24 may be permitted eleventh and twelfth elements 29 and 30, and the signal received via the second element 34 and the seventh inverter 14 to the output selection UND and next to the appropriate input of RAM, allowed the use of the latter. On the input set to "0" AND a signal, which via the open second element 20 with its corresponding output goes into generating equipment 7 (TH), setting its counter positions in the initial state. Address 0 - N outputs connected to respective FIRST inputs of RAM. The signals from the controller, the incoming information 0 - N input-output UND arrive at the corresponding inputs of unmanaged gates of the first block valve 37, and further inputs controllable valves of the second block valves 38. Managed the gates of the second block valves 38 are opened by the output signal of the eleventh element And 29. Managed the gates of the first block valve 37 and the third block valves 39 are closed, while in the third state, respectively, the signals from the outputs of the de is through the second inverter 9, open the third element And 21 and the fifth inverter 12 to the output record UND connected with the respective input of RAM. On a given signal in the discharge position of the end of the cycle, the end of synchronously, the position of synchronously, values synchronously RAM is write data, respectively, with the zero, first, second and third input-output UND. Then input the new address AND receive a signal via the open first item 19 and a clock output settings AND goes to the correct input, changing the state of the counter. Then write data to RAM at the new address is the same as described above.

To determine the correct configuration of the RAM setting signal to zero AND counter positions TH is set to the initial state. The Signal Log. "0" is fed to the input of the read AND continue through the third inverter 10, an outdoor fourth element And 22 and the first element OR 33 to the inputs open the tenth and twelfth elements 28 and 30 and the input of the sixth inverter 13. Thus the output signal of the tenth element And 28 are allowed to pass data through controlled valves of the first block valve 37, the output signal of the twelfth item, And 30 through eighth inserterror 13 through outdoor eleventh element And 29 prohibits the passage of signals through controlled valves of the second block valves 38. The Signal Log. "0" output of the sixth inverter 13 is supplied to the output reading UND and next to the appropriate input of RAM. Data from input-output discharge end of the cycle, the end of synchronously, the position of synchronously, values synchronously RAM are received respectively at the zero, first, second and third inputs and outputs UND and then through unmanaged valves of the second block valve 38 operated valves of the third block valve 39 operated valves of the first block valves 37 and information 0 - N input-output UND arrive in the controller of the personal computer (PC) to compare them with the original. The signal at the input of the new address AND, as described above, change of address RAM and reading its data.

Configuring UHC input in synchronism and UHC exit synchronism begins when input settings UND signal Log. "0", which opens through the fourth inverter 11 and the fifth element And 23 of the seventh, eighth and ninth elements 25, 26 and 27 and closes the sixth element, And 24, the output signal which closes the eleventh and twelfth elements 29 and 30. Thus the output signal of the seventh inverter 14, which is the output of the signal selection UND,RA 15 managed closed the gates of the second and third blocks of gates 38 and 39. The signal on the input set to "0" AND, passing through the open second And gate 20, is fed to the inputs of the installation in the "0" of the first and second triggers 35 and 36, setting them to zero state. The output signal of the ninth inverter 16 through the first output recording resolution UND received at the corresponding input UHC input in synchronism, it is permitted to write data via the data 0 to N inputs triggers the memory of this device. Recording data with information 0 - N outputs unmanaged gates of the first block valve 37 AND to corresponding inputs of UHC input in synchronism, is a signal with a clock output records UND arriving at the clock input write UHC input in synchronism. The signal at the input of a new address AND continue through the open first item 19 and outdoor seventh element And 25 on the clock inputs of the first and second triggers 35 and 36, the latter established in one state. When this signal Log. "0" output of the ninth inverter 16, the received first output recording resolution UND and further enable input write UHC input in synchronism, it is prohibited to write data in triggers memory of this device, and the output signal of the second three the of synchronism, allowed to write data in triggers memory of this device. Similarly to the above-described information recording in UHC output from the synchronism signal is received at a clock input write UHC exit synchronism. In configuration mode controlled valves UHC input in synchronism and UHC exit synchronism closed and are in the third state.

The correct configuration of UHC input in synchronism and UHC output from the synchronism is defined as follows.

The signal on the input set to "0" AND, as described above, the first and second triggers 35 and 36 are set in the zero state, is permitted in the thirteenth element And 31 and prohibited the fourteenth item And 32. The signal read from the output of the open ninth element And 27 through outdoor thirteenth element 31 and the tenth inverter 17 AND is supplied to the first output read permissions UND and next to the appropriate input of UHC input in synchronism. The signal from the enable input read UHC input in synchronism opens the valves, and the information stored triggers memory comes in 0-N outputs UHC input in synchronism 0 - N inputs UND and forth through the open gates of the first block is th address UND, the first and second triggers 35 and 36 are in one state, allowing the passage of the signal through the fourteenth element 32 and the eleventh inverter 18 to the second output of the read permissions UND and next to the appropriate input of UHC exit synchronism. Further work is also carried out as described for UHC input in synchronism.

In configuration mode and diagnostics on the clock input of counter positions TH receives clock pulses from a clock output configuration UND, and in mode clock input of counter positions TH receives clock pulses from clock input devices for CA.

The transfer device for the CA mode is performed by the signal Log. "1" at the input of the mode selection UND. At the same time on the clock input TH receive clock pulses from the respective input devices for CA. At address 0 - N inputs of RAM from address 0 - N outputs the ON signals of the account, at the output end of the cycle, the end of synchronously, the position of synchronously, values synchronously RAM are formed corresponding signals. According to the signal output end of the cycle in TH is synchronous setting in the initial state of the counter positions of a clock pulse with tactoe, the position of synchronously and values of synchronously RAM, and clock and information pulses from the clock and data inputs of the device for the CA act to corresponding inputs of a decoder of synchronously 5. The decoder of synchronously 5 performs element-by-element comparison of the information pulses with predetermined values synchronously output values synchronously RAM on the respective positions of synchronously and the formation of a result of comparison of the output response, as well as the formation of the signal at the output end of synchronously decoder of synchronously 5. Signal the end of synchronously the output of the decoder of synchronously 5 is formed with a time delay relative to the signal response. In case of coincidence of signals from the inputs of the position of synchronously and values of synchronously with the input information sequence at the output of the response of the decoder synchronously 5, a signal is generated Log. "1", when the mismatch signal Log. "0". The output signal of the response and the output end of synchronously decoder of synchronously 5 go to corresponding inputs of a FU. For the first 0 - N inputs and the second 0 - N inputs FU received signals, respectively, with 0 - N is eusto 6 (FU) works as follows. In the absence of the input of the response signal Log. "1", i.e., a positive response to the presence of synchronously with the corresponding output of the decoder, synchronously 5 reversible counter is in the zero state. The output signal from the zero state FU allowed the use of the remover in tact. Upon receipt of a positive response to the input of the response signal to the input end of synchronously FU with the respective outputs of the decoder synchronously 5, the reversible counter FU is installed in the positive mode account and increases its state unit. Thus the output signal from the zero state FU prohibited operation of the remover in tact. Thus, when the presence of a signal decode synchronously reversible counter FU increases your status on the unit, and in the absence decreases by one. When the signal difference in the number of presence and absence of synchronously reaches a predetermined criteria value is input in synchronism, upon receipt of the next signal the presence of synchronously reversible counter FU is set to the maximum state. Thus, the device for the CA enters the mode of synchronism, as evidenced by the signal Log. "1" at the output of the I and the lack of synchronously reaches the specified criteria value output from the synchronism. When this FU set to the zero state, and a device for the CA enters the search mode matching, as described above.

For the technical realization of the device for frame synchronization used static random access memory (RAM) and programmable logic integrated circuit (PPLIS).

The present invention allows synchronization of the various transmission information with asynchronous merging of digital streams of the first to fourth levels recommended by the International Consultative Committee on Telephony and Telegraphy (CCITT Blue Book), as well as custom transmission of information, organized in conjunction with radio-relay lines, called radiosistemi, while significantly reducing equipment.

Sources of information

1. RF patent 2019046, H 04 L 7.08.

2. RF patent 2136111, H 04 L 7.08.

3. Levin, L. S., Plotkin, M. A. Digital communication system. M.: Radio and communication, pages 102-103, Fig. 4.4.

1. Device for frame synchronization, containing the decoder of synchronously, generating equipment (TH), environment unit (FU), and the clock input of the device to the CEC the entrance, and the information input from the respective input of the decoder synchronously, the output end of synchronously which is connected with the corresponding input and with the respective input FU, and the output response with the respective input FU, the zero output state of which is connected with the corresponding input, and the output of the availability of synchronization is output having a synchronization device for CA, address 0 - N outputs the SECOND address are output devices for CA, characterized in that the input random access memory (RAM) device configuration and diagnostics (UND), the storage device criteria (UHC) input in synchronism, the storage device criteria (UHC) output from the synchronism, with address 0 - N inputs of RAM connected with address 0 - N outputs, and inputs the write, read, select, with the corresponding outputs of UND, the input-output end of the cycle the RAM is connected with the corresponding input, with zero input-output UND and an output end of the cycle the device for the CA, the input-output end of synchronously, the position of synchronously, values synchronously RAM connected to respective inputs of the decoder synchronously and respectively with the first, second and third inputs-outputs UND, the entry UND respectively connected with a clock input write UHC input in synchronism and UHC exit synchronism, the first outputs of the write-enable and read permissions UND connected respectively with the entry permit and entry permit reading UHC input in synchronism, the second outputs of the write-enable and read permissions UND connected with the entry permit and entry permit reading UHC output from the synchronism information 0 - N outputs configuration AND connected to respective inputs of UHC input in synchronism and UHC exit synchronism, 0 - N, the outputs of which are respectively connected with corresponding inputs UND, 0 - N outputs settings UHC input in synchronism respectively connected with the first 0 - N inputs FU, the second 0 - N inputs of which are connected with 0 - N outputs settings UHC output from the synchronism information 0 - N inputs and outputs, the inputs of the mode selection, the new address, set to "0", write, read, configure, UND are the corresponding inputs of the device for the CA, the input mode is selected AND connected with the respective input.

2. The device under item 1, characterized in that the device configuration and diagnostics (UND) contains the first and eleventh inverters, from the first to the fourteenth two-input And gates of the first and second input elements And the RA is connected to the inputs of the first and second elements, OR is the selection input mode UND, the output of the first inverter is connected to the inputs of the first to sixth and tenth elements And input the new address UND is another input of the first element And whose output is connected to the input of the seventh element And is clocked output settings UND, input set to "0" AND is the other input of the second element And whose output is connected to the inputs of the installation in the "0" of the first and second triggers, and is output setup to "0" UND, input recording UND is the input of the second inverter, the output of which is connected to another input of the third element And the sign read UND is the input of the third inverter, the output of which is connected to another input of the fourth element And the input of the fourth inverter is connected to another input of the sixth element And is input settings UND, the output of the third element And is connected to the input of the eighth element And the input of the fifth inverter, the output of which is a recording output AND the fourth output element And is connected to another input of the first element OR the output of which is connected to the inputs of the ninth, tenth, and twelfth items And the sixth inverter, the output of the fifth element And is connected to other inputs of the seventh, eighth and ninth elements, And the output of the sixth element And coedine OR the output of which is connected to the input of the seventh inverter whose output is the output of the selection of UND, the output of the sixth inverter connected to another input of the eleventh element And an output reading of the UND, the output of the seventh element And is connected to the clock inputs of the first and second triggers, the output of the eighth element is the output of clock cycles of the write-UND, the output of the tenth element And is connected to the inputs of the thirteenth and fourteenth elements And the outputs of the tenth and eleventh elements And are connected respectively to the control inputs of gates of the first and second block valves, the output of the twelfth element And connected to the input of the eighth inverter, the output of which is connected to control inputs of the gates of the third block of gates, the output of the first flip-flop connected to the input of the ninth inverter, the output of which is connected to another input of the thirteenth element And to the input of the second trigger, and is the first output recording resolution of UND, the output of the second trigger connected to another input of the fourteenth element and the second output recording resolution of UND, the output of the fourteenth element And connected to the input of the eleventh inverter whose output is the second output of the read permissions UND you is resheniya read UND, combined in pairs 0 - N outputs managed and appropriate inputs unmanaged gates of the first block valves are information 0 - N inputs-outputs AND combined in pairs of zero, first, second and third outputs of the controllable valves and the corresponding inputs unmanaged second valves block valves are zero, first, second and third inputs-outputs UND, 0 - N outputs unmanaged gates of the first block valves connected to the zero, first, second, and third inputs of the second controllable valves block valves and are the corresponding information 0 - N outputs settings UND, 0 - N inputs controllable valves of the first block valves connected to the zero, first, second and third outputs of gates of the third block valves and are 0 - N inputs AND outputs unmanaged second valves block valves connected to respective inputs of the third controllable valves block valves.

 

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1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

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