Generator quasiorthogonal opposite signals

 

(57) Abstract:

The invention relates to automation and computer engineering and can be used in communication systems employing digital methods for the formation of large systems of complex signals. The technical result consists in extending the functionality of the device by increasing the number of generated signals to the value of the square base encoding L=B2when the value of reorthogonalize R=1/3 and a small amount of used memory. The device includes a block inversion of the sign, item OR clock generator and modulo (- 1), m-bit binary counter module, executed with the output of the overflow register have increased capacity with third n-bit information input and output, the memory block is performed with the increased capacity of the n-bit second address input. 3 Il., table 2.

The invention relates to automation and computer engineering and can be used in radio communication systems with noise-like signals using digital methods for the formation of large systems of complex signals [1,2] . For a given database encoding generated by the device L=B2Polyarnaya synthesis of large systems quasiorthogonal phase-shift keyed signals (similar to [4], S. 37; [3]) or frequency-phase-shift keyed signals.

The number of known devices [2,5,6], which can be used to form complex systems of temporary signals of period T value of reorthogonalize (maximum peak level of intercorrelation function between any pair of signals i(t) andj(t)

< / BR>
For polar-shift keyed signals based on the specified group of error-correcting (B, L, d)-codes with code distance d and power L=2kcode words the value of reorthogonalize is calculated by the formula

R =|(B-2d)/B|. (2)

As a rule (see [1], S. 101-102), systems of orthogonal signals with R=0 based on (In,L=B,d=B/2)-codes Hadamard matrices. For example, for the formation of a system of orthogonal signals can be used a function generator Walsh [5], which contains the memory block and the group of adders modulo two. A disadvantage of the known device [5] is a small volume system signals L=B, causing very low relative speed of information transmission

r=]log2L[/B (3)

where ]x[ - integer part of the number X.

In [3] based on nonlinear code with more power instead of rows of the Hadamard matrix generated by the recurrent rule Forces jemimah intercorrelation properties R=1/3 disadvantage ensemble [3] is a small number of signals L<B causing a small relative velocity r=2m/3m.

On the basis of codes Bose-Chowdhury (see [2], S. 254, PL.6.4) built in General invariant to cyclic shift system temporal phase-shift keyed signals with parameters L=(B+1)2R=0,26 with databases encoding= 127 and B=255. A disadvantage of the known systems of signals [2], some of which is equivalent to system gold, is that for small values of base encoding<100 value reorthogonalize between any pair of signals is R>1/2.

Closest to the proposed device is a generator orthogonal opposite signals [6], which contains the register, clock generator, the m-bit counter module In the first logical element And characteristic overflow (reset) counter, modulo (- 1), where In is the number of pulses in the generated quasiorthogonal-opposite signal, the memory block, the second logic element And characteristic of a single signal "11...1", the logical element OR Assembly of the signal, the unit of inversion of the sign, moreover, single-bit and m-bit information input register is the control inputs of the device, and a single-bit output register is connected with the control of vatera and with the inputs of the second element, And the output of the second element And connected to the first input element OR the counting input of the counter is connected to the output of the clock generator, the information output of the meter is connected bitwise with the inputs of the second term of the adder and to the inputs of the first element And the counter overflow, the output of the first element And connected with the control input of the write register and a second input element OR m-bit input of the memory block bitwise connected to the output sum of the adder, the output of the memory block is connected to the third input of logic element OR the output element OR is connected with the information input unit of inversion of the sign, the output of the inversion of the sign is the output device.

The disadvantage of this generator orthogonal opposite signals [6] is a small volume generated signal systems L=2V, causing low relative velocity r=(m+1)/2m.

Task - extending the functionality of the device by increasing the number of generated signals quasiorthogonal-the opposite of the system L=B2when the acceptable value of reorthogonalize R=1/3 and a small amount of used memory.

This object is achieved in that in the us ocny counter modulo and modulo (- 1), where is the number of pulses in the generated quasiorthogonal-opposite signal, and the first bit and the second m-bit information inputs of the register are the two control inputs of the device, the first single-bit output register is connected with the control input of the inversion of the sign, the second m-bit output register and an information output m-bit binary counter module In a bitwise connected respectively with m-bit inputs of the first and second components of modulo (- 1), m-bit output sum of the adder module (In-1) bitwise connected to the m-bit address input of the memory block, the output of the memory block connected to the first input element OR the output element OR is connected with the information input unit of inversion of the sign, the output of block inversion of the sign serves as an output device, and the counting input m-bit binary counter on the module is connected to the output of the clock generator, wherein the m-bit binary counter module To be accomplished by the output of the overflow register is made larger capacity with third n-bit information input and output, the memory block is made larger capacity with n-bit second address input, and output periodon register entries, the third n-bit information output register connected bitwise with the second n-bit address input of the memory block, and the third n-bit information input register as the third managing input devices.

In the proposed device as a binary code sequences system quasiorthogonal opposite signals are binary code words nonlinear (12,144,4) code that can correct one error. For a system of signals with parameters B=12, L=B2=144, R=1/3 132 code word group (12,144,4)-code are set in blocks of combinatorial schemes Steiner S(5,6,12) (see[7], 2.7, S. 78-79, theorem 30). 12 incremental code words (see[7], Fig.2.16) consist of 6 codewords of weight 2 with code distance d= 4 and the opposite (inverse, supplemented by module two). To reduce the amount of memory used in the proposed device uses a cyclic combinatorial scheme Steiner S(5,6,12) (see[8], S. 83, PL. 3.18, the scheme above 3) set of basic blocks:

(,0,1,2,6,9), (,0,1,2,3,5), (,0,1,2,7,8), (4)

(,0,1,3,4,7), (,0,1,3,6,8), (,0,1,5,7,9) all mod II,

and the opposite (inverse) in the binary representation:

(3,4,5,7,8,10), (4,6,7,8,9,10), (3,4,5,6,9,10), (5)

(2,5,6,8,9,10), (2,4,5,7,9,10), (2,3,4,6,8,10) all mod II.

In us) mod 12 period 6, (6)

and uses six opposite codewords of weight "10":

(1,2,3,4,5,7,8,9,10,11) mod 12 period 6. (7)

The essential difference between the proposed device known from descriptions [7] (12,144,4)-code is that the application of cyclic t-schema Steiner allows you to store in memory only the basic code sequence, relative to which other signals can be calculated in real time using the modulo (- 1). In comparison with the prototype [6] the proposed device allows you to generate orthogonal opposite signal on the basis of the base unit combinatorial 3-schema Hadamard, and to increase the total number of signals quasiorthogonal opposite system instead of two incremental code sequences isolated "11. ..1" and zero "00...0" signals in the device 12 is used incremental code sequences of the weight of "2" and "10". In comparison with recurrent build rule quasiorthogonal ensemble of signals [3] the proposed device with the same mutual correlation properties of R=1/3, you can increase system signals to the value of the square base encoding L=B2. Compared with the systems temporary phase and magnitude of reorthogonalize R>0.5 of the proposed device allows you to generate the signals volume L=B2with the best of intercorrelation properties R=1/3. Thus, the proposed device is substantially different from the known (2,3,6,7]. Embodiments of the generator quasiorthogonal signals were examined in an unpublished application materials [9,10].

Functional diagram generator quasiorthogonal opposite signals shown in Fig.1, in Fig.2 is a timing diagram of operation of the device of Fig.3 - view 22 of 144 generated signals. The base code sequence (12,144,4) code recorded in the memory unit, are presented in table. 1. The generator is characterized by a table.2.

Generator quasiorthogonal opposite signal register 1 contains integral number of signal (U1, U2, U3), block 2 inversion of the sign of m-bit binary counter 3 on the module, the adder 4 to the module (V-1), unit 5 memory, the logical element OR 6 Assembly signal, the clock generator 7, and a single-bit information input N1 of the register 1 is input to the inversion of polarity-shift keyed signals quasiorthogonal system to the opposite value, n-bit L2 and m-bit U3 informational inputs of register 1 are respectively the inputs of the choice of the reference code sequence is shining input unit 2 inversion of the sign, m-bit output of the register 1 and the information output of the counter 3 bitwise connected respectively to the inputs of the first and second components of the adder 4, m-bit output sum of the adder and n-bit output register 1 bit connected to respective groups of the address inputs of the memory block 5, the output unit 5 memory connected to the first input of the logical element OR 6, the counting input of the counter 3 is connected to the output of the clock generator 1, the output of the overflow of the counter 3 is connected with the control input of the register entries 1 and with a second input element OR 6, the output of the OR element 6 is connected to the information input unit 2 inversion of the sign, the output of block 2 of the inversion of the sign is output.

Input register 1 is designed to receive and store the digital codes of the compound numbers (U1, U2, U3) for the entire period of time the formation of a complex signal:

code N1(0,1} determines the type of polar-shift keyed signal in the forward or opposite code;

code U2{ 0,1,....,7} selects one of the 8 basic binary code sequences (12,144,4) code recorded in the memory block 5;

code U3{0,1,....,10} when m=4 and B=12, supplied to the second input of the register 1, specifies the number of bits in the selected base code placentas the output bus of the device is performed under the influence of logical level "1", incoming control (clock) input of the write register 1. Changing the information on an output bus of register 1 is at a negative difference at the control input record, i.e. at the beginning of each period. In the presence of the control input is the logical level "0" case 1 carries out storing the received information at all times T generate a complex signal.

Unit 2 inversion of the sign allows to obtain an output signal in the forward or opposite code depending on the control logic level to a single-bit output of the register 1. In addition, in the function block 2, a transition from logic level "0","1" to the analog values"+1", "-1".

Count 3, count the clock pulses from the generator 7, specifies the period T=2PandIn quasiorthogonal opposite signals. At the end of each period on the logical state "1011" of the counter 3 produces a logic level "1" at the output of the overflow (reset) counter 3. This signal controls the reception of the input information in the register 1, and the recording is performed at the beginning of each period.

The adder 4 to the module (B-1) from the current state of the counter 3 for the module and constant (period T) offset, sadandlonely from unit 5 memory.

In block 5 of the memory contains a binary code sequence of basic blocks cyclic combinatorial schemes Steiner S(5,6,12), presented in the first six rows of the table.1, and two basic binary code sequence for the formation of 12 incremental signals quasiorthogonal opposite system, consisting of only 144 signals with the magnitude of reorthogonalize R=1/3.

Element OR 6 performs the function of logical Assembly of signals, combining in a single code sequence (B-1) bits from the output of the unit 5 memory and logic level "1" output from the overflow of the counter 3 at the end of each period So

Generator quasiorthogonal opposite signals is as follows.

When turning on the power source (Fig.1 not shown) is supplied the impetus for the installation in the logical state "1011" of the counter 3 module=12 and for the installation in one state push-pull D trigger input register 1, so with a single-bit output of register 1 to logic level "1" is supplied to the control input of block 2 of the inversion of the sign. Output counter overflow 3 logic level "1" is supplied to the control input of the register 1, turning it into receive mode (n+m+1)-bit digital listwa is set to a positive potential of a single amplitude "+1".

The clock generator 7 begins to produce pulses with a repetition period Tandwho is coming to the counting input of the binary counter 3. After the first clock pulse counter 3 from condition (B-1) goes to zero state, while the logic level "0" output from the reset of the counter 3 is supplied to the control input of the register 1, turning it into a storage mode of the input code composite numbers (U1,U2,U3) for all time T=Wandgenerating a complex signal. The logic level "0" or "1" according to the input code N1 with single-bit output of the register 1 is supplied to the control input of block 2 of the inversion of the sign to generate polar-shift keyed signal quasiorthogonal system in the forward or opposite (inverse) of the code. With n-bit output of the register 1 to the appropriate group of address inputs of the memory block 5 receives the binary code U2{0,1,....,7}, in accordance with a value which selects one of the rows of the matrix memory block 5, that is, selects one of the 8 binary base code sequences (12,144,4) code. With m-bit output of the register 1 to the input of the first addend adder 4 modulo (B-1) receives the binary code U3{ 0,1, ...,10}, in compliance with the number of bits in the selected base code sequence.

Under the influence of each clock pulse counter 3 from state -1 enters state digital code which is fed to the input of the second term of the adder 4. From the output of the adder 4 the calculated amount

h = (U3+)mod(B-1) (8)

goes to the appropriate group m address inputs of the memory block 5. Ordinal h selects a column in a matrix memory block 5. Bit value located at the intersection of the N2-th row and n-th column flows through the element OR 6 on the information input unit 2 inversion of the sign. Thus, under the influence of (B-1) clock pulses sequentially looping through the all (B-1) bits of the pre-selected code N2 binary code sequence, starting with bit ordinal U3 and ending bit ordinal (U3-1) mod(B-1).

When the transition counter 3 in the condition (B-1) logic level "1" output from the overflow of the counter 3 is supplied to the control input register entries 1 and through the element OR 6 on the information input unit 2 inversion of the sign. Depending on the value of the bit "0" or "1" at the control input unit 2, the output of the device at time T is set to the voltage level of unit amplitude neg is+m+1) times row binary code - non quasiorthogonal opposite signal. Under the influence of the following clock cycle of device operation is repeated.

To the timing charts of the operation of the device (Fig.2) shows that the counter 3 modulo In (charts top 10,11,...,13) performs the division of the repetition frequency of clock pulses received at its counting input with the output of the clock generator 7 (chart 9). If the counter 3 becomes the condition (B-1), its output overflow is set to logic level "1" (figure 14), and register 1 receives the input eight-bit bus device binary digital codes N1,N2,N3 (chart 1,2,...,8). After the next clock pulse counter 3 becomes zero state at the output of the overflow is set to logic level "0" and the register 1 goes into storage mode input codes N1,N2,N3 for all time T generate a complex signal (chart 15,16,....,22). For time T at the inputs of register 1 are prepared new digital codes N1,N2,N3 (chart 1,2,...,8). In the process of formation of the complex signal at the output of the element OR 6 (chart 24) logic level "1" is supplied from the output of the memory block 5 (figure 23) and output counter overflow 3 (chart 1A of the case 1 (figure 15) is formed output polar-shift keyed signal generator (figure 25) in the forward or opposite code.

In table.2, the symbols "+" and "-" indicate pulses of unit amplitude positive and negative polarity, respectively. Depending on the 8-bit input code (U1,U2,U3) (PL.2 columns with 2-th to 9-th) generated from 1 144 dvenadcatiletnih polar-shift keyed signals (in the table.2 columns from 10th to 21st). Similar to the prototype [6] the proposed device allows you to generate relative to the base binary code sequence 3-schema Hadamard recorded in the first row of the table.1, orthogonal opposite signals shown in Fig.3 and in the first 22 rows of the table.2. In table. 2 first eleven signalsi(t)j(t) (Fig.3(A)) form an orthogonal system as in accordance with formula (1) R=0. The second eleven signalsi(t)j(t) (Fig. 3 (B), in table.2 rows; 12,13,..,22) also form an orthogonal system with R=0. Signalsi(t) andi(t) the opposite when Quasiorthogonal system with the value of reorthogonalize R=1/3 form 66 polar-shift keyed signals on the basis of cyclic combinatorial schemes Steiner S(4,5,11) (PL.2 lines 1,2,..,11; 23,24,..,33; 43,44,..,55; 67,68,..,77; 89,90,..,99; 111,112,..,121) and 6 incremental signals (in the table.2 lines 133,134,..,137; 143).

The advantage of the proposed us what is to a greater extent L of the system signals with the same maximum peak levels of intercorrelation function R=1 /3 and more than two times smaller base encoding Century For example, in [3](see S. 69) shows the ensemble quasiorthogonal signals with parameters B=27, L=64 and R=1/3. The proposed device with a smaller database encoding (12 instead of 27) and with the same amount of reorthogonalize generates with regard to the opposite, more than twice the signal L (144 instead of 64), which increases the relative transmission rate r in accordance with the expression (4) from 0.22 to 0.58.

In addition, the proposed device can be used in two modes of operation. In the mode of information transfer speed r=0,58 quasiorthogonal opposite signals with the magnitude of reorthogonalize R=1/3, and similar to the prototype [6] in the transmission mode information, for selenaselena communication channels with rate r=1/3 orthogonal opposite signals with R=0.

Similarly, [3] on the basis of the proposed device can be constructed system of signals with parameters L=B, R=1/3 in base encoding=12mand r= 7m/12mwhere m is an integer.

Sources of information

1. Varakin L. E. communication Systems with noise-like signals. - M.: Radio and communication, 1985.- 383 C.

2. Mobile radio systems / I. M. Pyshkin, I. I. Duty, C. N. Talyzin, D. Tzvelev; Ed. by I. M. Pushkina.-trovesi, 1977, 6, S. 67-72.

4. Portnoy, S. L. , Moscow A. E., Maev O. I. Foreign Radioelectronics, 1968, 1 C. 26-43.

5. Cogolin P. M., Sadykov, R. H., Cherenkov A. C., Golden, S. A. the function Generator Walsh / USSR Author's certificate 1324018, MKI G 06 F 1/02.

6. Grichenko N. I., Lysakowski A. F., Shevchuk P.F. Generator orthogonal opposite signals / USSR Author's certificate 1697071 A1, MKI G 06 F 1/02.

7. Mack-Williams, U. D., Sloan N. J.A. theory of codes, ispravilasi errors.- M: Communications, 1979.- 744 S.

8. Hanani, H., Hartman, A., Kramer, E. S. On three-designs of small order. Disret Mathematics 45(1983), 75-93. (North-Holland Publishing Company).

9. Grinenko N. And., Lysakowski A. F., Velichko, A., Oplatka, A. Generator quasiorthogonal signals / Application VNIIKP 4769688/24 (149052) from 13.12.89; p/o 16.07.90 form 3/20 from 20.06.90.

10. Baikov Century , Shelobanova N. The conclusion of the examination Department 24 VNIIKP: form 3/20, 242675 from 17.09.90.

Generator quasiorthogonal opposite signals containing the register block inversion mark, a memory unit, element, OR, a clock generator, an m-bit binary counter modulo and modulo (- 1), where In is the number of pulses in the generated quasiorthogonal-opposite signal, and the first bit and the second m-bit infra connected with the control input of the inversion of the sign, the second m-bit output register and an information output m-bit binary counter module In a bitwise connected respectively with m-bit inputs of the first and second components of modulo (- 1), m-bit output sum of the adder modulo (- 1) bitwise connected to the m-bit address input of the memory block, the output of the memory block connected to the first input element OR the output element OR is connected with the information input unit of inversion of the sign, the output of block inversion of the sign serves as the output device, and the counting input m-bit binary counter on the module is connected to the output of the clock generator, wherein the m-bit binary counter module To be accomplished by the output of the overflow register have increased capacity with third n-bit information input and output, the memory block is performed with the increased capacity of the n-bit second address input, and the output of the overflow m-bit binary counter on the module is connected to the second input of the OR element and with the control input of register entries, the third n-bit information output register connected bitwise with the second n-bit address input of the memory block, and the third n-bit information input re

 

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