The method of generating scrambling code in the mobile communication system of usma and device for its implementation

 

(57) Abstract:

The invention relates to the field of generation scramblers codes in a mobile communication system. The device generating scramblers codes for transmitter downlink in a mobile communication system, USMA (universal mobile telecommunication system) contains the generator of the first m-sequence generator of the second m-sequence, the first adder, the set of first and second mask sections, many of the second adders, the output of which generates many secondary scramblers codes. Technical result achieved - generation scramblers codes combined into blocks of a given length, using masking capabilities, resulting in minimizing the complexity of the hardware. 4 C. and 26 C.p. f-crystals, 11 ill.

THE TECHNICAL FIELD TO WHICH THE INVENTION RELATES

The invention relates in General to a device and method of generating scramblers codes in mobile communication system and, in particular, relates to devices and method of generating multiple scrambling code using masking codes.

ART

In the mobile communication system with multiple access is used scramblers codes. The European system W-mdcr (W-CDMA), UMTS (USMA - universal mobile telecommunication system) generates many scramblers codes, grouped multiple scramblers codes of a given length. As a way to increase bandwidth is to use scramblers codes in the system mdcr, in addition to the sharing base station uses orthogonal codes to a variety of groups scramblers codes for channel separation. That is, when a group of scramblers codes used all orthogonal codes for channel separation, the mobile communication system to increase the number of available communication lines can use the second group scramblers codes. In the mobile communication system of USMA as scramblers codes used reference ("gold") a sequence of length 218-1 in order to have many scramblers codes (one primary scramblase code and many secondary scramblers codes in the same base station, formed by many groups scramblers codes. The reference sequence of length 218-1 includes a group of the 218-1 single reference codes. Reference SUP>-1 is divided into 38400 elements and repeatedly used for scrambling.

Each base station in mobile communication systems, USMA has a unique scramblase code, called "primary scramblers code", which is used to enable the terminal to distinguish each base station from other base stations in the system. Also each unique scramblase code used for expansion (scrambling) of the signals of the channels downlink (from base station to mobile unit) for each base station, called here "the primary scramblers code", and one of the groups scramblers codes used for channel expansion data downlink in the case when there are no orthogonal codes that use the primary scramblase code, called the "secondary scramblers code. The base station uses its unique primary scramblers codes for extensions (scrambling) signals the common control channel transmitted by each mobile station using the corresponding orthogonal code, to extend (scrambling) of the signals of the channels of data transmitted to the mobile station, nakadashi signals of the data channels to separate channels downlink.

The base station has its own unique primary scramblers codes to the mobile station could distinguish this base station from the neighbor. Namely, the number of primary scramblers codes should be large enough, for example, equal to 512, so that the mobile station is not able to simultaneously detect signals of base stations that share the same primary scramblers codes. Thus, separate neighboring base stations use different primary scramblers codes from among the 512 primary scramblers codes. When there are no more orthogonal code with the primary scramblers code allocated to separate channels, separate the base station uses the secondary scramblase code, choose from its many secondary groups scramblers codes corresponding to the used primary scramblers codes.

An example of using multiple scramblers codes is a descending line communication system USMA. It should be noted that for purposes of illustration, the terms "scramblase code, reference code, and a "reference sequence" are used interchangeably to indicate the same code as scrambl the zi in the mobile communication system of USMA.

Please refer to Fig.1, which after administration of specialized physical control channel, SFCU and dedicated physical data channels SVCD, . .. and N, in which the pre-run channel coding and moving, demultiplexes 100-104 (the number of which corresponds to the number of physical channels N plus one for SFCU) share a dedicated physical control channel, SFCU and dedicated physical data channels SVCD,..., and N on the I (inphase) and Q (quadrature) channels. The I and Q channels output separately from the demultiplexer 101, served in the multipliers 110 and 111, respectively. The multipliers 110 and 111 multiply the I and Q channels for orthogonal code 1 for the separation channels, respectively, and send the output to a scrambler 120. Similarly, the I and Q channels output separately from demultiplexes 102-104, are subjected to the same operation that was described above, and served in N scrambler with 124 and 128, respectively. Then the generator 100 groups scramblers codes generates secondary scramblers codes corresponding to the scrambler 120, 124 to 128, and outputs them to the corresponding scrambler. Here the scrambler 120, 124 to 128 multiply the output signals of the respective multipliers in the Asti scrambled signals in the adder 130, and imaginary parts of scrambled signals to the adder 135. The adder 130 adds the real part of a scrambled signal from the scrambler 120, 124 to 128 at that time, as the adder 135 adds their imaginary parts.

In Fig. 2 presents a block diagram of the generator 100 groups scramblers codes shown in Fig.1, which simultaneously generates multiple groups scramblers codes. Although for common control channels and data channels should be used only primary scramblers codes, to increase the number of available communication lines instead of primary scramblers codes can be used secondary scramblers codes. For example, if the base station And uses the primary scramblase code In the available orthogonal codes C-H, and different channels have been assigned to all the orthogonal codes C-H, then there is no longer orthogonal codes that can be assigned new channels, if the base station a wants to communicate the new terminal. In this case, instead of using the primary scrambling code And for new channels can be used secondary scramblase code Z instead of the primary scrambling code And then the new channels can be assigned on scramblase code Z. Thus, new channels can be distinguished from the original channels that are used orthogonal codes C-H, since the new channels instead of a primary code And use secondary scramblase code Z. Therefore, the base station must have the ability to generate many groups scramblers codes.

Please refer to Fig. 2, where the standard generator 100 groups scramblers code contains many generators 201 of the reference sequences and the set of blocks 203 delay corresponding to the generators 210 reference sequences. Received from the upper level control information about scramblers codes for multiple channels, generators 201 reference sequences generate scramblers codes, i.e. codes of the reference sequence, based on the control information and issue created scramblers codes to provide a component of the first channel. Blocks 203 delay provide delay scramblers code component of the first channel on the specified number of items and generate scramblers codes with a time delay, with the component of the Q-channel.

In Fig.3 presents a diagram showing the structure of the receiver of the descending line is to scramble the signals of the common control channels downlink, which were scrambled with the primary scramblers codes. At the same time for data channels downlink receiver should also descrambling signal scrambled using secondary scrambling code when the data channel downlink uses the secondary scramblase code. Thus, the receiver must have the ability to generate many scramblers codes.

Please refer to Fig.3, in which after receiving signals from the transmitter shown in Fig.1 and 2, the components I and Q channels of the received signals are in descrambler 310 and 315, respectively. The generator 300 groups scramblers codes simultaneously generates scramblers codes according to the appropriate channels and displays them in descrambler 310 and 315. Then descrambler 310 and 315 multiply the received signal I+jQ on paired values scramblers codes taken from the generator 300 groups scramblers codes for diskriminirovaniya received signals, and then derive the components I and Q channels descrambling signals to corresponding multipliers 320, 322, 324, and 326. Here, the orthogonal codes assigned to the respective channels are compressed multipliers 320, 322, 324 and 326 and displayed on sooo.

In Fig.4 presents a block diagram of the generator 300 groups scramblers codes shown in Fig.3, which simultaneously generates multiple groups scramblers codes. Although the generator 300 groups scramblers codes must actually use the primary scramblers codes for common control channels, it can also be used and secondary scramblers codes for channels used depending on the user, for example, the data channels in the absence of available orthogonal codes. Therefore, a mobile station must be able to generate many groups scramblers codes.

Please refer to Fig.4, in which the generator 300 groups scramblers codes receiver contains many generators 401 reference sequences and a lot of blocks 403 delay corresponding to the generators 401 reference sequences. Taking from the top level management information about scramblers codes for multiple channels, generators 401 reference sequences generate codes reference sequence in accordance with control information and output the created codes reference sequences, providing a component of the I channel the number of elements, creating codes reference sequence components of the Q channel.

In Fig. 5 presents a diagram showing the structure of the generators of the reference sequences is shown in Fig.2 and 4.

Please refer to Fig. 5, where the reference sequence is usually generated by a binary summation of two different m-sequences. Shift register, which generates the upper m-sequence is implemented using a generating polynomial, defined as f(x)= x18+x7+1, and the shift register, generating lower m-sequence is implemented using a generating polynomial, defined as f(x)= x18+x10+x7+x5+1.

In the existing standard technical conditions of USMA there is no description numbering scramblers codes and its generation. Thus, under standard technical conditions of USMA for receiver and transmitter require many of the above generators scramblers codes to generate many scramblers codes and, therefore, there are different generators for individual scramblers codes, which leads to complication of the hardware. In addition, when using the in € fashion split scramblers codes on primary and secondary scramblers codes and also depend on the numbering method scramblers codes.

THE INVENTION

Therefore, the present invention is a device and method of generating scramblers codes combined into blocks of a given length, using masking capabilities, resulting in minimizing the complexity of the hardware.

Another objective of the present invention is to provide a device and method of generating scramblers codes, including primary scramblase code and the corresponding secondary scramblers codes to be used instead of the primary scrambling code, to increase the number of available communication lines. Scramblers codes generated by the use of masking capabilities.

Another object of the present invention is to provide a device and method of generating primary scrambling code and relevant secondary scramblers codes. In one embodiment of the present invention for generating a first m-sequence is used, the first shift register and for generating a second m-sequence is used, the second shift register. The first m-sequence summeru the participating secondary scramblers code bits of the first shift register are entered in the N masking parts, which use the masking function for cyclic-shifting the first m-sequence. The output signals of each of the mask pieces added to the second m-sequence to generate N secondary scramblers codes.

Another object of the present invention is to provide a numbering scheme scramblers codes for the simplified generation scramblers codes using one generator scramblers codes.

To solve the above problems the present invention proposes a method of generating one primary scrambling code assigned to the base station and multiple secondary scramblers codes using two generators of m-sequences, each of which has a set of series-connected shift registers, namely, that generate a first m-sequence generator of the first m-sequence having a given generating polynomial, and the second m-sequence generator of the second m-sequence having a given generating polynomial different from the generating polynomial of the first m-sequence, summarize the output signal generator of the first m-sequence and the output signal of the primary purpose scrambling code take all the register values of the first m-sequence, multiply the values of the registers of the first m-sequence on the mask value, which determines the secondary scramblase code, summarize the multiplied values at each clock signal and generate the i-th secondary scramblase code by summing the total value with the output signal generator of the second m-sequence.

According to another aspect of the present invention a device for generating multiple scramblers codes in a mobile communication system mdcr, which generates one of the primary scramblase code assigned to the base station, and many secondary scramblers codes containing the generator first m-sequence with multiple series-connected shift registers for generating a first m-sequence generator of the second m-sequence with multiple series-connected shift registers for generating a second m-sequence, a first adder for summing the first and second m-sequence to generate primary scrambling code at least one of a masking section for receiving each of the values (ai), which determines the secondary scramblase code, by shifting the first m-sequence and summing the multiplied values (aix ki), the summation of the second m-sequence with the total values for the generation of secondary scrambling code. According to another aspect of the present invention a device for generating scramblers codes for transmitter downlink in a mobile communication system, USMA, which uses one primary scramblase code to separate base stations and many secondary scramblers codes for channel separation, comprising a generator of the first m-sequence to generate a first m-sequence generator of the second m-sequence to generate a second m-sequence, a first adder for summing the first and second m-sequence to generate primary scrambling code, lots of masking sections, each section of the first masking sections intended for shifting the first m-sequence and the set of second adders, each of the second number of adders is intended to summarize one of the shifted first m-posledovatelnostei codes.

BRIEF DESCRIPTION OF DRAWINGS

The above and other objectives, features and advantages of the present invention will become more apparent from the subsequent detailed description together with the drawings, in which:

Fig. 1 is a diagram showing the structure of a known transmitter downlink in a conventional mobile communication system, USMA;

Fig.2 is a block diagram of a known oscillator groups scramblers codes shown in Fig.1;

Fig. 3 is a block diagram showing the structure of a known receiver downlink in a conventional mobile communication system, USMA;

Fig. 4 is a block diagram of a known oscillator groups scramblers codes shown in Fig.3;

Fig. 5 is a detailed diagram showing the structure of a known generator groups scramblers reference groups in a conventional mobile communication system, USMA;

Fig.6 is a diagram showing the structure scrambling code according to the first embodiment of the present invention;

Fig. 7 is a detailed diagram showing the structure of the generator groups scramblers codes for transmitter downlink in a mobile communication system, USMA according to the first embodiment of the present invention;

Fig. 8 is a detailed diagram showing the structure of the according to the first embodiment of the present invention;

Fig.9 is a diagram showing the structure scrambling code according to the second variant of the present invention;

Fig.10 is a detailed diagram showing the structure of the generator groups scramblers codes for transmitter downlink in a mobile communication system, USMA according to the second variant of the present invention;

Fig. 11 is a detailed diagram showing the structure of the generator groups scramblers codes for receiver downlink in a mobile communication system, USMA according to the second variant of the present invention.

DETAILED DESCRIPTION THE PREFERRED OPTION OF CARRYING OUT THE INVENTION

Below with reference to drawings, describes a preferred implementation of the present invention. In the following description, well-known functions and structures are not described in detail so as not to overload the invention with unnecessary detail.

Used here as scrambling code reference code is generated by the binary summation of two different m-sequences. Suppose that two m-sequences of length L each, are defined as ml(t) and m2(t), respectively, and the set of reference codes can contain L different reference placenta is R>< / BR>
where t is the time variable, and - the value of the shift. As can be seen from equation 1, the set of reference codes is the set of all sequences that contain the sum of the m-sequence m1(t), cyclically shifted again, and the m-sequence m2(t). Thus, according to the objectives of the present invention the sum of the m-sequence m1(t), cyclically shifted again, and the m-sequence m2(t) will be denoted by like reference code g. That is, g(t) = m1(t+)+m2(t). If the period of the reference code is equal to 218-1, then a separate m-sequence forming a reference code, also have a period equal to 218-1. Thus, the m-sequence m1(t) can be cyclically shifted a maximum of 218-1 times, and the number of elements in the set of reference codes is 218-1, what is the maximum value of the cyclic shift.

The set of reference codes used in embodiments of the present invention, contains 218-1 reference codes in the form of elements, each of which contains m-sequence m1(t) with generating polynomial defined as f(x)=18+x7+1, and m-sequence m2(t) with parodius inost m1(t), cyclically shifted again, can be obtained by applying masking capabilities to the values of the memory shift register that generates the original m-sequence.

Variants of the present invention offer generator for generating multiple reference sequences using masking capabilities and how effective separation of the set of reference sequences in the set of primary scramblers codes and a set of secondary scramblers codes to reduce the number of masking capabilities stored in memory.

THE FIRST OPTION

In Fig. 6 is a diagram showing the structure of primary and secondary scramblers codes according to the first embodiment of the present invention.

First, when a reference sequence selected from the reference sequences of length 218-1, the first 38400 elements are used as the primary scrambling code, the second 38400 elements as the first secondary scrambling code corresponding to this primary scramblers code, third 38400 elements as the second secondary scrambling code corresponding to a given PE is, sootvetstvuyuschego this primary scramblers code, the fifth 38400 elements as the fourth secondary scrambling code corresponding to this primary scramblers code, sixth 38400 elements as the fifth secondary scrambling code corresponding to this primary scramblers code. Here, when using 512 primary scramblers codes, there are five groups of secondary scramblers codes corresponding to the 512 primary scramblers codes. In particular, if 218-1 (length scramblers codes) divided by 38400, you get six groups scramblers codes. Of the six groups scramblers codes first group scramblers codes is used as the primary scramblers codes, and the remaining five groups scramblers codes are used as secondary scramblers codes. In this structure, if the cell cell (base station) uses its own primary scramblase code and secondary scramblers codes, selected from her own group of secondary scramblers codes, then the selected secondary scramblers codes that belong to the group of secondary scramblers codes corresponding to the primary is always not available orthogonal codes with the given primary scramblers code.

As shown in Fig.6, as soon as the selected primary scramblase code, secondary scramblers codes corresponding primary scramblers code, are also part of the reference code, which also contains this primary scramblase code. Here the secondary scramblers codes are generated by applying the masking capabilities of the primary scramblers codes. This method is adapted to the generator groups scramblers codes for the transmitter shown in Fig.7, which simultaneously generates one primary scramblase code and many secondary scramblers codes.

Please refer to Fig.7, in which the generator 701 group scramblers contains codes generator 750 first m-sequence containing the upper memory 700 shift registers (hereinafter referred to as "the first memory shift registers") (registers 0 to 17) and the adder 730, generator 760 second m-sequence, containing the lower memory 705 shift registers (hereinafter referred to as "second memory shift registers") (registers 0 to 17) and the adder 735, many masking sections 710 through 712 and 714 through 716, many adders with 744 742 on and 740, and many blocks of the delay 722 on 724 and 720. The first 705 shift registers stores the preset initial value registers "babout". The values stored in each of registers in the memory 700 and the memory 705 may change during each period of the input clock signal (not shown). In the memory 700 and 705 registers remembered the 18-bit (or symbol) of the binary value "and1' and b1" accordingly (i=0 to s-1, where C is the total number of registers in the memory 700 registers and memory registers 705).

Generator 750 first m-sequence to generate a first m-sequence using the memory 700 registers and the adder 730, which is a binary adder, summing the binary values from registers 0 through 7 memory 700 registers and outputs the sum to the register 17. Register 0 memory 700 registers sequentially outputs binary values, which form the first m-sequence during each period of the input clock signal. Masking sections 710 through 712 remember the code values of the mask (k1i and kNi) for the generation of cyclic shifts of the first m-sequence by a specified number of elements. Cyclic shifts are achieved by multiplying the code values of a mask value registers andi" the first memory 700 shift registers, as shown in the following equation: (kS="ptx2">

Generator 760 second m-sequence to generate a second m-sequence using the memory 705 registers and the adder 735, which is a binary adder, summing the binary values from registers 0, 5, 7 and 10 memory registers 705 and outputs the sum to the register 17. Register 0 memory 705 registers sequentially outputs binary values, which form the second m-sequence, during each period of the input clock signal. The masking section 714 through 716 remember each of the code values of the mask (sli SNi) for the generation of cyclic shifts of the second m-sequence for a specified number of elements. Cyclic shifts is provided by multiplying the code values of a mask value registers "bi" the second memory 705 shift registers. The resulting values are fed into the adders with 742 on 744, respectively. Each of the generators of m-sequences 750 and 760 generates the m-sequence according to the corresponding generating polynomial.

The adder 740 totals value 0's register (i.e. the last digit) first 700 and 705 second memory shift registers for generating scrambling code, which becomes the primary Kremlinologists to the first memory 700 shift registers, with one discharge generated from a mask parts 714 through 716 corresponding to the masking sections with 710 through 712. In other words, the output signal of the first masking section 710 of the first group is added to the output signal of the first masking section 714 of the second group and so on, until the summation of the output signal of the N-th masking section 712 of the first group with the output signal of the N-th masking section 716 of the second group.

Thus, each masking section 710 through 712 in the first group has a corresponding masking section among the masking sections 714 through 716 of the second group. Output signals from the respective masking sections are added together in adders with 742 on 744, respectively. That is, a separate masking sections have mating part on a one-to-one basis with respect to the first and second memory 700 and 705 shift registers. For example, the first masking section 710 of the first memory 700 shift registers corresponds to the first mask section 714 of the second memory 705 shift registers, N-th masking section 712 corresponds to the N-th masking section 716, etc. Between two adjacent mask sections (that is, the first masking sections 710 and Wii sections, in response to the input clock signal. Here, the output signals of the adders with 742 on 744 contain component (I channel.

Blocks delay 722 on 724 and 720 delay signals of the first channel on the specified number of elements to generate respective signals Q channel.

The following describes the operation of the present invention with the structure described above.

As soon as in the first and second memory 700 and 705 shift registers, each of which has 18 registers for circular shift register values "AI" or "bi", filed the initial value of the primary scrambling code, in the adder 740 served 0-th register values for the first and second memory 700 and 705 shift registers, and the masking sections 710 through 712 (from the first to the N-th) are 18 values of registers and1" the first memory 700 shift registers to generate a cyclically shifted sequence of the first shift registers. Meanwhile, in the mask section from the first to the N-th (714 through 716) served 18 values of registers "b1" the second memory 705 shift registers to generate a cyclically shifted sequence of the first shift registers. Then the first mask section 710 masks the input value is s) using the masking function of k1i (that is, (k1iai)) and outputs the masked values to the adder 744 for generating the first secondary scrambling code. Masking occurs simultaneously in each masking section 710-712. N-I a masking section 712 masks the input values of the first (upper) shift registers using masking kNi (that is, (kNiai)) and outputs the masked values to the adder 742 for generating the N-th secondary scrambling code. N-I a masking section 716 masks the input values from the second (lower) shift registers using masking Ni (that is, (sNiai)) and outputs the masked values to the adder 744 to generate the N-th secondary scrambling code. The first masking section 714 masks the input values from the memory 705 registers using masking S1i (that is, (s1iai)), and outputs the resultant value to the adder 742 for generating the first secondary scrambling code. Each of the masking sections 710-712 masks the input values from the first memory 700 shift registers and outputs the masked value in the corresponding adders 742-744. Then the adder 740 summarizes the crystals were immediately subjected to the delay unit 720 delay. The adder 744 summarizes the output bits from the N-x mask sections 712 through 716 to generate signals of the I channel, which immediately serves to block 724 delay. Block 722 delay delays the signal of channel I, issued by the adder 744, a specified number of elements to generate scramblers signals of the Q-channel. The adder 742 summarizes the output bits of the first masking sections 710 and 714 to generate signals of the I channel. These signals I-channel immediately delayed by the specified number of elements in block 722 delay. Then, in the adder 730 summarizes the values of the 0-th and 7-th register of the first memory 700 shift registers, and the total value is input to the seventeenth register, which leads to the shift left value to the right by one, and in the leftmost register restarts the output value of the adder 730. Values 0-th, fifth, seventh and tenth registers of the second memory 705 shift registers are summed in the adder 735, the total value is entered in the seventeenth register, which leads to the shift left value to the right by one, and in the leftmost register (that is, the seventeenth register) loads the output value of the adder 735. This procedure is repeated to generate many of cremolino is a, which provides simultaneous generation of one primary scrambling code and one secondary scrambling code. The receiver must use scramblers codes only for the shared control channel and the assigned data channel and, therefore, will need one primary scramblase code and one secondary scramblase code.

Please refer to Fig.8, which, once in the first memory 840 shift registers, with 18 of the upper shift register and the second memory 845 shift registers 18 of the lower shift registers served the initial value for the primary scrambling code, in the adder 810 served 0-s register values for the first and second memory 840 and 845 shift registers. The output signal of the adder 810 is the primary scramblers code. 18 values of registers andi" the first memory 840 shift registers are served in the masking section 820. Meanwhile, in the masking section 825 served 18 values of registers "bi" the second memory 845 shift registers. Then the mask section masks 820 input values from the first shift register by using the mask function k.i(that is, (kiai)) and outputs the masked values in Sumeria from the second (lower) shift register using masking Si(that is, (siai)) and outputs the masked values to the adder 815 to generate secondary scrambling code. Then the adder 810 adds the output bits from the 0-th register of the first and second memory 800 and 805 shift registers to generate signals primary scramblers codes I-channel. These signals are the primary scramblers codes I-channel immediately delayed by the specified number of elements in block 830 delay to generate signals primary scramblers codes Q-channel. The adder 815 summarizes the output bits of the mask sections 820 and 825 to generate signals primary scramblers codes I-channel, which are immediately subjected to the delay in block 835 delay. Then, in the adder 800 summarizes the values of the 0-th and 7-th registers of the first shift register, and the total value is displayed in the seventeenth register, which leads to the shift left value to the right by one. Values 0-th, fifth, seventh and tenth registers from the second shift register are summed in the adder 805, and the total value is issued in the seventeenth register, which leads to the shift left value to the right by one. This procedure is repeated to generate many scramblers codes.

THE SECOND OPTION

In Fig. 9 is a diagram showing the structure of primary and secondary scramblers codes according to the second variant of the present invention. At that time, as in the first embodiment to generate scramblers codes masking is performed for the m-sequence mi(t), and m-sequence m2(t), the second option is to generate scramblers sequences includes a cyclic shift only m-sequence m2(t), not m-sequences mi(t). To have this option is well described by equation 1.

Please refer to Fig. 9, where, when M secondary with the appropriate codes are used first, (M+2)-th, (2M+3)-th, . .., (K-1)*M+K)-th,..., and (M+512)-th reference codes. Secondary scramblers codes corresponding to ((K-1)*M+K)-th reference code is used as the (J) th primary scrambling code consists of M reference codes, that is, ((K-1) *M+(K+1)), ((K-1)*M+(K+)),..., (K*M+K)-th reference codes. Here, when using 512 primary scramblers codes each of the sets of secondary scramblers codes corresponding to the 512 primary scramblers codes, consists of M secondary scramblers codes. In this structure, if the cell the cell uses one of the primary scramblers codes, then the secondary scramblers codes that belong to the group of secondary scramblers codes corresponding to the primary scramblers code will be used when it is necessary to use a secondary scramblers codes.

As shown in Fig.9, once the selected primary scramblase code generated secondary scramblers codes that are appropriate for primary scramblers code, by adding the cyclically shifted first m-sequence and the second m-sequence. Here the secondary scramblers codes are generated by applying functions mastclimbers codes for transmitter, it is shown in Fig. 10, which simultaneously generates one primary scramblase code and many secondary scramblers codes.

Please refer to Fig. 10, in which the generator 1050 first m-sequence contains the first memory 1040 shift registers (registers 0 through 17) and the adder 1010 for summing the output signals of registers 0 through 7.

Generator 1060 of the second m-sequence contains the second memory 1045 registers (registers 0 through 17) and the adder 1015 for summing the output signals of registers 0, 5, 7 and 10. Generator scramblers codes shown in Fig.10, contains two generators 1050 and 1060 m-sequences, lots of masking sections 1000 through 1005, many adders with 1032 at 1030 and 1034 and multiple delays 1022, 1024 and 1020. The first memory 1040 shift registers stores the preset initial value of register "aabout"and the second memory 1045 shift registers stores the preset initial value registers "bo". The memory 1040 and 1045 shift registers can remember 18 binary values (bits or symbols) "1' and bi" (0 i 17). Two generator 1050 and 1060 m-sequences to generate the digits of the corresponding output sequences coz the ante of the present invention uses the reference code length 38400 symbols to generate scramblers codes.

Thus, the memory 1040 and 1045 shift registers can be set to an initial value when each memory 1040 and 1045 register produces a sequence having a length of 38400 characters.

Generator 1050 first m-sequence to generate a first m-sequence using the memory 1040 registers and the adder 1010, which is a binary adder, summing the binary values from registers 0 through 7 memory 1040 registers, and outputs the sum to the register 17. Register 0 memory 1040 registers sequentially generates binary values, which form the first m-sequence during each period of the input clock

signal. Masking sections 1000 through 1005 remember the meaning of the code mask (with k1i no kNi) for the generation of cyclic shifts of the first m-sequence by a specified number of elements. Cyclic shifts are obtained by multiplying the values of the code mask register value "ai" the first memory 1040 shift registers, which is expressed by the following equation: (kLiai). The resulting values are fed to the adders with 1032 in 1034, respectively.

In preferred embodiments of the present invention, each of the code values of the mask (with the th cyclically shifted from 1 to N times. Thus, each of the code values of the mask is determined by the required number of cyclic shifts.

The adder 1030 sums the values 0's registers of the first and second memory 1040 and 1045 shift registers for generating scrambling code, which becomes the primary scramblers code. Each of the adders with 1032 on 1034 adds one digit generated by the masking sections 1000 through 1005, with one discharge generated by the second memory 1045 shift registers, respectively, to generate signals scramblers codes I-channels. Here the output signal from adder 1030 is used as the primary scrambling code, and scramblers codes issued by the adders with 1032 in 1034, can be used as a secondary scramblers codes that match the primary scramblers code.

Below is an example of possible values of the mask (k1ifor kNi): k1i= (000000000000000010), k2i(000000000000000100), k3i=(000000000000001000),... . By controlling the values of the mask, it is possible to generate other primary and secondary codes. The following example shows how you can receive the necessary code m is Olya for m-sequence (that is, xn/f(x)) and take the remainder of the division to create a code mask. For example, if you want to create a code mask, performing cyclic shifts 31 times, it is necessary to take x31, divide it by the generating polynomial f(x)=x18+ x7+ 1 and find the remainder, which is not further divided. The final balance will be x13+ x9+ x2that can be seen from the following expression:

x31=x13x18=x13(x7+1)=x20+x13=x2x18+x13=x2(x7+1)+x13=x13+x9+x2< / BR>
The binary sequence corresponding to x13+x9+x2will be 000010001000000100 that is the code of the mask required for the cyclic shift of the m-sequence 31 times.

Blocks delay 1022, 1024 and 1020 performs the delay signals of the I channel by the specified number of elements to generate signals scramblers codes Q-channel.

As described above, in the second embodiment of the present invention are generated group scramblers codes shown in Fig.9, using only one generator reference code, the masking section between 1000 and 1005 and the adders with 1022 at 1034.

The following describes the operation of the crust the village of the Whigs registers, each of which has 18 registers, served the initial value for the primary scrambling code value 0's register of the first and second memory 1040 and 1045 shift registers are fed into the adder 1030, and 18 values of registers ai" the first memory 1040 shift registers are served in the masking section 1000 (first) 1005 (N-th) in order to generate a cyclically shifted sequence (1 through N) of the first m-sequence. Then the first mask section 1000 masks the input value (aifrom the first memory 1040 (upper) shift registers using masks k1ifor generating the first secondary scramblers codes (that is, (k1iai)) and outputs the masked value (aiin the adder 1032. N-th masking section 1005 masks the input value (aifrom the first memory 1040 (upper) shift registers using masks kNito generate the N-th secondary scramblers codes (that is, (kNiai)) and outputs the masked values to the adder 1034. At the same time, the adder 1030 summarizes the output bits from the 0-th register of the first and second memory 1040 and 1045 shift registers. The generated output signals immediately zaderzhala register of the second memory 1045 shift registers. Output signals immediately served to block 1022 delay. Then, the values of the 0-th and seventh memory registers 1040 shift registers are summed in the adder 1010, and the adder 1010 outputs the sum in the seventeenth register, which leads to the shift left value to the right by one for re-download in the leftmost register (that is, the seventeenth register) output value of the adder 1010. Values 0-th, fifth, seventh and tenth registers memory 1045 shift registers are summed in the adder 1015, and the adder takes the sum of the seventeenth memory register 1045 registers, which leads to the shift left value to the right by one for download in the leftmost register (that is, the seventeenth register) output value of the adder 1015. This procedure is repeated to generate many scramblers codes.

In Fig.11 presents a diagram showing the generator scramblers codes for receiver, which is designed for generating one primary scrambling code and one secondary scrambling code. The options shown in Fig.10 and 11, can be used either in the transmitter or in the receiver.

The receiver according to the second variant of the present sobrero one masking section 1100.

Please refer to Fig. 11, which, as soon as the first memory 1140 shift registers having 18 registers, and the second memory 1145 shift registers 18 registers filed the initial value for the primary scrambling code value 0's register of the first and second memory 1140 and 1145 shift registers are fed into the adder 1120. 18 values of registers andithe first memory 1140 shift registers are served in the masking section 1100 to generate a cyclically shifted m-sequence. Then the masking section 1100 masks the input values (aifrom memory 1140 registers with values mask kifor generating the first secondary scramblers codes (that is, (kiai)) and outputs the masked values to the adder 1125. The adder 1120 summarizes the output bits from the 0-th register of the first and second memory 1140 and 1145 shift registers. The output signals of the adder 1120 immediately delayed in block 1130 delay. Meanwhile, the adder 1125 summarizes the output bits from the masking section 1100 and the 0-th shift register of the second memory 1145 shift registers and immediately displays the amount in block 1135 delay. Then the 0-th and seventh registers of the first memory 1140 shift registers are summed is here seventeenth register) will be downloaded again the output value of the adder 1110. Values 0-th, fifth, seventh and tenth registers of the second memory 1145 shift registers are summed in the adder 1115, shifting left value to the right by one unit and re-downloading the leftmost register output value of the adder 1115. The controller (not shown) may control the values of the mask when the receiver must generate other scramblers codes.

The generator scramblers codes on the second version of the required values of the mask stored in the mask section, in order to generate secondary scramblase code, that is, to generate N scramblers codes used N values of the mask. Accordingly, the structure of primary and secondary scramblers codes shown in Fig.9, provides the opportunity to implement the generator scramblers codes for the structure of the transceiver shown in Fig.10 and 11, which additionally contains only N functions mask with relatively low complexity hardware to generate many scramblers codes.

Although the invention has been shown and described with reference to specific preferred implementation, specialists in the art it is obvious that it can be made to the Les of the invention.

1. The method of generating primary scrambling code and N secondary scramblers codes associated with the primary scramblers code for mobile telecommunication, namely, that (a) generate a first m-sequence from the first memory shift registers having a set of registers with values a1where i = 0 to s-1, where C = the total number of registers, (b) generate a second m-sequence from the second memory shift registers having a set of registers with values of biwhere i = 0 to s-1, where C = the total number of registers, (c) summarize the first m-sequence with the second m-sequence to generate primary scrambling code, (d) masking aiwhere i= 0 to s-1, to obtain the L-th secondary sequence, which is the first m-sequence cyclically shifted L times, where 1 L N, and (e) summarize the L-th secondary sequence with the second m-sequence to generate the L-th secondary scrambling code.

2. The method according to p. 1, characterized in that the first and second m-sequence generated on the basis of the first generating polynomial and the second generating polynomial, respectively.

3. The method according to p. 1, ).

4. The method according to p. 2, characterized in that it further cyclically shift the first memory shift registers.

5. The method according to p. 4, characterized in that when the cyclic shift of the first memory shift registers summarize the specified bits of the first memory shift registers based on the first generating polynomial of the first m-sequence, shift right the first memory shift register and insert the value equal to the sum of the specified bits in ac-1.

6. The method according to p. 5, characterized in that a0fold with a7for the education of the next ac-1.

7. The method according to p. 2, characterized in that it further cyclically shift the second memory shift registers.

8. The method according to p. 7, wherein when the cyclic shift of the second memory shift registers summarize the specified bits of the second memory shift registers based on the second generating polynomial of the second m-sequence, move to the right the second memory shift register and insert the value equal to the sum set of bits, bc-1.

9. The method according to p. 8, characterized in that b0stack with b5b7and b10for the education of the next bsee the code to create the components of the Q-channel for the L-th secondary scrambling code and nezadelannyh L-th secondary scramblase code is a component of the I-channel for the L-th secondary scrambling code.

11. The method of generating primary scrambling code and N secondary scramblers codes associated with this primary scramblers code for mobile telecommunication, namely, that (a) generate a first m-sequence from the first memory shift registers having a set of registers with values aiwhere i = 0 to s-1, where C = the total number of registers; (b) generate a second m-sequence from the second memory shift registers having a set of registers with values of biwhere i = 0 to s-1, where C = the total number of registers, (C) summarize the first m-sequence with the second m-sequence to generate primary scrambling code, (d) enter aiwhere i = 0 to s-1 in the mask section, (e) masking aiwhere i = 0 to s-1, each of the masking sections to create a secondary sequence, (f) summarize each of the secondary sequences from the second m-sequence to generate N secondary scramblers codes, and L-I secondary sequence represents the first m-Puu and the second m-sequence generated on the basis of the first generating polynomial and the second generating polynomial, respectively.

13. The method according to p. 11, characterized in that the masking operation (e) is expressed by the following equation:

(kLiai).

14. The method according to p. 12, characterized in that it further cyclically shift the first memory shift registers.

15. The method according to p. 14, wherein when the cyclic shift of the first memory shift registers summarize the specified bits of the first memory shift registers based on the first generating polynomial of the first m-sequence, shift right the first memory shift register and insert the value equal to the sum of the specified bits in ac-1.

16. The method according to p. 15, characterized in that a0summarize with a7for the education of the next ac-1.

17. The method according to p. 12, characterized in that it further cyclically shift the second memory shift registers.

18. The method according to p. 17, wherein when the cyclic shift of the second memory shift registers summarize the specified bits of the second memory shift registers based on the second generating polynomial of the second m-sequence, move to the right the second memory shift register and insert the value equal to the sum of >b7and b10for the education of the next bc-1.

20. The method according to p. 11, characterized in that it further delaying each of the secondary scramblers codes to create the components of the Q-channel for the secondary scramblers codes, and nezagarionnyje secondary scramblers codes are components of the I-channel for the secondary scramblers codes.

21. The device for generating primary scrambling code and secondary scramblers codes associated with the primary scramblers code for mobile telecommunication containing the first memory shift registers for generating a first m-sequence, and the first memory shift registers has a set of registers with values aiwhere i = 0 to s-1, where C= the total number of registers, the second memory shift registers for generating a second m-sequence, and the second memory shift registers has a set of registers with values of biwhere i = 0 to s-1, where C = the total number of registers, the primary adder for summing the first m-sequence with the second m-sequence to generate primary scrambling code, lots of masking sections for maskirovka summation secondary sequences from the second m-sequence to generate secondary scramblers codes each of the masking sections cyclically shifts the first m-sequence by using the mask.

22. The device according to p. 21, characterized in that the first and second m-sequence is generated based on the first generating polynomial and the second generating polynomial, respectively.

23. The device according to p. 21, characterized in that the mask in each of the masking sections is expressed by the following equation:

(kLiai).

24. The device according to p. 22, characterized in that it further comprises a first adder registers to sum the digits of the first memory shift registers, and the first memory shift registers cyclically shifted by summing the set of bits of the first memory shift registers in the first adder registers based on the first generating polynomial of the first m-sequence, right-shift of the first memory shift registers and paste the output signal of the first adder registers in ac-1.

25. The device according to p. 24, characterized in that a0added to a7for the education of the next ac-1.

26. The device according to p. 24, characterized in that it further comprises a second adder registerlink shifted by summing the set of bits of the second memory shift registers in the second adder register based on the second generating polynomial of the second m-sequence, right-shift of the second memory shift registers and paste the output signal of the second adder registers in ac-1.

27. The device under item 26, characterized in that b0stack with b5b7and b10for the education of the next bc-1.

28. The device according to p. 21, characterized in that it additionally contains many blocks of delay for delaying the output signals of the primary adder and secondary adders to create a component of the Q-channel of the primary scrambling code and secondary scramblers codes.

29. The device for generating primary scrambling code and secondary scrambling code associated with the primary scramblers code for mobile telecommunication containing the first memory shift registers for generating a first m-sequence, and the first memory shift registers has a set of registers with values aiwhere i = 0 to s-1, where C = the total number of registers, the second memory shift registers for generating a second m-sequence, and the second memory shift registers has a set of registers with values of biwhere i = 0 to s-1, where C = the total number of registers, primary the aqueous scrambling code a masking section for masking aiwhere i = 0 to s-1, to create a secondary sequence, the secondary adder for summing the secondary sequence with the second m-sequence to generate secondary scrambling code, and a masking section cyclically shifts the first m-sequence by using the mask.

30. The device according to p. 29, characterized in that it additionally contains many blocks of delay for delaying the output signals of the primary adder and secondary adder to generate the component of the Q-channel of the primary scrambling code and secondary scrambling code.

 

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