Multi-channel analog-to-digital converter

 

(57) Abstract:

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code. The technical result is to increase speed multi-channel analog-to-digital converters that is achieved by using the optimal logical procedure code selection, taking into account the statistical characteristics of the converted signals, and the settling time voltage output digital to analogue Converter. The device includes N information channels, each of which consists of a block of comparison, triggers, item, element, OR, as well as the six elements And the element is NOT, the pulse generator, trigger the one-shot, subtractive counter, a register, a d / a Converter, a persistent storage device, item, OR. 4 Il., table 1.

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code.

Known multi-channel analog-to-digital Converter (ADC) containing the pulse generator, a control unit, a counter, a digital-to-analogue conversion of the operational storage device, decoder channel numbers, items, OR (and.with. 930656, CL N 03 TO 13/17, BI 19, 1982).

The disadvantage of this device is its complexity is mainly due to the complexity of implementing block preemption and control unit.

The closest in technical essence to the present invention is a multichannel ADC, containing n information channels, each of which contains a block of comparison, the input blocks comparison of combined and connected to the output of the digital to analogue Converter, the second input of each unit of comparison is the corresponding input bus, the outputs of blocks compare connected to respective first inputs of block priority interrupt inputs digital to analogue Converter connected to respective outputs of the pulse counter, a counting input connected to the first output control unit, the pulse generator, the first output of which is connected to the first input of the control unit, the second input is connected to the first output block preemption, the second outputs of which are connected to the corresponding inputs of the Converter unit code in binary, the outputs of which are the first output bus, the one-shot and ale is, the input is connected to the first output block preemption, and exit through the one-shot is connected to the second input of the block preemption, the installation of the meter inlet, the first Manager of the input of the pulse generator and the second output bus, the second and third outputs of the control unit are connected respectively to the third and fourth inputs of the block preemption, the third output control unit is the third output bus, a second output of the pulse generator is connected to the fifth input of the unit preemption, the second control input of the pulse generator is the control bus, the outputs of the pulse counter are the fourth output bus (and.with. The USSR 1520656, CL H 03 M 1/38, b.and. 41, 1989, prototype).

The disadvantage of this device is a low speed, because it does not takes into account statistical characteristics of the signals at the input multi-channel ADC and the time for establishing the voltage at the DAC output. The principle of operation of the ADC is that on the input of the DAC by using a counter sequentially formed all possible codes starting with zero. Due to this, the DAC output is formed by gradually changing the voltage, which simultaneously sravnivats the AI precision ADC) the number of possible combinations grows rapidly (it is equal to 2Nwhere N - bit DAC), which reduces the performance multichannel ADC.

The technical result improved performance multichannel ADC by applying the optimal logical procedure of selection of the output code, taking into account the statistical characteristics of the signal and the temporal characteristics of the DAC (the settling time of the input voltage).

The technical result is achieved in that in a multi-channel ADC, containing n information channels, each of which contains first and second triggers, the first item, the unit of comparison, the first inputs are combined and connected to the output of the digital to analogue Converter (DAC), the second input of each unit of comparison is the corresponding input bus, a pulse generator, one-shot, second, third and seventh elements, And the element is NOT introduced into each information channel of the first element OR the third trigger, the second element OR subtractive counter, a register, a persistent storage device (ROM), each information channel output of the Comparer is connected to the first input of the first element OR the first input of the first flip-flop, a second input connected to the first output of the second tragedian with the second input of the second trigger, the second output of which is connected to the second input of the first element OR the third inputs of the first triggers of all information channels combined and connected to the output of the fourth element And the second inputs of the first elements And all information channels combined and connected to the output of the fifth element And the third inputs of the second triggers all information channels combined and connected to the output of one-shot outputs the first trigger all information channels form the first output device.

The outputs of the first elements OR all data channels connected to the corresponding inputs of the second element And the second outputs of the second triggers all data channels connected to the corresponding inputs of the third element And the first input of the third trigger is a control input of the second input of the third trigger is connected to the output of the second item OR the third input to the first input of the fifth element And the output of the sixth element And the first Manager of the input register and the first Manager of the subtractive input of the counter, the output of the third trigger is the second output device and is connected to the input of one-shot and managing the input of the pulse generator, the first output of which is the output of the pulse generator connected to the first input of the sixth element, And a second input connected to the output of the subtractive counter and a second input of the fourth element, And a third input connected to the output element, the input of which is connected to the output of the second element And the first address input of a permanent mass storage device, the second address inputs of which are connected with inputs of the seventh element And the inputs of the digital-analog Converter and the output register, the first terminals are connected to information inputs of the register, the second output information subtractive inputs of the counter, third outputs are third outputs of the device, the fourth output is connected to a second input of the fifth element And whose output is the fourth output, the output of the one-shot is connected with the second Manager of the input register and the third managing subtractive input of the counter, the output of the seventh element And connected to the first input of the second element OR the second input is connected to the output of the third element And.

A structural scheme of the device differs from the known fact that it introduced an additional trigger, subtractive counter items OR register and constant memory (ROM), which are standard the register - IR, subtractive counter - IE, ROM - RE (Avanesyan, R., Levshin VP of Integrated circuits TTL, TTLS: a Handbook. - M.: Mashinostroenie, 1993, - S. 160, 172, 190, 207). However, despite the fact that the blocks are standard nodes of digital computers, their introduction, as well as the emergence of new functional connections between them and the existing units gives the chance to appear in the device to a new property. Namely, the ADC can reduce the conversion time of the measured value by applying optimal matching code which takes into account the probabilistic characteristics of the measured value, and the temporal characteristics of the digital to analogue Converter (settling time output voltage). The optimal procedure code selection can be made using methods known in theory of automatic control and Troubleshooting (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under. editor I. A. Ushakov. - M. : Radio and communication, 1981. - 280 C.). The optimal procedure can reduce the time spent on the selection code corresponding to an input voltage of each information channel, and, consequently, to increase rapidly and 3 - the first and second triggers; 4 - the first element OR; 5, 6, 7, 8, 9, 10 - elements one through six; 11 - item NOT; 12 - pulse generator; 13 - third trigger; 14 - one-shot; 15 - analog Converter (DACS); 16 - case; 17 - subtractive counter; 18 - permanent memory (ROM); 19 - the seventh element And; 20 - second element OR. The unit of comparison 1, the first and second triggers 2 and 3, the first element OR 4, the first element And 5 constitute an information channel 21.

The unit of comparison 1 is intended for comparing convert the input voltage UIand voltage output DAC 15 - UDAC. If UI>UDACat the output of the Comparer 1 appears a signal corresponding to a logical unit, otherwise a logic zero.

The first 2 and second 3 triggers, the first element OR 4 and the first element And 5 are logic control information channel 21. In the first trigger 2 provides information from the output of the Comparer 1 for admission to the third input of the first flip-flop 2 of the leading edge of the pulse from the output of the fourth element And 8. Recording is possible only in case, if the second trigger 3 is in the zero state, i.e., the level at the first output (inverse) sootvetstvuyuschego trigger 2. The second trigger 3 at the beginning of the operation of the device is set to the zero state. When the conversion of the input analog voltage in the code in this information channel is completed, the second trigger 3 is translated in one state (the rear edge of the pulse from the output of the first element And 5). Zero level from the first (inverted) output of the second trigger 3 translate the first trigger 2 in one state, then this news channel to participate in the further operation of the device will not. When the conversion is completed in all information channels (i.e., all second trigger 3 will be in a single state and their second output will be a logic level one), will trigger the third element And 7, the signal from which the operation will end. The second element, And 6 together with the first elements OR 4 of each information channel is intended for process control code selection. The output of the second element And 6, you receive a level corresponding to a logical unit, when the voltage at the input of all information channels exceeds the voltage output from the DAC 15.

The fourth element And 8 is designed to generate pulse at the third input of the first flip-flop 2 output the appropriate unit of comparison 1. The pulse at the output of the fourth element And 8 is formed by applying to it the first input pulse from the first output of the pulse generator 12 in the presence of a signal of the logic unit at the output of the subtractive counter 17 (the content of the counter 17 is zero) and the presence of a signal of the logic unit output element 11 (if at least one information channel, the level of the input voltage less the voltage coming from the output of the DAC 15).

The fifth element And 9 is designed to generate pulse to the second input of the first element And 5 all information channels. The output signal of the first element And 5 in the second trigger 3 is overwritten by the information from the inverted output of the first trigger 2. Note that this is only possible when the second trigger 3 is in the zero state, since the signal from the first output (inverse) is supplied to the first input of the first element And 5 (i.e. in the case when convert this information channel is not completed). The pulse at the output of the fifth element And is formed with the arrival of the pulse from the output of the sixth element And 10 and in the presence of logical units on the third output of the ROM 18 (convert to any news channel, completed).

The sixth cell battery (included) is the difference of the level of logical units on the output of the subtractive counter 17 (when the content of the subtractive counter 17 will be equal to zero).

The pulse generator 12 is designed to synchronize the operation of the device. He is a two-phase generator of rectangular pulses, and the pulses at its second output is shifted in time relative to the pulses at the first output.

The third trigger 13 is designed for fixing the beginning of the conversion process and its completion. When submitting its first input of a start signal, the third trigger 13 is set in one state and starts the conversion process. Upon arrival of the pulse from the output of the sixth element And 10 and level logical units on the output of the second element OR 20 (the process of converting all of the information channels is completed) third trigger 13 is set in the zero state and the conversion process ends.

The one-shot 14 is designed to generate a pulse at the beginning of the conversion process. When the pulse from its output is supplied to the second control input of the register 16 and the third control input of subtractive counter on which the register 16 is reset, and the subtractive counter 17 is written to the unit. The pulse output of one-shot 14 is also supplied to the third input (the input set to the zero state) of the second trigger 15 is designed to convert a digital code, supplied to its input, the corresponding output level of the analog voltage.

The register 16 is designed to store the current value of the output code. On the trailing edge of the impulse applied to the first control input (input record) register 16, it is written with information from the first outputs of the ROM 18. The second control input of the register 16 is used to reset.

Subtractive counter 17 is designed to generate a time interval corresponding to the time of establishing the voltage at the DAC output 15 for the current code. After recording in subtractive counter 17 a number on his second Manager (subtractive) input start receiving pulses from the first output of the pulse generator 12. With the arrival of each pulse the contents of the subtractive counter 17 is decremented by one. When the counter 17 at the output you receive a level corresponding to a logical unit, which indicates that the voltage at the DAC output has reached a steady-state value. Let for this code TO thei(served on the input of the DAC 15) settling time output voltage of the DAC is Tiand the period of the pulses from generator 12 is t. Then in subtractive counter what about the values produced from the second outputs of the ROM 18 for admission to the first control input (input record) pulse from the output of the sixth element And 10. When applying the pulse to the third control input of subtractive counter 17 its contents becomes equal to one.

The ROM 18 is intended for storage of digital codes used in the procedure of selection of the output code. In ROM 18 is also stored values of the delays for all codes used (corresponding to the time of establishing the voltage at the output of the DAC 15). The contents of the ROM is determined by the performed procedure code selection. In Fig.2 the graph shows one of the possible variants of the process of selection code for 4-bit ADC. In accordance with Fig.2, the process begins with a check code corresponding to the number 6 (the top of the root vertex). If at least one information channel, the input voltage less the voltage coming from the output of the DAC 15, the transition occurs along the edge labeled 0, in this case, the system switches to the top 4. Otherwise (the voltage at the input of all information channels more voltage coming from the DAC 15, a transition is made to the top 8 on the edge with label 1. The process continues until it reaches any hanging vertices. In this case, the voltage in the information channel for which the conversion is finished (usually the lowest scanal is disabled and will not affect the operation of the device. From hanging vertices there is a transition to the previous level, these transitions are indicated by the dotted arrow. The process continues until it is finished converting all of the information channels. For example, let the input of the first information channel is energized, the corresponding code number 9, to the input of the second and third channels - voltage, corresponding to the number 8 and to the input of the fourth information channel is the voltage corresponding to the code number 6. Then the sequence of scanned codes will correspond to the graph shown in Fig.3.

The contents of the ROM 18 for 4-bit multi-channel ADC is shown in the table.

The codes used in the recruitment process is recorded in the ROM 18 in the form of a sequence of words. The addresses of the words listed in the second column "Address". Address value is given in decimal form, and binary (in parentheses). In binary write address bits separated by a space, it is formed by the output signal of the second element And 6.

Each word has four fields. First the "Code" field contains the current code used in this step, the selection of the output code (the table shows the decimal value of this code and in brackets - sootvetstvuyuschego code from the "Code" field (in this case taken that time is proportional to the difference between the previous and the current code, for example when moving from vertex 8 to vertex 6 delay is equal to 2). The field "Output code" contains the code value, which will be delivered in accordance with the voltage information of the channel, the conversion is finished. Since the output code will be issued only upon reaching the hanging vertices, so this field is not always filled in (for other vertices it can be any value). The "Sign of the end" indicates that the current code corresponds to Fig.2 hanging the top (for hanging tops this field contains the unit).

The seventh element And 19 generates at its output the level of the logical unit, if the current code is the last possible combination (code all digits contains units), and the conversion of all channels is still not finished. It is possible, for example, when applying to the input of any of the information channel voltage exceeding the maximum voltage at the output of the DAC 15. The signal of the logical unit from the output of the seventh element And 19 flows through the second element OR 20 to the second input of the third trigger 13, allowing the trigger goes to the zero state and project after the conversion is complete, all information channel, when the second trigger 3 in all information channel 21 will be transferred in one state and work the third element And 7.

Consider the operation of the device when the procedure code selection in accordance with Fig.2 for the next case. ADC - 4. The number of information channels 4. Output voltage range output 4-bit MCS 15 is 10 V For 4-bit ADC in this case, the quantization step is equal to U = 10V/24= 10V/16 = of 0.625 V. This means that when applying to the input of the DAC 15 code, for example, equal to 8, its output will be a voltage UDAC= 80,625=5 V. Suppose also that at the input of the first information channel ADC voltage UWH=5,7 V, to the input of the second UWH= 5,2 V, third - UWH=5,1 V and the input of the fourth information channel - voltage UWH= 4,2 V. operation of the device is illustrated a time chart shown in Fig.4.

In the initial state, the third trigger 13 is in the zero state. When applying for his first entrance (start) pulse he goes into one state, which means the beginning of the process of analog-to-digital conversion. At the output of the trigger 13, you receive a level corresponding to the logical units is one, which clears the register 16, writes in subtractive counter unit 17 and moves the latter triggers 3 all information channels 21 in the zero state. Zero code with output register 16 will be transferred to the second address inputs of the ROM 18. However, regardless of the value of the signal at the first address input of the ROM 18, the first and second outputs of the ROM 18 will receive the code number 6 (table, row 1 or 17). The level of logical units with an output of the third trigger 13 will also be available at the control input of the pulse generator 12 and it will begin to issue pulses on the first and second outputs. The first pulse appears at the first output of the pulse generator 12 and he will be on the second (subtractive) the subtractive input of counter 17. Since the subtractive counter 17 has been recorded by the unit, its contents will be zero and the level of logical units will appear at its output, which goes to the second input of the sixth element And 10. With the arrival of the pulse from the second output of the pulse generator 12 to the first input of the sixth element And 10 it works, its output will appear in the pulse, the trailing edge of which is in register 16 and subtractive counter 17 written code number 6 with the first and second outputs of the ROM 18 (Fig. 2 this corresponds to the top 6). Code number 6 from the output of the register 16 of the settlement will go to the first inputs of the units of comparison 1 all information channels 21. In this case, the input voltage at the inputs of all information channels 21 exceeds the voltage at the DAC output 15, and outputs blocks of comparison 1 all information channels 21 formed level logical units. Accordingly, the level of logical units will appear at the output of all the first elements OR 4, respectively, and at all entrances of the second element And 6. The second And gate 6 will work and the level of logical units will be installed at the first address input of the ROM 18. Given that his second address inputs the code number 6 (with output register 16) at the first outputs of the ROM 18 set code number 8, and the second outputs code number 2 (table, line 23, columns 3 and 4).

After the contents of the subtractive counter 17 becomes equal to zero (at its second control input (input subtraction) constantly receives pulses from the first output of the pulse generator 12) and its output will be level logical units, with the arrival of the pulse from the second output of the pulse generator 12 will trigger the sixth element And 10 and the pulse from its output will go to the first control inputs (inputs write) register 16 and subtractive counter 17. On the trailing edge of this pulse in the subtractive counter 17 will be, Rav is which will arrive at the input of the DAC 15, at the output of which is formed a voltage UDAC= 80,625=5.0 V (Fig.4 time t3).

Now the voltage at the input of the fourth measuring channel 21 (and only it) is less than the DAC output 15. After the output of the subtractive counter will set the level of logical units and work the fourth element And 8, the first trigger 2 fourth information channel will be set in the zero state and its output (inverse) set the level of logical units. Since the first address input of the ROM 18 is a logic level zero, and the second address input code number 8, the first output ROM set code number 7, and the second outputs code number 1 (table, row 9). With the arrival of the pulse from the second output of the pulse generator 12 will trigger the sixth element 10 And a signal from its output into a subtractive counter 17 will be written to unit, and in the case of 16 - code number 7. Code output register 7 will arrive at the input of the DAC 15 and its output will be a voltage UDAC=70,625= 4,375 V (Fig.4 time t4).

The voltage at the input of the fourth information channel again less than the DAC output 15, the output of the second element And 6 and, therefore, the first address input of the ROM will be logiteck number 6, and at the same time on the fourth output of the ROM 18 is established level of logical units (table, row 8, columns 5 and 6). After the contents of the subtractive counter 17 becomes equal to zero, with the arrival of the second pulse from the output of the pulse generator 12 will trigger the sixth element And 10, then the fifth element And 9, the pulse from the output of which will go to the fourth output device by which any external devices can be fixed, the conversion result to the fourth information channel 21 with third outputs of the ROM 18 (in this case, the code number 6), thus, the number of information channel in a single position code will be available on the first output device (in the zero state is the first trigger 2 only the fourth information channel, and because you are using inverted output of the first trigger 2, then the corresponding bus is the level of logical units). The pulse output from the fifth element And 9 will also go to the second input of the first element And 5 each information channel 21, and the inverted output of the first trigger 2 will be rewritten to the second trigger 3. Because the first trigger 2 is in the zero state only in the fourth information channel, sootvetstvenno with his first (inverse) output will translate the first trigger 2 the same news channel in one state, will block the first element And 5 and will set the level of logical units on the output of the first element OR 4, resulting in further logic fourth information channel will not affect the operation of the device.

On the trailing edge of the pulse from the output of the sixth element And 10 in register 16 will be written following code value from the first outputs of the ROM 18, namely the code number 8 (table, row 8, column 3). DAC output 15 will set the voltage UDAC= 80,625= 5.0 V (Fig.4 time t5). In Fig.2 this corresponds to the return from the top 7 in the top 8.

Similarly, suitable selection of the output code for other information channels. Note only that for the second and third data channels, the conversion will be finished at the same time (Fig.4 time t8).

After finish converting all the information channels, the second triggers 3 all information channels 21 are installed in one state, respectively trigger the third element And 7, then the second element OR 20, the level of logical units from the output of which will go to the second input of the third trigger 13. With the arrival of the pulse from the output of the sixth element And 10 at its rear edge the third trigger t10). The output of the third trigger 13 is connected to the second output device, by which you can judge the condition of the device.

As follows from Fig.4, in the process of selection code for all four information channels used 8 code combinations. In the prototype we had to check the 16 combinations (24). Thus, the proposed multi-channel ADC can reduce the conversion time and, consequently, to increase the operating speed of the device.

The advantage of the device is also the possibility of implementing such a procedure code selection, which would take into account both the statistical characteristics of the signal and the time required to establish a voltage at the DAC output (which largely affects the performance of such an ADC). The task of finding the optimal matching code in this case corresponds to the well-known problem Troubleshooting in complex object restore (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under. editor I. A. Ushakov. - M.: Radio and communication, 1981. - S. 85-103). Selecting the ROM 18 in a single chip, with the possibility of replacement, you can find selection procedure code so C temporal characteristics of the DAC 15.

Multi-channel analog-to-digital Converter comprising n information channels, each of which contains first and second triggers, the first item, the unit of comparison, the first inputs are combined and connected to the output of the digital to analogue Converter (DAC), the second input of each unit of comparison is the corresponding input bus, a pulse generator, one-shot, second, third and seventh elements, NO element, characterized in that it introduced in each information channel of the first element OR the third trigger, the second element OR subtractive counter, a register, a persistent storage device (ROM), each information channel output of the Comparer is connected to the first input of the first element OR the first input of the first flip-flop, a second input connected to the first output of the second trigger and the first input of the first element, And output to the first input of the second trigger, the output of the first element And connected to the second input of the second trigger, the second output of which is connected to the second input of the first element OR the third inputs of the first triggers of all information channels combined and connected to the output of the fourth element And the second inputs of the first elements And all Informatsionnyi channels combined and connected to the output of one-shot, the outputs of the first triggers all information channel form a first output device that outputs the first elements OR all data channels connected to the corresponding inputs of the second element And the second outputs of the second triggers all data channels connected to the corresponding inputs of the third element And the first input of the third trigger is a control input of the second input of the third trigger is connected to the output of the second item OR the third input to the first input of the fifth element And the output of the sixth element And the first Manager of the input register and the first Manager of the subtractive input of the counter, the output of the third trigger is the second output device and is connected to the input of one-shot and managing the input of the pulse generator, the first output of which is connected with the second Manager of the subtractive input of the counter and to the first input of the fourth element And the second output of the pulse generator connected to the first input of the sixth element And a second input connected to the output of the subtractive counter and a second input of the fourth element, And a third input connected to the output element, the input of which is connected to the output of the second element And the first address input p is, the inputs of the digital-analog Converter and the output register, the first terminals are connected to information inputs of the register, the second output information subtractive inputs of the counter, third outputs are third outputs of the device, the fourth output is connected to a second input of the fifth element And whose output is the fourth output device, the output of the one-shot is connected with the second Manager of the input register and the third managing subtractive input of the counter, the output of the seventh element And connected to the first input of the second element OR the second input is connected to the output of the third element I.

 

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