Analog-to-digital converter

 

(57) Abstract:

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code. The technical result is a simplification of the device and applying optimal matching code, taking into account the statistical characteristics of the converted signal. The device includes a divider reference voltage, multiplexers, Comparators voltage, the register, the pulse generator, the trigger shaper codes. 1 table, 3 Il.

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code.

Known successive approximation ADC, containing a comparison circuit, a successive approximation register, a digital-to-analogue Converter (DAC), And clock (Chernov Century, Device I / o analog information to digital systems of data collection and processing. - M.: Mashinostroenie, 1988. - S. 85, Fig.57). Successive approximation ADC is characterized by the following features. During code selection method is used half della. The conversion process always takes N clock cycles, where N is the ADC.

The disadvantage of this device is its low performance, as the applied algorithm selection code (half division) optimal only in the case when the probability of the output codes are equal.

The closest to the technical nature of the present device is an N-bit ADC reading, containing the divider reference voltage, the inputs of which are respectively the first and second inputs of the device and are intended for connection of the reference voltage, 2Nstrobing voltage Comparators (KN), the first inputs of which are combined and the third input device is designed to input the converted voltage, the second inputs of the voltage Comparators are connected to the respective outputs of the voltage divider, and outputs connected to information inputs of the decoder, the outputs of which are connected to first inputs of the respective XOR, the second input of the first EXCLUSIVE OR element is the first control input output code, the second inputs of the other EXCLUSIVE OR circuits are combined and the second control input of the output is controlled by outputs of the device, the gate inputs of voltage Comparators, decoder and register are combined and the synchronization input device (Fedorov, B. Taurus C. A. Chip DAC and ADC: the operation, settings, application, - M.: Energoatomizdat, 1990. - S. 151, Fig.3.17) (prototype).

The disadvantage of this device is a significant challenge, because to build an N-bit ADC requires 2NComparators and a voltage divider containing the same number of the same resistance. It should be noted that the greatest challenge in implementing such an ADC in the integrated design is the creation of 2Nhigh-precision voltage Comparators.

The technical result - the simplification of the device by reducing the number of applied voltage Comparators as representing the greatest challenge in the implementation of the ADC in the integrated design.

The technical result is achieved by the N-bit ADC, containing the divider reference voltage, the inputs of which are respectively the first and second inputs of the device and are intended for connection of the reference voltage, M (M < 2N) strobing voltage Comparators, the first is imago voltage, register, put M multiplexers, the trigger pulse generator and shaper codes, the outputs of the voltage divider connected to the corresponding inputs of the multiplexers, the outputs of which are connected to the second inputs of the respective voltage Comparators, the outputs of which are connected with the first inputs of the driver code, the first group of outputs which is the first output device and connected to the first group of information inputs of the register, the rest of the group of outputs of the driver codes connected with the corresponding group of information inputs of the register, the first input of the trigger is the fourth input device, a trigger output, which is the second output device connected to the first control input of the register and the control input of the pulse generator, the output of which is connected to the gate inputs of voltage Comparators and the second managing input register, the first group of outputs of which are connected to the address inputs of the first multiplexer and the second input of the shaper codes, other groups of outputs connected to the address inputs of the respective multiplexers, the last output of the shaper codes connected to the second input of the trigger.

Structural, shaper codes and M multiplexers, which are standard nodes in digital computer technology and in the implementation of these nodes in the integrated design achieved significant progress. However, despite the fact that the blocks are standard nodes of digital computers, their introduction, as well as the emergence of new functional connections between them and the existing units gives the chance to appear in the device to a new property. Namely: ADC easier to implement, especially in monolithic integrated circuits, by reducing the number of high-precision voltage Comparators. While it introduced M multiplexers, and in this case they will make the greatest difficulty in the implementation of the ADC. But as you know, the multiplexer is a set of analog switches controlled by the decoder. When using CMOS technology, high-quality analog switches, which represents a straight-way valve, can be created on a chip very easily and in large quantities (Chernov Century, Device I / o analog information to digital systems of data collection and processing. - M.: Mashinostroenie, 1988. page 90, 20-25-th row from the top).

In affect, the voltage Comparators, the implementation of which is of considerable complexity, and at the same time it introduced multiplexers (most of whom are high-precision analog switches), whose implementation in the integrated design is much less complex task. The same can be said about the driver code. It can be implemented as a permanent storage device. Modern technologies allow to create a monolithic memory chip very large volume. Thus, the proposed device is simpler in implementation.

Structural diagram of the ADC is shown in Fig.1, where 1 is the divisor of the reference voltage; 2 - multiplexer; 3 - voltage comparator; 4 - the register; 5 - clock 6 - trigger; 7 - shaper codes.

The divider reference voltage 1 is a 2Nseries-connected identical resistor. The multiplexer 2 is designed to connect one of the outputs of the divider reference voltage 1 to the corresponding input of the voltage comparator 3. The number of plug-in input code is applied to the address inputs of the multiplexer 2. Strobing the voltage comparator 3 is intended for comparing voltage, postupala remember current codes, coming from the shaper's output codes 7, in the process of selection of the output code. Clock 5 is designed to synchronize the operation of the device. On the leading edge of the pulses from generator 5 is latched Comparators voltage 3, the trailing edge is an entry in the register 4 codes from the outputs of the shaper codes 7. The trigger 6 is designed for fixing the beginning of the conversion process and its completion. When submitting its first input signal "START" trigger 6 is set in one state, and starts the conversion process. When the signal of logical units on the last shaper's output codes 7 trigger 6 is set in the zero state and the conversion process ends.

Shaper codes 7 is designed to implement the process of selection code in the conversion process. Consider the process of selecting the code on one particular example. Let the ADC is equal to four, and the ADC contains two multiplexer and, accordingly, two voltage Comparators (M=2).

The process of selection code can be represented as a graph shown in Fig.2.

In accordance with Fig.2, initially, at the address inputs of the first is inego scheme) code is set to 6 (the top of the root vertex). Thanks to the multiplexers in the second inputs of the voltage Comparators 3 set voltage corresponding codes 6 and 9. Denote by UM1the voltage at the output of the first multiplexer and through UM2the voltage at the output of the second multiplexer. The outputs of the Comparators 3 depending on the input voltage, there are three possible combinations: 00 - when the input voltage UBXless than the voltage applied on the first and second multiplexers 2 (UBX< UM1and UBX< UM2); 10 - when the input voltage is above the voltage received from the second multiplexer, but less than the voltage received from the first multiplexer (UBX< UM1and UBX> UM2); 11 - when the input voltage is above the voltage applied on the first and second multiplexers. Then depending on the values of the codes at the output of the voltage Comparators 3 there is a transition on the corresponding arc of the graph. For example, if code 00 jumps to the top of 2-5, and accordingly the address inputs of the multiplexers 2 must be installed codes 2 (lower multiplexer) and 5 (upper multiplexer). The code selection process is terminated upon reaching the hanging vertices. In Naugolnykh.

The table shows how the driver code 7 must convert the codes supplied to its inputs.

Consider, for example, 4, 5, 6 table row. In the 4th column of the table everywhere is the number 9. This means that in the first output register 4 which are fed to the second inputs of the former (codes 7, installed code corresponding to the digit 9. In this case, if the output of the 1st and 2nd Comparators will be zeros (4th row in the table), then the first output driver code set code corresponding to the number 5 (4th row, 5th column of the table), and the second outputs set code corresponding to the number 2 (4th row, 6th column of the table). Ie provides the transition from the top 6-9 to the top 2-5 00 arc (Fig. 2). In the last column of the 4th row (corresponding to the signal value at the last shaper's output code 7) in this case is zero, which indicates that the hanging top is not achieved and the conversion process should be continued.

The driver code 7 can be implemented using a persistent storage device or a programmable logic matrices.

It should be noted that the process of selection code does not necessarily have to match what is depicted n the activities, which would provide a minimum average time of conversion or any other criterion. The optimal sequence of codes can be found by methods of theory of search (in this case, the searching code combination corresponding to the input voltage). Algorithms for solving such problems are considered, for example, in the book "Paszkowski, C. the problem of optimal detection and search failures in REA. - M.: Radio and communication, 1981. - 280 S.".

Consider the operation of the device when the procedure code selection in accordance with Fig.2 for the next case. ADC - N=4. The device contains 2 multiplexer 2 comparator (M=2). A reference voltage is connected to the divider reference voltage is 10 V. For the four-digit ADC in this case, the quantization step is equal to U = 10V/24= 10V/16 = of 0.625 V. This means that when applying to the address input of the multiplexer 2 of the code corresponding to, for example, the number 9, the output of this multiplexer will appear a voltageM= 9 * of 0.625 = 5,625 V.

Let the ADC input voltage UBX= 3,2 V.

The operation of the device, and therefore the process of converting the input voltage into the code begins with the filing of the fourth input device is uleva condition). The trigger 6 is transferred in one state and its output appears a level corresponding to a logical unit. Upon receipt of the leading edge of the voltage drop from the output of the trigger 6 to the first control input (input reset) register 4 it will be set in the zero state. The first group of outputs of the register 4 will be established code of zero, which will go to the second inputs of the former (codes 7. According to the table data (rows 1-3), regardless of the code at the output of the voltage Comparators 3, the first group of outputs of the driver code 7 code appears in the number 9 (lines 1-3, column 5), and the second group of outputs code number 6 (lines 1-3, column 6).

After the transition of the trigger 6 in one state level logical units of its output is supplied also to the control input of the pulse generator 5, and its output is starting to get a pulse on the second control input (input record) register 4. In case 4 on the trailing edge of the first pulse from the pulse generator 5 in the first group of inputs will be recorded code number 9, and the second group of input code number 6. This corresponds to the root vertex 6-9 graph in Fig.2.

Code number 9 from the first output register 4 will go to the address inputs of the first multiplexer 2 (in the forest inputs of the second multiplexer 2 (lower scheme) will be the code number 6 and its output will appear a voltage UM2= 6 * of 0.625 = 3,75 V. using voltage Comparators 3 compares the voltage outputs of respective multiplexers to the input voltage UBX= 3,2 V. With the arrival of the next pulse from the pulse generator 5 to the gate inputs of the voltage Comparators 3 on the leading edge of this pulse is fixed to the comparison results. In this case, the input voltage is less than the output voltage and the first and second multiplexers and the output of the Comparators will be a logic level zero.

So, at the first inputs of the driver code will be a combination of 00, and the second outputs code number 9 (with the first group of outputs of register 4). In accordance with the table (line 4), then the first output driver code set code number 5 (line 4, column 5), and the second outputs code number 2 (line 4, column 6 of the table). In Fig.2 this corresponds to a transition from vertex 6-9 in the top 2-5 conditionally 00. On the trailing edge of the second pulse from the pulse generator 5 codes numbers 2 and 5 will be written to the corresponding bit of the register 4, which in the future will go to the address inputs of the respective multiplexers 2. The output of the first multiplexer (upper which reduces the voltage UM2= 2 * of 0.625 = 1,25 V. In this case we have UBX> UM1and UBX> UM2. Consequently, at the output of the voltage Comparators is the combination 11. Given that the second inputs of the former (code 7 code is the number 5, then the first output driver code 7 code appears in the number 5 (line 9 of the table). At last the shaper's output code 7 will be set to the level corresponding to the logical unit (line 9, column 7 of the table). This signal is sent to the second input of the trigger 6 and install it to the zero state. Output trigger will set a level corresponding to a logical zero, which turns off the pulse generator 5. The process of converting the input voltage into the code on this end. The output from the first output of the driver code 7 will be the result of the conversion, i.e., the code number 5.

From the previous description it follows that the conversion process was over in about two stroke operation. Two bars will also be required when converting a voltage corresponding to the code numbers 6, 7, 8, 9. For other codes, the conversion time will be three steps (Fig.2).

Increasing the number of multiplexers, it is possible to increase the operating speed of the device. the Torah stresses. In this case, codes 6, 7, 8 can be obtained within one cycle of the device codes 2, 3, 4, 5, 9, 10, 11, 12 for two bars and codes 0, 1, 13, 14, 15 for three quantum devices.

Thus, when the simplification of the device compared to the prototype (the four-digit ADC reading must contain sixteen Comparators) proposed ADC allows to provide high enough performance.

The cost of equipment and the performance of the proposed ADC occupies an intermediate position between the ADC reading and successive approximation ADCS. Increasing or decreasing the number of multiplexers and Comparators, it is possible to get the desired performance parameters, which is an additional positive feature. The average conversion time can be reduced by applying optimal matching code. Selecting the driver code 7 in a separate chip, with the possibility of replacement, you can find selection procedure code in such a way as to ensure maximum performance under the given statistical characteristics of the signal.

Analog-to-digital Converter with N bits containing the divider reference voltage, the inputs of which being, M (M < 2N) strobing voltage Comparators, the first inputs of which are combined and the third input device is designed to input the converted voltage, the register, characterized in that it introduced M multiplexers, the trigger pulse generator and shaper codes, the outputs of the voltage divider connected to the corresponding inputs of the multiplexers, the outputs of which are connected to the second inputs of the respective voltage Comparators, the outputs of which are connected with the first inputs of the driver code, the first group of outputs which is the first output device and connected to the first group of information inputs of the register, other groups of outputs of the driver codes connected with the corresponding group of information inputs of the register, the first input of the trigger is the fourth input device, a trigger output, which is the second output device connected to the first control input of the register and the control input of the pulse generator, the output of which is connected to the gate inputs of voltage Comparators and the second managing input register, the first group of outputs of which are connected to the address inputs of the first multiplexer and the multiplexer, the last output of the shaper codes connected to the second input of the trigger.

 

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