Semiconductor storage device

 

(57) Abstract:

The invention relates to semiconductor memory devices. The technical result is to reduce the power consumption, small cross currents, the purity of voltage levels. The device has plenty of memory cells, the circuit selection control circuit, the circuit of the pump. 19 C.p. f-crystals, 10 ill.

The invention relates to a semiconductor storage device according to the restrictive part of paragraph 1 of the claims.

The main field of application of such semiconductor memory devices are nonvolatile, electrically erasable programmable semiconductor memory device, made of memory cells that can as often as desired to be programmed and re-erased by the application of certain voltages. Recall when this occurs due to the application or removal of charge on the so-called floating gate electrode. This is due to the application of suitable voltages to the lines of word and bit lines of the storage device. When the working conditions of reading with low voltage is typically 5 volantes. When programming and erasing in the contrast between the control gate and the source/drain/substrate apply a higher voltage is usually about 17 volts. These stresses are denoted in the following as high voltage as they exceed the absolute value of the supply voltage. Due to the high field strength, the electrons can tunnel through the potential barrier insulation effect Fowler-Nordheim) or formed near the drain of the hot electrons can overcome isolation (the channeling effect of hot electrons). As the supply voltage storage circuit is typically about 5 volts, shall be provided with control circuits for input from outside or produced inside the programming and erasing voltages, which can selectively enable these voltage on a memory cell (or, respectively, line, word and bit line). For circuit-technical and technological reasons it is preferred to limit the voltage range of at least one control line (bit line or lines of words) to a voltage equal to or less than the value of the supply voltage, and to apply a high voltage only other control is positive, and negative high voltage.

From Y. Yatsuda, etc., IEEE J. Solid-State Circuits, Vol. sc-20. No. 1., pages 144-151, 1985 known high-voltage control circuit for positive voltages, which uses an external beat Clock). Performed on the n-MOS transistors scheme, however, is not able to switch the negative high voltage. In addition, the scheme requires a relatively large capacity, to be able to give a sufficiently high charging current that the load could be charged during 50 to 100 μs.

From EP 320916 B1 became known control circuit for non-volatile, electrically erasable and programmable semiconductor memory device, which can switch both positive and negative high voltage and uses an external clock. This scheme is based on the principle of giving according to each load's own high voltage generator, which generates the required negative high voltage. The number of required stages of the generator, however, increases with the absolute value of the high voltage.

At higher voltages, this concept requires large floor space. In kachestvennom case does not clean the level of zero volts. In the prepare phase a certain value of the voltage on the load is applied prior to the charge. During the process of erasing level is limited only through the series connection of the n-MOS transistor and multiple, i.e. two or more p-MOSFETs. Due to this known scheme are also vulnerable to cross-interference. Reading mode and a voltage of +5 volts) and in write mode, a voltage of +15 volts) levels of zero volts are also not clean. Instead, the output voltage is the magnitude of the trigger voltage of the p-MOS transistor. The proposal to use a transistor with a trigger voltage of zero volts, shifts the problem in the region is more complex and thus more disadvantageous from a cost perspective technologies.

From IEEE Journal of Solid-State Circuits, vol 27, Nr. 11, 1 November 1992, pp. 1547-1553, HR, Toshi-katsu Jinbo and others, "A 5-V-only 16-MB Flash Memory with Sector Erase Mode" known semiconductor memory device according to the restrictive part of paragraph 1 of the claims, which provides control scheme as the Row Main decoder circuit with blocks a and B. the Circuit block a, which is also referred to as a normal block, connected after the n-MOS-FET depletion channel and a is used primarily for to convert a positive level signal at the negative voltage level of operation mode erase. For this purpose, the circuit block served In a negative high voltage to 13 volts from the cascade charge pump and include via the control signal ERA. This known control scheme allows thus to produce a selection of individual lines of words and manage negative erase voltage, along with running 5 or, respectively, 0 for read mode. Although the function of the known control scheme seems to be comparable with the function corresponding to the invention of the schema that underlies both schemes constructive concepts differ significantly from each other.

Next, the control circuit for the memory cells of the EEPROM is known from US-A-4823318. Also, and this control scheme is different essential specific features of the corresponding invention the control circuit.

From. US-A-4742492 known, the following control scheme, the goal of which is to put alternately on the capacitor on the output side, the voltage-Vgg, -Vpp +Vpp generated by the three generators of the charge pump. To do this, depending on the applied on input line upravlyauschaya from the corresponding invention the control circuit is a separate circuit characteristics.

The basis of the present invention, therefore, is the task of developing a device of the type described in the preamble of the description, which circuit is technically simpler, requires less space, is in General less power consumption and small cross-currents, and in all operating conditions provides a smoothed voltage levels, in particular, also smoothed zero (without ripple) voltage level.

This task according to the invention is solved by a device according to paragraph 1 of the claims.

According to the invention provides that the management of the electoral scheme signal selection of the group of memory cells for operating States erasing and saving the data content of memory cells provided corresponding to all memory cells of one group control scheme with a single control line for connection with all memory cells in the selected group, and on the control line to the selected group of memory cells selectively connects the erase or the reference voltage.

Corresponding to the invention of the concept of schema decides mentioned in the introductory part of the problem in a simple way and before testie together all memory cells of one group of the control circuit with a single control line for the active excitation or accordingly, inclusion as the erase voltage (negative high voltage) and the reference voltage (for example, with a strictly defined level of zero volts) circuit for generating high voltage circuit-technically can be done razmazanno from the control circuit in the form of separate circuit components. In contrast to the prior art is not required to be aligned with each load, and the load indicated is subject to excitation by the control circuit line and the corresponding circuit components (e.g., line, words), your own high voltage generator, which generates the necessary erasing voltage (negative high voltage). Taking into account the required number generator cascades, which increases with the absolute value of the high voltage, previously known concept at higher voltages is disadvantageous from the viewpoint of space (i.e. it is too resource-demanding). In comparison with the known solutions of the present invention allows to centrally provide the group of memory cells to the desired values of high voltage, which is supplied to the control circuit either outside or from yavleniya can be performed circuit is technically more simple and consist of only a few structural elements. Since the control circuit for reasons of maximum space economy should be implemented, as a rule, in a cellular raster advantage may be simple circuit-technical execution of the control circuit is preferred from the viewpoint of high-density integration. Simultaneously, the control circuit requires low power consumption and basically has no cross currents, which could contribute to power loss. In particular, when implemented in an n-pocket CMOS technology these advantages become of particular importance due to the fact that all n-MOS transistors have a common conclusion of the substrate (mass), and thus to enable negative voltage can be applied only to the p-MOSFET.

Corresponding to the invention the control circuit is able selectively, for example, depending on the signal applied to the memory cells, as the erase voltage (negative high voltage) and the reference voltage (the level of zero volts) in particular and without loss through a single control line. Since the memory cells form a relatively large capacitive load, best is to connect the voltage achieable, anyway, with minimal time delay.

To distinguish whether the group of memory cells to be erased, or should persist the data according to the invention provides that the control circuit for selecting, supplied to the control line of the erase voltage and the reference voltage is controlled by the signal selection produced is turned on before the control circuit diagram of the selection. It is advisable that the scheme of the signal of selection was connected in most cases to already existing in a semiconductor memory device, the address decoder or completed integrated in the semiconductor storage device. This allows not only completely erase large areas of semiconductor memory devices, but also within the larger cycles of the erase save only the contents of the selected groups of memory cells, resulting in you can reduce organizational costs of processing programs information. Another advantage is obtained due to the fact that since the reference voltage is in absolute value less than the erase voltage, the control circuit requires less time to on the tyranny of memory cells time necessary for the erase process may be reduced.

Further according to the invention provides that the control scheme for the active inclusion of the erase voltage and the reference voltage on the control line has a valid depending on the select signal or signal selection circuit pump that choice includes the erase voltage and the reference voltage without local generation of these voltages.

In the form of a development of the invention can be further provided that the semiconductor memory device can be operated in the third operating condition, which can be given in compliance with the programming, reading or saving the content data storage cells, and semiconductor memory device has connected through a switching device with a control circuit diagram of generating a programming voltage for supplying the control circuit with the opposite sign relative to the erase voltage, and exceeds the value of the supply voltage programming voltage for programming the memory cell, as given in compliance with the control circuit of the switching device for salesgenie to the control circuit of the read voltage, or subject to application to the control circuit of the reference voltage is controlled by the line state to the selected group of memory cells. Due to this, all voltages required for programming, reading, erasing and maintain the data content of memory cells, can be applied through a single line.

For the application of the voltage, supplied from the circuit generating the programming voltage, or the smaller the absolute value of voltages of the same sign can be provided that before the switching device may be included given the scheme of generating the programming voltage driving circuit, which outputs to the switching device voltage, the values of which correspond to the third operating state for programming, reading and storing the content data storage cells. This allows the application in principle any number of stresses with the sign opposite to the sign of the erase voltage. The stability of these voltage levels depends largely on the quality of the exciting circuit.

To communicate the exciting circuit with the control circuit may be OEM home button Flex cable is mu in the first and second operating condition of the applied reference voltage, and in the third operating condition is applied issued by the circuit voltage levels.

For communication circuits generate the erase voltage from the control circuit may be provided that the control circuit contains associated with the generation of the erase voltage to the second voltage input to which the first and the second operating condition is applied erase voltage and the third operating condition of the erase voltage or the voltage of which absolute value is less than or equal to the programming voltage.

To connect reference voltage and to communicate the exciting circuit with the control circuit can be provided that the control circuit contains to be activated through the first internal clock input and connected between the first input voltage and the control line of the first pump, which in the first operating state is a lock between the first input voltage and the control line, in the second operating condition works as a scheme of pumping from the first input voltage to the control line and in the third operating condition works as a scheme of pumping between associated with the first input voltage of the circuit and control is treno connecting the reference voltage through a pumping mechanism, to prevent failure of the reference voltage due to leakage currents or interference, which causes a decrease once the deposited charge. Further, it can be provided that the first pump connects voltage, supplied from the exciting circuit and having an opposite sign than the erase voltage, with the control line.

For the active inclusion of the erase voltage may be provided that the control circuit contains to be activated through the second internal clock input, a second pump connected between a second input voltage and the control line, which in the first operating condition works as a scheme of pumping from the second input voltage to the control line and the second and third operating condition as a schema lock between the second input voltage and the control line. Second, the pumping scheme determines when active Poluchenie the erase voltage by a pumping mechanism to prevent failure of the erase voltage due to leakage currents or interference, which causes a decrease once the deposited charge, and causes, on the other hand, with the active prikluchenii reference voltage or when vaginosi operation may be provided, the first pump has associated with externally controlled input reset to the initial state, the switch is reset to its original state to the first operating condition, the pumping scheme worked reliably as a schema lock. Can be provided by the control input reset to the initial state when coming from the address decoder the address change to the first pump, above all, securely blocked.

As another measure may be provided to the second circuit pump contained managed through the first internal clock input, deactivating the switch to the second and third operating state of the second pump worked reliably as a schema lock. Due to this, additionally provided that when connecting the reference voltage or when communicating summarized from the exciting circuit voltage of the erase voltage is blocked.

For schema generation voltage can be provided that the semiconductor storage device for at least one interconnected group of memory cells of one line of word or bit lines arranged on the semiconductor substrate in a matrix form at the intersections of Azania and a single circuit generating the programming voltage, which is given in accordance with at least one control circuit. This allows the use of globally generated voltages that can be generated on the semiconductor substrate, and thus from the outside. In both cases, this leads to savings in the area of the mounting area compared with the previously known schemes.

To activate the first and second circuit pump can be provided that the control scheme given in compliance scheme selection, which depending on the applied to the input selection signal of the selection gives in accordance applied to external clock input external clock signal with the first or second internal clock output. To activate pumping schemes may provide a clock signal, which is selectively supplied to the first or second pump.

At the same time to activate the first and second circuit pump, for example, can be provided that the scheme of selection when a logical zero input selection applies the external clock signal in opposite phase to the first internal clock output and sets the second internal clock output to a logical unit, and when a logical unit on the input selection applies NR is chovy output at a logical zero.

For the communication scheme selection with the control circuit can be provided that the first and the second operating state of the first internal clock circuit output selection associated with the first internal clock input and the second internal clock circuit output selection associated with the second internal clock input. As in the first and second operating condition, respectively, is active one of the two pumping schemes, these operating conditions may be provided by clock signals.

To communicate the exciting circuit through the control circuit with memory cells can be provided that switches the first and second circuit pump and attached according to the second pump deactivates the switch contain, respectively, the MOS field-effect transistors with a common, externally managed by the conclusion of the substrate. Due to this can be applied on a semiconductor substrate different potentials, which allows linking summarized from the exciting circuit voltages, which have the opposite sign of the erase voltage.

In a particularly simple circuit-technical realization of circuit pump can be advantageous that the first internal clock input is connected first of hypoxia supplied from the exciting circuit of the voltage levels may be provided, the circuit in the first operation mode depending on the applied input selection signal excitation selection of excitation generates a voltage level for programming or to save the content of the data, and in the second mode generates a voltage level for reading. This allows solely depending on the signals that should not have special electrical power be applied to a single control line voltage of different sign, and the voltage of both characters can exceed the supply voltage.

In a further form of execution of the invention can be provided that in General, externally managed the conclusion of the substrate in the first and the second operating condition is applied the reference voltage, in the third operating condition and the first mode is applied programming voltage and the third operating condition and the second operating mode, the applied read voltage.

To enable fast switching times can be provided that in the third operational state to the first internal clock directly after switching to the third operating condition of the applied clock signal with Sirenevy signal only in the initial phase and then to maintain it at a level which holds the switch to the first pumping circuit pump open.

In a further preferred form of execution can be provided that the scheme selection contains a second external clock input for the application is separate from the external clock signal of the second external clock signal and attached in accordance with the second internal clock output and both clock inputs the amplitude of the doubler, applies when a logical zero input selection external clock signal in opposite phase to the first internal clock output and sets the second internal clock output to a logical unit, and when a logical unit on the input selection applies the external clock signal in opposite phase with increased in comparison with the external clock signal, the amplitude of the second internal clock output and sets the first internal clock output at a logical zero. In a further form of execution, in particular, the second circuit pump may be provided for applying clock signals that exceed the supply voltage, in order to reliably control the switches of the circuit of the pump.

With regard to applied technology and physical design remember the project is on the order of +5 volts, the erase voltage is of the order of 12 volts, and the programming voltage is about +18 volts.

Further characteristics, advantages and expedient forms of execution of the invention follow from the description of examples of implementation with the help of drawings on which is shown:

Fig. 1A and 1b schematic design memory cells are nonvolatile, electrically erasable programmable semiconductor memory device;

Fig. 2 - the location of the storage cells and their relationship with the bit lines and lines of words;

Fig. 3 is a schematic representation of a wiring diagram of the first exemplary embodiment of the control circuit with the circuit selection with amplitude doubler;

Fig. 4 is a schematic diagram wiring schema excitation for positive voltages;

Fig. 5 - schematic representation of the simulation with the voltage applied at the input of the selection and the control line, as a function of time after application of the erase voltage and the reference voltage to the line of words;

Fig. 6 - schematic representation of the simulation with the voltage applied at the input of the selection, the control line, the second within the ve functions of time after application of the erase voltage and the reference voltage to the line of words;

Fig. 7 - schematic representation of the simulation with the voltage applied at the input selection output circuit of excitation and on the control line, as a function of time after application of the programming voltage and the reference voltage to the line of words;

Fig. 8 is a schematic representation of the simulation with applied input selection, output circuit excitation and on the control line voltages as functions of time during application of the read voltage and the reference voltage to the line of words;

Fig. 9 is a schematic representation of a wiring diagram of a second exemplary embodiment of the control circuit with the circuit selection without amplitude doubler; and

Fig. 10 is a schematic representation of a wiring diagram of the third exemplary embodiment of the control circuit with the circuit selection without amplitude of the doubler.

With the help of Fig. 1A and 1b must first explain the construction and principle of operation of electrically programmable and erasable semiconductor memory device with lots of storage cells SZ. Each memory cell SZ consists of the control electrode 1, galvanically isolated electrode 2, source 3, the area of Ino unleashed electrode 2, the insulator 7 is located between the galvanically isolated electrode 2, on the one hand, and the area of source 3, the drain region 4 and a region of the substrate 5, on the other hand. The galvanically isolated electrode 2, which is surrounded by insulators 6 and 7, is located between the control electrode 1, the area of source 3 and drain region 4. Recall corresponds to the application and removal of charges on the galvanically isolated electrode 2. This is due to the application of suitable voltage between the control electrode 1 and the drain region 4. For reading to the control electrode 1 make positive relative to the area of the drain 4 voltage, which typically is about and +2.5 volts, and thus is of the order of magnitude of the supply voltage, and which is not sufficient to electrons or holes could overcome the insulator. For programming to the control electrode 1 apply a positive high voltage, which typically is about +18 volts and thus exceeds the supply voltage to inject electrons into the galvanically isolated electrode 2. To erase the negative high voltage, which typically is about -12 volts and such to inject holes in the galvanically isolated electrode 2. When programming and erasing due to high field strengths electrons or holes can tunnel through the potential barrier insulator 7 (effect of Fowler-Nordheim) or formed near field flow 4 hot electrons can overcome the insulator 7 ("the channeling effect of hot electrons").

In a typical storage device according to Fig. 2 when reading the stored contents data from the storage cells SZ bit line 8 is connected with the output of the source cell or remains disconnected. Provided (not represented in more detail), awarded in compliance with the bit lines 8 amps reader, which detects the state of a cell by detecting the current through the memory cell SZ current or by detecting a potential bias on the corresponding bit lines 8. Reference position 9 indicate the lines of words for addressing the storage cells SZ are connected with (not represented in more detail) decoding scheme addresses. The details of the layout and principle of operation of such storage devices are known to the expert and do not require here a more detailed description.

Fig. 3 shows the first preselective 10 includes input selection 12, the first external clock input 13, the second external clock input 14, the first internal clock output 15 and the second internal clock output 16. Further, the scheme selection 10 consists of a logical element with the negation 17 and logical element OR denial 18. Accordingly, the first inputs of both logic elements 17 and 18 are connected to the input selection 12 and, respectively, the second inputs are both logic elements 17 and 18 are connected with the first external clock input 13. The output of the logic element And denying 17 corresponds to the first internal clock output 15 scheme selection 10. The output of logic element OR denial 18 is connected through a capacitor 21 to the second internal clock output 16 of the circuit selection 10. Similarly, the second internal clock output 16 is present, the connection point of two series-connected transistors 20. It consists of two transistors 20 consecutive circuit applied voltage Vpp. The control input of one of the transistor 20 is connected directly to a clock input 14, while the control input of the other of the two transistors 20 is connected via the logical element NOT 19 with the second external clock input 14. To the control inputs of both transistors 20 through this postaudits. The control circuit 11 has five inputs 22, 23, 26, 33, 34 and a single exit 35. The inputs 22 and 23 are associated with the internal clock outputs 15, 16 scheme selection 10 internal clock inputs of the control circuit 11. The input 26 is externally managed by reset input in the initial state. The first voltage input 33 depending on the switching device 36 in the first and the second operating condition is associated with a weight, which in all the examples represents the potential of the reference voltage, or the third operating condition is associated with a positive supply voltage circuit 37. The second voltage input 34 is connected with the generation of the erase voltage, generating a negative high voltage. Through the control line 35 and the corresponding line of words 9 (see Fig. 2) are controlled by the control electrodes 1 storage cells SZ. The first internal clock input 22 through a capacitor 24 is connected with the control input acting as a switch pump transistor 31. Between the control input of the transistor 31 and the reset input in the initial state 26 intermediate included working as a switch reset to the initial state of the transistor 27, the control input of which peg as switch pump transistor 32. Between the first voltage input 33 and control input of the transistor 31 intermediate included working as a deactivating switch transistor 28, which has together with the transistor 31 control input. Between the control line 35 and control input of the transistor 32 is enabled robotaxi as a switch in a feedback transistor 30, a control input which is also connected with the control line 35. Transistors 28, 30, 31 and 32 have a common, managed outside the conclusion of the substrate 29. In all the examples provided, that to the first voltage input 33 in the third operating condition is applied summarized from the exciting circuit 37 positive voltage and the first and second working state level of zero volts. Similarly, all of the examples of execution provided that the inlet 34 in the first and second working condition make summed schemes generate the erase voltage negative high voltage, and a third operating condition or summarized from the circuit generating the erase voltage negative high voltage or the voltage of which absolute value is smaller than or equal to the programming voltage. These voltage fail or NR is not represented in detail. With this in principle requires only two voltage generating circuits, one for positive voltage for reading and the positive high voltage for programming and the other for negative high voltage to erase.

Using a shown in Fig. 3 of the first exemplary embodiment is illustrated in the following principle. The control circuit 11 operates in three operating conditions. In the first and second working state, the first voltage input 33 is connected through a switching device 36 to ground. If the input selection 12 is applied a signal corresponding to the first operating state, through the control line 35 and attached to the respective storage cells SZ line of words 9 to the control electrodes 1 make available to a second input voltage 34 negative high voltage of about -12 volts, in order to erase to inject holes in the galvanically isolated electrodes 2 storage cells SZ. If the input selection 12 is applied a signal corresponding to the second operating state, through the control line 35 and attached to the respective storage cells SZ line of words 9 lying on the ground voltage input 33 potential mass applied is agenia 33 summarized from the exciting circuit 37 through the switching device 36 positive voltage serves on the control line 35. In the first working state of the input selection 12 zero applied voltage, which is applied to the first external clock 13 clock signal with twice the amplitude U23,max served on the second internal clock output 16 and thus to the second internal clock input 23. Made of the logical element 19, both transistors 20 and capacitor 21, the amplitude of the doubler is necessary for reliable control of the transistor 32. On the second internal clock input 23 to do this requires the clock signal U23 with amplitude U23,max, which exceeds the triggering voltage uint32_t, min transistor 32 to a double value. For the supply circuit of the amplitude doubler 19, 20, 21 to the two external clock inputs 13, 14 attached two separate clock signal with the upper voltage level of 5 volts and the low voltage level of 0 volts. Through applied on the second internal clock input 23 of the clock signal U23 activates the second pump consisting of a capacitor 25 and transistor 32, and a packet takes is applied to a second input voltage 34 negative high voltage. Applied at the control input. transistor 32, the voltage uint32_t composed initially of applications operated on/BR> and when you run the clock signal U23 with amplitude U23,max on the second internal clock input 23 is reduced by the difference

dU=U23,max-2/uint32_t min/

between applied on the second internal clock input 23 clock amplitude U23, max, and a double value of the absolute value of the triggering voltage uint32_t,min transistor 32:

U35-U35-dU.

The above equations fair, of course, only if the capacity of the capacitor C25 25 is large compared with the parasitic capacitances and capacitances C30, C32 transistors 30 and 32. The first internal clock output 15 and thereby also the first internal clock input 22 is deactivated, which means that the switch of the pump 31 of the first circuit of the pump serves as a lock between the first voltage input 33 and the control line 35. The reset input in the initial state 26, except when the change of address, attached permanently to weight. The address changes at the input of the reset state 26 briefly apply the supply voltage to set the control inputs of the transistors 28 and 31 on the non-negative potential. The control inputs of transistors 28 and 31 may otherwise due to the connection above the critical to get to the negative potential, causing the transistors 28 and 31 could GE is th is applied to the first external clock input 13 of the inverted clock signal is connected to the first internal clock output 15 and thus to the first internal clock input 22. Using the clock signal consisting of a capacitor 24 and the transistor 31, the first pump is activated and switches applied to the first input 33 of the potential mass to the control line 35. In contrast, the second internal clock output 16 and thus also the second internal clock input 23 is deactivated, causing the switch to the pump 32 of the second circuit pump serves as a lock between the second voltage input 34 and the control line 35. In the third operating state of the input selection 12 is also applied to the level of five volts, which is applied to the first external clock 13 clock signal switches to the first internal clock input 22. Due to the clock signal activates consisting of a capacitor 24 and transistor 31 of the first pump and switches on the control line 35 is applied to the first input 33 of the positive voltage, supplied from the exciting circuit 37 through the switching device 36. Depending on the signals applied to both inputs of the selection of the excitation 43, 44 of the circuit 37 on the first input voltage 33 is applied programming voltage, the read voltage or zero voltage. Accurate the are the same voltage, as on the first voltage input 33. To achieve a rapid switching times may be appropriate to include the quantum only in the initial phase and then to maintain it at a lower level. Due to this, the control input of the transistor 31 remains at a negative potential, causing transistor 31 remains open. The second internal clock output 16 and thus also the second internal input 23 are empty, due to which the switch of the pump 32 of the second circuit pump serves as a lock between the second voltage input 34 and the control line 35.

Fig. 4 shows the details of the exciting circuit 37, which is connected to the circuit generating the programming voltage, is connected through the switching device 36 from the control circuit 11, 39, 40 and causes applying a positive voltage to the control circuit 11, 39, 40. The circuit 37 contains three inputs 42, 43, 44 and one output 45. The output 45 is provided for communication through the switching device 36 with the first voltage input 33 of the control circuit 11. The circuit 37 is composed of four transistors, two p-channel field-effect transistors 46, 47 and two n-channel field-effect transistors 48, 49. The input 42 is a voltage input to connect the first voltage, which typically is about +18 volts. The inputs 43 and 44 are input to the selection of excitation. Depending on the signals applied to the inputs of the selection of the excitation 43 and 44, the circuit 37 or includes applied at the input 42 of the positive high voltage for programming, or includes a typical image with the height and +2.5 volts partial voltage for reading, or served in the capacity of the masses to save the contents data to the output 45 and thus to the first voltage input 33 of the control circuit 11, 39, 40.

In Fig. 5-8 presents the temporal characteristics of the voltages applied in various selected points is shown in Fig. 3 schema.

Fig. 5 shows the time characteristic of the voltage signal 50 applied to the input selection 12, and signal 51 applied on the control line 35. By control of the input selection 12 is switched between the first and second operational status. The level of zero volts on the input selection 12 corresponds to the first, and the level of five volts to the second operating state. If the input selection 12 applied level of five volts, to the control line 35 serves potential mass to be applied to the first voltage input 33, which is connected, on voltage 34 voltage erase which here is about -12 volts, serves on the control line. The process of pumping lasts about 5 μs, while previously reached a certain voltage. After switching on the input selection in contrast, requires only about 2 μs, while the reference voltage is applied to the control line.

Presented on Fig. 6 characteristics voltage 52, 53, 54, 55 pass the same process as in Fig. 5. Presented on Fig. 6 chart 52 and 53 correspond to the diagrams 50 or 51 in Fig. 5. Additionally in Fig. 6 shows the characteristic voltage 54 on the second internal clock input 23 and the characteristic voltage 55 on the second switch of the pump 32. In both points, the voltage oscillates with the frequency of the clock signal. In the first operating condition, the amplitude of both signals 54, 55 is of the order of 7 volts, while in the second operating state, the amplitude of both signals is of the order of 4 volts. Applied at the control input of the second switch pump 32 signal 55 corresponds applied to the control line 35, the amplitude-modulated signal 54 at the second clock input 23 to the signal 53.

In Fig. 7 presents diagrams 56, 57, 58, to the course of the voltage 33 and the characteristic voltage 58 on the control line 35 in the third operating condition. Input selection 12 is always 5 volts as applied the signals 56 are significant only for the first two operating States. Comparison of specifications voltage 57 to the first voltage input 33 and the characteristics of the voltage 58 on the control line 35 indicates that the control circuit 11 switches summed up from the exciting circuit 37 positive high voltage "approximately without delay. The delay time is less than about 1 μs.

In Fig. 8 similarly, Fig. 7 shows the switching summarized from the exciting circuit 37 positive voltage, and the characteristic voltage 59 to the input selection 12, the characteristic voltage of 60 on the first voltage input 33 and the characteristic of voltage 61 on the control line 35 is provided in the third operating condition. Instead of the programming voltage, which is about +18 volts, is applied to the readout voltage of the order and +2.5 volts. Also in this case, the delay times are about the same order of magnitude as for the application of a programming voltage, and lie below in the order of 1 μs.

Presented on Fig. 9 the second exemplary embodiment corresponding to the invention the control circuit 39 in basically predstavljaet a variant of scheme selection 10, reduced the amplitude of the doubler 19, 20, 21 and the second external clock input 14. Scheme selection 38 consists of entrance selection 12, the first external clock input 13, a logical element with the negation 17, a logical element OR denial 18 and the internal clock outputs 15 and 16. The control circuit 39 of the second exemplary embodiment is also a shortened version of the corresponding circuit 11 according to the first exemplary embodiment. There is no working as a deactivating switch transistor 28 and transistor 32 in comparison with the control circuit 11 control input can be mutually replaced with the associated with the control line 35 electrode. The transistors 30, 31 and 32 have a common, externally managed the conclusion of the substrate 29.

The amplitude of the doubler 19, 20, 21 to the control circuit 39 is not required, so as to control the transistor 32 is sufficient any low voltage U23, the Shah on the second internal clock input 23. At each period of a clock signal U23,max. applied to the second internal clock input 23, accumulated on the capacitor 25, the charge is uniformly distributed on the capacitor 25 and acting as a capacitive load CSZa memory cell contained in the second internal clock input 23 of the clock signal and the capacitance of capacitor C25 25.

U32=U35-->uint32_t=U35-(C25-->U23,max)/(C25+Csz)

To the control circuit 39, on the one hand, are sufficient clock signals with small amplitude U23, max on the second internal clock input 23, on the other hand, when a disadvantageous ratio of containers, in which the capacity of the capacitor C25 25 is small compared to the capacity of the Csz managed storage cells SZ, control line 35 flows only a small current, which means a relatively long-lasting process of pumping. This disadvantage can be eliminated only through capacitor 25 with high capacity C25 and related large footprint on the semiconductor substrate 5.

Presented on Fig. 10 the third exemplary embodiment comprises the control circuit 40 and from the same schema selection 38, as in the second exemplary embodiment. The control circuit 40 is performing with elements of the control circuits 11 and 39 of the first two examples. Compared with control circuit 39 of the second exemplary embodiment, the control circuit 40 of the third exemplary embodiment further comprises a transistor 32, which is connected in series with transistor 41 and has a common control input. Point of connection both enabled each other transistors 32 and 41 is connected by acting as a feedback loop transistor 30 in contrast to the control circuit 39 from the second exemplary embodiment is included between the General Manager of the output transistors 32 and 41 and the connection point of the transistor 41 to the condenser 25. Transistors 28, 30, 31, 32 and 41 have a common, externally managed the conclusion of the substrate 29.

In the first operating condition, the control circuit 40 operates in comparison with the control circuits 11, 39 as follows. As in the control circuit 39, the amplitude of the doubler 19, 20, 21 is not required in the control circuit 40 to activate the second pump 25, 32, 41. Because of the two transistors 32 and 41 in comparison with the control circuit 39 is improving output load factor. Each time period is applied to the second internal clock input 23 of the clock signal U23 accumulated on the capacitor 25, the charge is distributed uniformly on the capacitor 25 and acting as a capacitive load, S32, 41 control inputs of the transistors 32 and 41, which leads to applied to the control line 35 voltage U35 next hop:

U35-->U35-(25U23,max)/(C25+C32,4l)U35-U23,max

Due to the relatively small capacity, S32,41 corresponding control inputs of the transistors 32 and 41 to the capacitor 25 does not require too much capacitance C25 and thus does not require too much space on the semiconductor substrate 5. With a small capacitor 25 can be achieved quickly process pump. In the second and third working status is a synthesis of control circuits 11 and 39.

1. Semiconductor storage device, containing a number of memory cells (SZ), located on the semiconductor substrate (5), configured to operate in at least two modes, the first of which corresponds to erasing the contents of the memory cells (SZ), and the second is to preserve the contents of memory cells (SZ), and also provides a scheme for selection for selection of one group of memory cells (SZ) corresponding to all memory cells (SZ) one group control circuit (11, 39, 40) with one control line (35) to communicate with all memory cells (SZ) of the selected group in both modes, and the control circuit (11, 39, 40) for selection of the erase and the reference voltage on the control line (35) is arranged to control the signal generated in the circuit selection (10, 38), included before the control circuit (11, 39, 40), characterized in that the control circuit (11, 39, 40) contains the current depending on the signal selection circuit pump comprising first and second circuit pump, made with a possibility of erasing and reference voltages to the selected group of memory cells (SZ).

2. Semiconductor storage device according to p. 1, from which CITYVIEW or save the contents of memory cells (SZ), and, additionally, there are connected through the switching device (36) with the control circuit (11, 39, 40) scheme of generating the programming voltage to the control circuit (11, 39, 40) with respect to the erase voltage of the opposite sign and surpassing the value of the supply voltage, and the switching device (36) for the selective supply control circuit (11, 39, 40) the programming voltage or the read voltage or the reference voltage is arranged to control, via the control line (35).

3. Semiconductor storage device according to p. 2, characterized in that before the switching device (36) after the circuit generating the programming voltage on the circuit (37), is arranged to feed switching device (36) of the voltage levels corresponding to the third operation mode for programming or reading or storing content data storage cells (SZ).

4. Semiconductor storage device according to p. 2 or 3, characterized in that the control circuit (11, 39, 40) has an associated switching device (36) of the first input voltage (33), to which the first and second working mode is ptx2">

5. Semiconductor storage device according to one of paragraphs. 1-4, characterized in that the control circuit (11, 39, 40) is associated with the generation of the erase voltage to the second voltage input (34), to which the first and second operating modes of the applied erase voltage, and a third mode - erase voltage or the voltage of which absolute value is less than or equal to the programming voltage.

6. Semiconductor storage device according to one of paragraphs. 2-5, characterized in that the control circuit (11, 39, 40) contains a run through the first clock input (22) of the first pump (24, 31) connected between the first input voltage (33) and the control line (35) and is configured to provide locking between the first voltage input (33) and the control line (35) in the first mode, with the possibility of functioning as a scheme of pumping from the first input voltage (33) to the control line (35) in the second mode and to operate as a scheme of pumping between the circuit (37) associated with the first input voltage (33), and the control line (35) in the third mode.

7. Semiconductor storage device according to one of paragraphs. 2-5, differently the(25, 32) connected between the second voltage input (34) and control line (35) and has a capability of functioning as a scheme of pumping from the second voltage input (34) to the control line (35) in the first mode and the second and third modes - as a schema lock between the second voltage input (34) and control line (35).

8. Semiconductor storage device according to one of p. 6 or 7, characterized in that the first pump (24, 31) has associated with controlled reset input (26) the switch is reset to the initial state (27).

9. Semiconductor storage device according to one of p. 7 or 8, characterized in that the second circuit pump (25, 32) contains managed through the first clock input (22) deactivating the switch (28).

10. Semiconductor storage device according to one of paragraphs. 1-9, characterized in that at least one group of memory cells (SZ) one line of words (9) or bit line (8) located on a semiconductor substrate (5) in the form of a matrix at the intersections of a line of words (9) and bit lines (8) contains a single generation of the erase voltage and the circuit generating the programming voltage that the device according to one of paragraphs. 1-10, characterized in that connected to the control circuit (11, 39, 40) scheme of selection (10, 38) is arranged to switch, depending on the applied to the input selection (12) signal selection external clock signal to the external clock input (13), respectively, on the first or second internal clock outputs (15 or 16).

12. Semiconductor storage device according to one of paragraphs. 1-11, characterized in that the circuit selection (10, 38) at logic zero at the input (12) selection is made with the possibility of transferring the external clock signal in opposite phase to the first internal clock output (15) and install a second internal clock output (16) to a logical unit, and when a logical unit on the input (12) - transmission of the external clock signal in opposite phase to the second internal clock output (16) and install the first internal clock output (15) to a logical zero.

13. Semiconductor storage device according to p. 11 or 12, characterized in that the first and second modes, the first internal clock output (15) scheme of selection (10, 38) connected to the first internal clock input (22) of the control circuit and the second internal clock output (16) scheme of selection (10, 38) is connected with Evo on one of the PP. 9-13, characterized in that each switch both the first and second circuit pump(30, 31, 32, 41), and deactivating the switch (28) contains the MOS field-effect transistor, with all of the specified MOS field-effect transistors have one common for all externally managed the conclusion of the substrate (29).

15. Semiconductor storage device according to p. 14, wherein the first internal clock input (22) of the control circuit connected to the first capacitor (24) and the second internal clock input (23) of the control circuit connected to the second capacitor (25).

16. Semiconductor storage device according to one of paragraphs. 7-15, characterized in that the circuit (37) is executed with a possibility depending on the applied inputs selection of excitation (43, 44) signal output voltage for programming or reading, or to save the data content.

17. Semiconductor storage device according to one of paragraphs. 14-16, characterized in that the total managed the conclusion of the substrate (29) in the first and second modes of the applied reference voltage, the third and first modes of the applied voltage for programming, and in the third and second modes applied apraise fact, in the third mode of operation on the first internal clock input (22) directly after switching to the third mode of the applied clock signal with a predetermined duration.

19. Semiconductor storage device according to one of paragraphs. 1-18, characterized in that the circuit selection signal (10) contains a second external clock input (14) for the second external clock signal and the amplitude of the doubler (19-21) with the second clock output (16) and two clock input (13, 14), and with a possibility of issuing at logical zero input selection (12) of the external clock signal in opposite phase to the first internal clock output (15) and install a second internal clock output (16) to a logical unit, and when a logical unit input selection (12) - distribution of the external clock signal in opposite phase with increased in comparison with the external clock signal, the amplitude of the second internal clock output (16) and install the first internal clock output (15) to a logical zero.

20. Semiconductor storage device according to one of paragraphs. 1-19, characterized in that the reference voltage is a zero voltage, the supply voltage has a value of about +5 V to the 8th Century

 

Same patents:

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The invention relates to the field of digital computer technology and can be used in integrated circuits for MOS transistors

Address shaper // 2010361
The invention relates to computing and can be used to build storage devices and input registers of microprocessor systems

The invention relates to a method of complete reprogramming erasable non-volatile memory of the control unit

FIELD: computers.

SUBSTANCE: each variant of computer system, in particular block for controlling operation processes in transporting means, contains two memory devices, inner-system bus, central processor, input-output block, ROM, self-loading block, flash-memory. Methods describe operation of each variant of said systems.

EFFECT: higher efficiency.

6 cl, 7 dwg

FIELD: electronics.

SUBSTANCE: method for erasing information recorded on a microchip with heterogeneous semiconductor carrier with power-independent memory includes injecting short-term nominal power voltages onto the microchip and the controlling gate. During that time in the conductors of the microchip, positioned on its substrate, Foucault currents are excited with intensity of at least 60 mA with by irradiating the conductors of the microchip with two orthogonal alternating sinusoidal magnetic fields. Irradiation is conducted using three kicking coils by magnetic fields at sharp angles on two sides of the perpendicular to the substrate. In the plane, which lies perpendicularly to the direction of magnetic field expansion, the direction of its vector is changed between 90° and 270° with the frequency of the first magnetic field ω, with value not less than 6,28 rad·kHz and intensity, sufficient for excitation of Foucault currents in the conductors of the microchip with value of not less than 20 mA. In the plane, which lies perpendicularly to the direction of expansion of second magnetic field, the direction of its vector is changed between 180° and 360° with frequency of second magnetic field valued between 2ω and 4ω. The value of amplitude of second magnetic field more than twice exceeds the value of amplitude of first magnetic field. Irradiation using the second magnetic field is started after one quarter of frequency period after beginning irradiation using the first magnetic field. The duration of irradiation should not be less than duration for which nominal microchip power voltage is enabled. A carrier is positioned in the fourth cylinder kicking coil. Transverse dimensions of kicking coil hollow exceed transverse dimensions of the substrate with recorded information. The throttle is positioned inside the third cylinder throttle coaxially. The first and second circular kicking coils are positioned coaxially on the opposite sides of the third kicking coil in such a way, that the longitudinal axis of first and second kicking coils is orthogonal to the longitudinal axis of third and fourth kicking coils, and these axes intersect in the middle of the third kicking coil.

EFFECT: increased reliability of information deletion without possible restoration, reduced time of erasure, reduced power consumption.

3 cl, 9 dwg

FIELD: information technologies.

SUBSTANCE: in case when value of input data for recording is more than value of existing data in memory matrix, semiconductor storage device permits recording of input data into memory matrix. Reading controller reads existing data from memory matrix and compares them to data for recording fixed in 8-bit latch register. In case when value of data for recording is more than value of existing data, incremental controller generates signal WEN1 to permit recording into controller of recording/reading and performs record of data for recording, fixed in 8-bit latch register, into memory matrix.

EFFECT: protection of semiconductor memory device against recording of input data in it, which do not satisfy specific requirements to data.

30 cl, 15 dwg

FIELD: information technology.

SUBSTANCE: flash memory based systems are used for storage of streaming HD video data. Flash memory devices are physically accessed in a page oriented mode. Input data are written in a multiplexed fashion into a matrix of multiple flash devices. List processing is performed and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data. In case an error occurred in the current page in one or more flash devices, the content of these current pages is kept in the additional memory buffer.

EFFECT: providing adaptation of writing modes depending on detected writing defects.

14 cl, 7 dwg

FIELD: physics.

SUBSTANCE: device has a contact pad (1) lead connected to control gates of floating-gate MOS transistors of memory elements (13), with sources of diode-connected n-channels of transistors (9 and 10), a p-channel MOS transistor (4), whose drain is connected to the drain of the diode-connected n-channel transistor (5), whose source is connected to the drain of the transistor (13), with the input of a modulator (20) and with the drain of the diode-connected n-channel transistor (6), whose source and the gate of transistor (4) is connected to the positive supply bus (+Ep) (19). The leads of contact pads (2 and 3) are connected to a resonance antenna circuit. Lead (2) is connected to drains of transistors (7), (9), (11) and the gate of transistor (8), and lead (3) is connected to drains of transistors (8), (10), (12) and the gate of transistor (7). Drains of transistors (11 and 12) are connected to the positive supply bus (+Ep) (19). Sources of transistors (13) are connected to drains of address n-channel MOS transistors (14), whose sources are connected to drains of address n-channel MOS transistors (15), whose sources and drains of transistors (7) and (8) are connected to the earth bus (⊥) (18). Gates of transistors (14) and (15) are connected to outputs of row (16) and column (17) decoders, respectively.

EFFECT: smaller size of the integrated circuit chip of a radiofrequency identifier, as well as possibility of writing an individual code in a block of read-only memory elements.

1 dwg

Decoder // 2307405

FIELD: computer engineering, possible use for designing rapid action clocked recording devices of high capacity.

SUBSTANCE: decoder contains field transistors of first and second conductivity types (8-19), zero first (1), zero inverse (2) and first, second, ..., n (3) address inputs, input of mode selection (4), power contacts of first (5) and second (6) of voltage level, block of parallel-connected n transistors (7) with channel of first type, gates of which are connected to corresponding n inputs (3), first output buffer element (20), output of which is the first output (21) of decoder, second output buffer element (22), output of which is the second output (23) of decoder.

EFFECT: increased reliability and reduced mass-dimensional characteristics.

1 dwg

FIELD: charge reading device and energy-independent memorizing device with passive matrix addressing.

SUBSTANCE: charge reading device contains two charge support means, two pseudo-differential support reading amplifiers (RSA1; RSA2) and a pseudo-differential reading amplifier (SA). Another variant of the device is meant for reading charges from a set of means (701) for charge storage and contains at least two pairs of charge supporting means, two pseudo-differential support reading amplifiers (RSA1; RSA2) and at least two pseudo-differential reading amplifiers (SA). Energy independent memorizing device with passive matrix addressing contains dielectric memorizing material, having hysteresis and capable of electrical polarization, and aforementioned system of reading amplifiers.

EFFECT: improved charge balancing, output signal control, ensured automatic shift in cophased mode, automatic correction of zero level shift.

3 cl, 10 dwg

FIELD: method, aimed at weakening interfering voltages which occur in data storage device which has passive matrix addressing.

SUBSTANCE: in accordance to the method, injection of electric potentials is performed in time-coordinated manner, which corresponds to impulse injection protocol. During execution of addressing operation a memory cell adjusts to first polarization state by receiving first active voltage impulse. Then, depending on the protocol used, second voltage impulse is injected, which may be second active voltage impulse with polarity which is opposite to polarity of first impulse. Given voltage impulse is used for switching the cell to second polarization state. Cells of device are configured in two or more electrically divided segments in such a way, that each segment corresponds to an individual space of physical addresses. During conduction of addressing operation data is directed into segment, which is selected on basis of information about previous and/or planned injections of active voltage impulses into segments.

EFFECT: increased efficiency.

36 cl, 35 dwg

FIELD: information technology.

SUBSTANCE: electronic device for saving power in a memory device has memory comprising a plurality of number buses. The memory includes a plurality of memory banks, wherein each of the plurality of memory banks includes a pair of sub-banks, each pair of sub-banks sharing pre-decoded data. The electronic device also includes a plurality of number bus generators connected to memory, wherein each number bus generator is associated with the number bus from the plurality of number buses of the memory. Power in each of the plurality of number bus generators is switched off in the default state except during the period for accessing the number bus. The electronic device also includes a decoder which is connected to the plurality of number bus generators in order to receive a request for accessing memory, and in order to decode the request for accessing memory in order to determine the address associated with the request for accessing memory. The decoder records the selected number bus generator but not other number bus generators from the plurality of number bus generators, in response to the request for accessing memory.

EFFECT: reduced current leakage in memory devices.

11 cl, 9 dwg, 3 tbl

FIELD: information technology.

SUBSTANCE: dual voltage semiconductor memory device having a plurality of write drivers receiving low voltage data input signals; a plurality of bit lines connected to the plurality of write drivers, wherein the plurality of write drivers is configured to write low voltage data input signals in the plurality of bit lines in response to reception of low voltage data input signals; a timing tracking circuit configured to delay a high voltage number line signal in accordance with the time associated with the plurality of write drivers which write low voltage data input signals; and a plurality of memory cells which react to the high voltage number line signal and the plurality of write drivers writing the low voltage data input signals.

EFFECT: reduced power consumption.

30 cl, 6 dwg

Decoder 2 in 4 // 2547231

FIELD: information technologies.

SUBSTANCE: device comprises four logical NOT elements, four logical AND elements, two signal breeders.

EFFECT: increased efficiency and development of a device, in which internal transformation of information is carried out in two-digit current form of signals determined by condition of input current binary signals.

4 cl, 10 dwg

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