Device priority service requests
(57) Abstract:The invention relates to the field of computer engineering and can be used for processing requests based on their priority service. The technical result is to increase speed and reliability. The device contains a register of requests, the elements OR element And a generator of clock pulses, a counter, a decoder, a trigger and keys. 1 Il. The invention relates to the field of computer technology, in particular to a device priority service requests.A device for the priority service requests , containing a register of applications, the input of which is connected to the information input device, the registers of priority items AND, OR, the counter, the outputs of which are connected with the first inputs of the circuits compare the outputs are connected to first inputs of elements And the first group, and the counting input of the counter is connected to the output element And the first inverted input of which is connected to the zero input trigger control, a single entrance through which the first element OR is connected to control inputs of the device with a single input counter and the pulse generator.The disadvantage fetnah application timeout application with a lower priority is very large, in some cases, is illegal and may result in the loss of low-priority applications.The closest technical solution to the present invention is a device for servicing requests , which allows to extend the functionality of the device by ensuring that the waiting time to service requests and contains the register of applications, registers of priority made in the form of a summing counters, two groups of elements, And two groups of elements, OR a counter, a pulse generator and a frequency divider.The disadvantage of this device is low speed, the greater complexity and as a consequence low reliability.The purpose of the invention is to enhance reliability and performance of the device by reducing its instrumental composition and improving the management of his work.This objective is achieved in that the device priority service requests containing the register of requests, a single input bits which is connected to the information input device, and outputs connected to the inputs of the OR element, the output of which is connected to the first input element And a second input connected with the control input device, and vygodskaya. Information outputs of the counter are connected to the inputs of the decoder, the outputs of which are received at control inputs key information inputs which are connected to the outputs of register requests, and outputs the keys are connected to the inputs of the OR element. The output element OR is connected to the input of the trigger control signal which sets the trigger to zero, and the entrance that sets the trigger unit is connected with the control input device. The trigger output is connected with the control input of the counter. The outputs of keys connected to the zero inputs of the respective bits of the register requests and information input device.Diagram of the device shown in the drawing.Device priority service requests contains a register of requests 1, item OR 2, key 3, item, OR 4, the trigger control 5, item And 6 clock 7, a counter 8, a decoder 9, line requests 9, line control keys 10, the information line key 11, the input set trigger control in Nol, the input set trigger control in edinica, the control input of the counter 14, the counting input of the counter 15, which runs the generator input clock pulses 16, line, signal processing devices, the information output device 19, the discharge line application with the register of requests 20.Device priority service requests is as follows.Isolated inputs bits of register requests 1 with information inputs 9 requests maintenance requests. Requests to establish appropriate discharge register requests in one state. Requests have their own priorities, rigidly associated with the bits of register requests. From the output of register requests 1 pings each of your lines of communication are received at the inputs of the OR element 2. When there is at least one request in the register 1, the output signal from the OR element 2 is supplied to one of inputs of the element And 6 and readiness processing device, as evidenced by the presence of a signal at the control input device 17, with the output element And 6, the signal at the enable input 16 clock pulses 7 and runs it. The output signal of the generator 7 through line 15 arrive at the counting input of the binary counter 8, which starts to work and generate on their outputs a sequence of binary codes corresponding to the non-priority applications received. Binary codes with the outputs of the counter 8 are received on the inputs of designatory receives signals from the outputs of the bits of register requests 1, relevant applications received. When matching the priority of the service request another application with binary code generated by the counter 8, on one of the outputs of the valve 3 is formed of a single signal, which is output 19 of the device, processing system and initiates the processing of the application. At the same time this signal is fed via line 20 to the corresponding input register of the queries 1, setting to zero the state of the corresponding bit of register requests 1, thus preparing the reception of a new application of this priority.The counter 8 in each cycle of operation generates a binary sequence of non-priority applications, starting with the highest priority, until then, until it matches the binary code priority number counter and the priority number of the received request.If no service request of the i-th application, the corresponding digit of the register of requests 1 remains in the zero state. As a consequence, the signal at the output of the valve 3 will also be zero. The device then verifies the availability of a request from another application with a lower priority.After finding the request with the highest priority, as evidenced by a single signers control input 12 of the element OR 4 outputs a signal, sets the trigger control 5 to zero, and thereby interrupts the operation of the counter 8. The next series of search requests for service will begin only after servicing system will signal that opens the trigger 5 of the control input 13 of the device along the line 18. This signal indicates that the processing device has handled the previous request and is ready to take the next one.Thus, one cycle of operation of the device will be found in the request with the highest priority from coming to this point in time queries.Since the proposed device, in comparison with the prototype  total number of items reduced by approximately two times due to the exclusion of registers-counters priorities, schema comparison, elements And the first and second groups, and also controls the starting and stopping of clock pulses, all this leads to a decrease in the failure rate of the device is approximately two times and, consequently, to improve reliability of the device.The increased performance provided by the fact that, first, the signal processing at the service of a application by using the 3 elements and 4 elements in prototypa without stopping the clock unlike the prototype, where the clock stops whenever it detects a request from the application with the highest priority. This improves the throughput of the device.In addition, during the cycle of operation of the device serves all applications, including low priority.Literature
1. USSR author's certificate 475622, CL G 06 F 9/18, 1975.2. USSR author's certificate 898435, CL G 06 F 9/46, 1982 - prototype. Device priority service requests containing the register of requests, a single input bits which is connected to the information input device, and outputs connected to the inputs of the OR element, the output of which is connected to the first input element And a second input connected with the control input of the output element And is connected to allow the generator input clock pulses, the output of which is connected to the counting input of the counter, characterized in that it additionally introduced decoder, trigger, keys, and another element OR, the inputs of which are connected to the outputs of the keys, and the output connected to the input set trigger to zero, thus the outputs of the decoder are connected to control inputs of the keys, and informacia, the input set trigger unit connected with the control input device, the keys are connected to the zero inputs of the respective bits of the register requests and output devices, and input keys connected to the outputs of register requests.
FIELD: computer science.
SUBSTANCE: device has n-byte query register, query limits location systems, each of which consists of counting timer and OR element, OR element, AND element, keys cascade.
EFFECT: higher reliability and speed of operation.
FIELD: method and device for processing data for preserving recurrent status in data processing device.
SUBSTANCE: device has data processing block, having multiple functioning modes, for each of which special memory stack is present. Method describes operation of this device. Data carrier contains program, configuring data processing device for performing stages of method.
EFFECT: decreased size of code and decreased interruption processing delay.
3 cl, 16 dwg
FIELD: engineering of information processing systems.
SUBSTANCE: system contains master-system for processing information, interface, central communication device, client system for processing information, object model. In accordance to method each master system sends to central communication device elements of its data array determined in appropriate master-representation, while in master-representation of connected master system elements of data array are contained, for which system has data priority.
EFFECT: simplified specification and development of interfaces between technical applications.
2 cl, 6 dwg
FIELD: engineering of interrupt processing mechanisms in computer systems.
SUBSTANCE: system contains processor with multiple contexts for execution of commands stored in memory. In response to common interrupt logical processors of processor with multiple contexts compete for receiving access to jointly utilized register. First logical processor gaining access to aforementioned jointly utilized register processes common interrupt. Remaining logical processors return from interrupt.
EFFECT: increased productiveness of system.
4 cl, 5 dwg
FIELD: computer engineering, possible use in data exchange systems and local computing networks.
SUBSTANCE: device contains N≥2 client blocks, clock impulse generator, N client time controllers, OR element, AND-NOT element, selector-multiplexer, two N-input AND-NOT elements, two priority encoders, main wait time controller.
EFFECT: increased probability of timely servicing of clients under conditions of real functioning process of data exchange systems, with continuous dynamics of change of modes of different priority requests from clients.
4 cl, 7 dwg
FIELD: engineering of computers for controlling memory, in particular, external memory controllers.
SUBSTANCE: memory control device for operation in memory controller network contains memory controller being an owner unit, capable of controlling the blocking of certain data area during execution of input-output outputs, and component for exchanging messages, providing for transmission of at least one message with blocking request, permission of blocking, blocking removal request and blocking removal signal, and also input-output component, while any image of aforementioned data area, received by instant copying thereof, is maintained as coherent relatively to data area itself, and input-output component may position previous direct confirmation, that this data area remains coherent to any such image, to cash-memory, and may perform input-output operations on basis of aforementioned previous direct confirmation. Method describes operation of aforementioned device. Software product for computer is realized on machine-readable carrier and contains a program recorded thereon, realizing operations of aforementioned method.
EFFECT: expanded functional capabilities.
3 cl, 3 dwg
FIELD: engineering of means for pausing execution of a stream until certain memory access occurs.
SUBSTANCE: in one variant of realization, processor contains a set of executive devices, capable of executing a set of streams. First stream includes a command, which determines the address being tracked. Logical pausing means pause execution of first stream, and monitor causes renewal of first flow as reaction to access of given address being tracked.
EFFECT: increased processor productiveness.
5 cl, 14 dwg
FIELD: methods for automatic execution of a program, connected to data file, when data file and program being executed are positioned on different computer units.
SUBSTANCE: in methods, program being executed is accessed through graphic image of data file type, realized in the network, which includes client system and a set of server systems. Client system receives the scheme, which determines connection between the set of programs being executed and corresponding set of data file types. Graphic image of data files is displayed, information about selection of graphic image of data file is received from server system, on basis of it program to be executed is selected and executed.
EFFECT: increased productivity of system due to distributed execution of programs.
9 cl, 19 dwg, 3 tbl
FIELD: method and system for providing user interface information to client.
SUBSTANCE: in accordance to the invention, access system contains registration mechanism. Client environment for automatic processing of user interface receives registration information from the client and transmits user interface information after receipt. Server for automatic processing of user interface receives registration information from client environment for automatic processing of user interface and notifies processor of user interface about registration, and also receives user interface information from user interface processor. The server contains filtration device for filtering out information of no interest to client, and notification device for notifying the client about information which is of interest to the client.
EFFECT: ensured capacity for filtration and coordination of excessive and disorienting notifications.
2 cl, 11 dwg
SUBSTANCE: device contains a set of central processor units, which are assigned a common external up address in telecommunication network which allows packet data. IP messages, addressed to a network element, are received, and received IP messages which contain first messages are identified. First value is identified in first message and first message is transmitted to central processor unit on basis of identified first value, if identified first value is not equal to zero.
EFFECT: ensured load balancing for central processor when using several types of traffic.
3 cl, 3 dwg