Asynchronous processing unit

 

(57) Abstract:

The invention relates to data processing. The technical result is to increase functionality. The device contains a set of asynchronous control circuits, stopping circuit for blocking the control signal in the cycle control first asynchronous control circuits. Stopping scheme prevents the exchange of data signals to the first asynchronous control circuits with other asynchronous control circuits. The method describes the operation of the specified device. 3 S. and 12 C.p. f-crystals, 4 Il.

The technical field to which the invention relates

The invention relates to an asynchronous device data processing and more specifically to a technique that enables asynchronous processing unit to operate with improved energy efficiency.

Art

A processing unit such as a microprocessor, typically implemented using a synchronous architecture, because it is generally accepted that it is more simple for asynchronous architecture. Synchronous microprocessors are running guided from the outside of the synchronization signal, while asynchronous microprocessor external clock complicates the design of the microprocessor. For example, the designer must consider how to manage the data flow in the absence of a reference oscillator signals, and the delay of processing elements should be measured by the circuit, instead of them just to simulate the trigger period.

But microprocessors synchronous architectures do not have the proper energy efficiency. The synchronization signal in the synchronous pattern is generated continuously, resulting in the scheme of transitions occur, the scattering energy. The sampling clock should be set to such values that the processor was able to handle peak load, and despite the fact that the frequency of the signals can be adjusted under control of software in accordance with the changing requirements, this can be done only relatively rough and low granularity. Therefore, the synchronization signal for the most part has a higher frequency than is required to support the current workload, and the result is loss of power.

So you want microprocessor with improved energy efficiency.

The invention

Accordingly, this invention provides a device for abrabesorse cycle management request-confirm to control the flow of data in this asynchronous control circuit, it is configured to exchange data signals with at least one other scheme from a specified set of asynchronous control circuits; the first of these asynchronous control circuits includes a stopping circuit for blocking the control signal in the cycle control first asynchronous control circuit, thereby preventing the exchange of data signals with the specified at least one other scheme from a specified set of asynchronous control circuits to cause the blocking of the control cycles of a specified set of asynchronous control circuits.

This invention provides a device-based asynchronous architecture. Asynchronous architecture causes transitions in the circuit only in response to a request for performing useful work. It can instantly be switched between zero scattering power and maximum performance on-demand. Since many embedded application tasks are rapidly changing workload, found that asynchronous processor provides an opportunity to significantly save energy.

Most microprocessors design as the circuit of CMOS structure, and Kocku most of the microprocessors of the prior art - asynchronous and therefore use free running signals, they cannot easily control their actions; and when the program has no more be performing useful work tools software is usually transferred in a continuous cycle, with or without performing any work, or by polling the peripheral device until the input signal. Both of these solutions represent a continuous action in the circuit and dissipate significant amounts of energy, while not performing any useful work, or doing it in a very small volume, unless there is an interruption or until the peripheral device does not receive an input signal. Asynchronous processor that executes the same program will also waste energy without performing any work.

This invention solves this problem by introducing the "stop" circuit, which causes the cessation of all actions of the processor until an interrupt. This scheme works by intercepting control signal in asynchronous control circuits of the processing unit and through the effective opening of the single cycle control request-confirm. Since the control circuit is placed in the device, and therefore, stop, ultimately, cover the entire device as a whole, stopping all actions. Preferably, the interrupt is used to cancel the stop in the initial cycle management, and then to action spread from this point throughout the system.

Therefore, this invention applies insensitive to delay the nature of asynchronous control circuits in the processing unit in order to stop at one control point in the cycle control one of the control circuits with the subsequent spread of stops throughout the system.

Preferably, the execution stops schemes with block request signal generated by the control cycle of the request-confirmation, but skilled in the art it will be obvious that the stop circuit can also instead be performed by blocking the confirmation signal instead of the signal request.

In preferred embodiments of the first asynchronous control scheme is implemented with the ability to execute commands, and the device also includes a comparison circuit for comparing commands that can be executed with a predetermined command, ukazywania include in the decoder command processing unit, but you can place it in another location in the device. In the preferred implementation predetermined command is a command for branching branching in the current command. But skilled in the art it will be obvious that in order to lock and unlock cycles control of asynchronous control circuits can use other solutions and that the use of such teams branching is not significant.

Preferably, stopping the scheme contained the first logic circuit having inputs for receiving one or more interrupt signal and stop signal generated by the comparison circuit and indicating an executable command is consistent predetermined command. The first logic circuit may have an input for receiving the signal of execution, which is used to confirm that the control signal in the cycle control first asynchronous control circuits need to block. The signal of execution used in the preferred embodiments of the reason that, for example, the stop cycle control may depend on the result of the previous executed command. In this case, the signal will be sent to if the result team branching, and in this case, the stop command should not be executed, and the signal of execution respectively set to "inactive".

The first logical circuit can be performed in any appropriate way, but in the preferred implementation of the first logic valve is AND IS NOT to derive the logical value 0 when all inputs are set to logic 1; one or more interrupt signals are logic 1 in the inoperative condition, and the remaining input signals are set to logic 1 in the current state.

Stopping circuit preferably also includes a second logic circuit having inputs for receiving the request signal of the control cycle of the request-confirmation and the output signal of the first logic circuit, and the output of the second logic circuit is connected to an independent receiver to the request signal. In the preferred implementation of the second logic valve is And why it is performed with the opportunity to not output the request signal when the output signal of the first logic circuit is set to a logical 0. Skilled in the art it will be obvious that to perform logic stopping schemes can ispath the implementation of this invention, the interrupt signal is used to unlock the control signal, blocked stopping circuit, thereby enabling the exchange of data signals between the control circuits and thus causing the unlocking of the control cycles.

In preferred embodiments of the cycles control request-confirm using the communication Protocol level signaling.

In accordance with a preferred implementation of many of asynchronous control circuits include a set of interacting asynchronous pipelined circuits.

The processing unit according to this invention may be of any appropriate shape, but in the preferred implementation of this device is a microprocessor.

On the other hand, this invention provides a method of processing data in a processing unit, comprising the following steps: providing a variety of asynchronous control circuits for data processing, each asynchronous control scheme uses a loop control request-confirm to control the flow of data in this asynchronous control circuit and configured to exchange data signals with at least one other with the nogo conditions - blocking control signal in the cycle of the first control scheme specified asynchronous control circuits, thereby preventing the exchange of data signals with the specified at least one other scheme from a specified set of asynchronous control circuits for the realization of the lock control cycles specified multiple asynchronous control circuits.

Brief description of drawings

The implementation of the present invention described only as an example with reference to the drawings, in which similar reference signs are used for similar features and in which:

Fig. 1A and 1B is a schematic of two different communication protocols that can be used to control the flow of data in an asynchronous microprocessor;

Fig. 2 is a block diagram of a structure of a RAM of the processor in accordance with a preferred implementation of the present invention;

Fig. 3 is a diagram of the internal organization of crystal that contains the memory of the processor of the preferred embodiments in addition to the portion of memory;

Fig. 4 - schematic diagram of the logical components used to lock and unlock cycle of the request-confirmation in asynchronous with the description of the preferred embodiments of the invention

Before a detailed description of the structure of the microprocessor in accordance with a preferred implementation of the next will set-out some basic information about asynchronous design.

Asynchronous design is a complex and multifaceted discipline, with many different approaches to solving her problems. It is necessary to provide a method for flow control in the absence of any reference clock. The processor in accordance with the preferred implementation option for flow control uses forms handshakes type "request confirmation". The sequence containing the message data from the sender to the recipient, the following:

1) the sender places on the bus valid data value;

2) the sender then sends the event "Request";

3) the recipient receives the data when it is ready for this;

4) the receiver sends the event the Confirmation to the sender; and

5) the sender can then remove the data from the bus and start following message when it is ready.

Data sent over the bus using a standard binary encoding, but the "Request" and "Confirmation" mo is Finance", in which the change in signal level (either high to low or Vice versa) is an event. Fig. 1A depicts a communication Protocol using transition signaling. In accordance with Fig.1A: after the sender has placed valid data value on the bus (indicated by transition 10), it then sends a request event, indicated by the transition from low to high 20. The receiver then reads the data from the bus and sends the event of confirmation to the sender - specified transition 30 of Fig.1A. After the sender has received this event confirmation, he can then remove the data bus is indicated by the transition 40. In accordance with the image at the right side of Fig. 1A this sequence of steps is then repeated for subsequent data values. According Fig.1A is a change in level from high to low 25, 35 also indicates the direction of the query and the event confirmation.

Another solution for signaling events request and confirmation is to use a communication Protocol level signal according to Fig. 1B, in which the front signals the event, and the phase return-to-zero must occur before you can signal the following message. To the sender at the transition 20, and upon receipt of the data values, the receiver sends an event confirmation when moving 30. As communication Protocol transition signaling, the sender can then remove the data value from the bus when crossing 40. But in addition, upon receipt of the event confirm the sender removes the query event is indicated by a transition from high to low 50; and then the recipient removes the event confirmation is indicated by a transition from high to low 60. This sequence of events is then repeated for the next value of the data placed on the bus.

According Fig.1A and 1B transitional signaling is conceptually clearer, since each transition plays a role, and therefore synchronization is determined by the circuit function. This signaling also uses the minimum number of transitions and therefore should be effective from the point of view of energy efficiency. But used to control the transition CMPOP structure is relatively slow and inefficient, and therefore, in a preferred implementation of the present invention, the processor uses the communication Protocol level signaling, which uses more high-speed and energy-saving schemes, despite what nchronization phases of recovery (return to zero) in the Protocol.

Using the foregoing methods of self-synchronization it is possible to design a block of asynchronous pipelined data processing to account for the delay of data processing at each stage and one of these protocols to send the result to the next stage. Appropriate design can take into account the various delays in the processing of data and arbitrary external delay; the important thing is the local ordering of events, although, of course, long delays will have the result of low performance.

In contrast to synchronous conveyor used in a synchronous processor, when the whole pipeline must always be synchronized at a speed determined by the slowest stage in the worst environmental conditions (voltage and temperature), and on the basis of worst-case data - asynchronous conveyor will operate with a variable speed determined by the current conditions. It is possible to prevent a rarely occurring conditions the worst case that the data processing unit worked a little slower. In these cases, when such conditions arise some loss in performance, but since such cases are quite rare, their Wilmette self-synchronization for control of asynchronous pipelined block of data follows a detailed presentation of the operational processor memory (RAM represents the portion of the processor, which is used to perform common data processing functions in accordance with a preferred implementation of the present invention and with reference to Fig.2, which is a block diagram of the structure of a RAM of the processor. Its structure is based on the totality of interacting asynchronous pipelines, each of which operates in its own time mode with his usual speed. These conveyors can make the processor unacceptably long delay, but in contrast to synchronous conveyors asynchronous pipeline can have a very small delay, because the pipeline does not depend on clock cycles and therefore can operate at its inherent rate.

The processor starts with the address of the interface 200, which issues requests to fetch in memory 210 through the line 205. Address interface 200 has an independent device increment address, which gives him the opportunity to pre-fetch commands as much advance notice as allow containers of various pipeline buffers. This logical unit increment to determine the next address shown tract-branch 215. After the pipeline memory sulfuric order to direct them into a logical scheme of decoding commands 230. After decoding the command decoder 230, they are sent on path 235 to the pipeline control 240.

In addition to issuing a query command, the address interface also sends requests for data in the memory 210. After the data is fetched data value read in the register file 250 via path 245. Then the Executive plan of the conveyor 260 reads commands from the pipeline control 240 and executes these commands, based on the data values read from the register file 250. The execution results are sent to the address interface 200 on highway 265 and you can return in the register file 250 on highway 270. Upon receipt of the results from the pipeline execution address interface 200 sends the results to the pipeline memory 210 on highway 275 for storage in memory.

When the address interface 200 sends the retrieval commands in the memory 210, it sends the value of the program counter (SC) requested on highway 285 in the pipeline SC 280. From there, the value of IC can be considered in case of SC contained in the register file 250, where they can be used as operands by executable their teams. Pipeline SC need to remember the values of IC, the corresponding values in the pipeline memory to each of command.

Address interface 200 can be performed with the possibility of prefetch commands sequentially from the current value IC, and then all deviations from sequential execution will be sent as adjustments from the pipeline execution to the address interface.

In preferred embodiments of the present invention, the RAM of the processor can be combined with part of the memory, for example, 4 kilobytes of memory; however, this part can be configured either as cache or as a fixed area NVR and flexible memory interface ("funnel"), which will allow the direct connection of 8-, 16 - or 32-bit external devices, including memory allocated from the NVR with direct access. The internal organization of the crystal, which includes a memory processor in accordance with a preferred implementation of the present invention and 4 kilobytes of memory, shown in Fig.3.

Because of the lack of a reference clock in an asynchronous data processing system question synchronized sampling from memory has a special significance. In accordance with a preferred implementation of the appropriate measures provided for in the crystal p the NGO to crystal and configuration registers and loaded during start-up and the defining characteristics of the organization and synchronization in each memory area. The reference delay is generally reflects the access time of the external STOPV, and so NVR is configured in such a way as to take one of the reference delay. ROM, which usually is much slower, can be configured with the adoption of several reference delays. It should be noted that the reference delay is used only for synchronization outside of the crystal, and all delays in the crystal are self-synchronizing.

4 kilobyte memory is preferably configured as a cache containing four blocks of 1 KB; each of these blocks is a fully associative memory device of arbitrary replacement for numeric bus quartz delay line and the block size. The pipelined register 410 between sections ABC 420 and NVR 430 enables the next sample to start your search for ABC at the time when NVR ends the earlier sample. Thus, by exploiting the memory of the processor to issue multiple memory requests to return the data from the first query. Subsequent requests will detect, and they bypass the view ABC, thereby saving energy and improving performance.

After the above picnometry followed by the description of the scheme, which is used to lock and unlock feedback loop of asynchronous control circuits.

As mentioned above, the microprocessor contains a number of interconnected asynchronous control circuits, each of which applies a control cycle request-confirm to control the flow of data. By blocking response in one of these cycles control unit, ultimately, will be distributed around the microprocessor, stopping all the action.

In a preferred implementation of the present invention provides a scheme that provides locking and subsequent unlocking of the cycle of the request-confirmation end-stage pipeline execution 260. Skilled in the art it will be obvious that the exact location of this scheme is not of special importance, since all asynchronous control circuits are interconnected, and therefore blocked any cycle management request-confirmation will ultimately have the same result.

The scheme used in the preferred implementation for locking and unlocking cycle management request-confirm at the last stage of such components. Whenever a command is sent from the command pipeline 225 to the decoder commands 230, this command is compared with the 'Century' -command in the decoration of commands 230. 'Century' -command is a command for branching, and 'In'. command is the command branch, which branches to the current command (i.e., to itself). So at this point the program loops again, but serve a useful function, as long as the interrupt will not agitate cycle. 'Century' command is usually used to ensure that the microprocessor was in a state of readiness prior to receipt of the interrupt, which indicates that there is still forthcoming useful work. In the preferred implementation of this invention is 'Century' -use this command to stop all activity in the processor.

When the detection of the 'Century' command decoder commands 230 it forms the "stop" signal which is sent through the line 235 to the pipeline control 240, and from there sent to the pipeline execution 260, along with many other control signals that are used to control other aspects of the functionality of the pipeline execution, for example the control signals that tell arithmetical-logical unit (ALU) in the pipeline execution about Kaku is 0 and the output register 520, fixing respectively the input operands and output data. Cycle management form the request signal 510, which must be subjected to delay 511 enough time for data processing functions at this stage, and the confirmation signal 530; these signals are associated with the registers 500 and 520 to form the complete management cycle. The control cycle can be interrupted by valve And 560, which, if the output signal of gate AND NOT 550 is a logical 0 will not allow to pass to the request signal.

The valve AND NOT 550 receives four input signals, namely the "stop" signal 551 generated by the decoder commands 230, the signal interrupt request (irq) 552, the signal of the fast interrupt request (fiq) 553 and the signal of execution 554, which is formed by a conveyor performance and confirms that the command 'Century' really need to do. The signal of execution used in the preferred embodiments of the reason that, for example, the execution of the 'Century' command may depend on the result of the preceding command. In this case, the signal of execution will be issued to the pipeline execution, if the result of the preceding command, specified as 'Century' is the command that you want to process. Or predshestvuyuschei the filling up will be respectively set to "inactive".

The valve AND NOT the 550 will have an output signal of logic About when not to act two sources of interrupts 'irq' 552 and 'fiq' 553 (when a logical unit, because they are "low" signals), a stopping signal 551 will be active (logic 1), and the signal of execution 554 will be location in which you want to perform roadside diagram of preferred embodiments of the present invention.

Skilled in the art it will be obvious that the synchronization of the input signals 551, 552, 553 and 554 in the valve AND NOT 550 is essential for the proper functioning of the scheme. The signal of execution 554 reliable, because it is formed in place, and ensure proper synchronization delay 511. Delay 511 delay line request to have the time to determine the results of the preceding command to the following: whether the signal of execution to be valid or not; and to generate an appropriate signal performance. Stopping signal 551 is formed in the decoder commands 230, and proper synchronization provide pipelining control 240, which uses a known method of synchronization for safe guiding values which must be able to unlock the control scheme even when all control circuits in the system is blocked due to the performance of the 'Century'. Therefore, the interrupt sources must be directly connected to the tire 552 and 553. This interrupt signals must never make the transition from the current (logical value 0) at the inactive level (logical value 1) when a stop signal 551 is still applicable, in order to avoid incorrect behavior of the circuit. But the devices that generate interrupts, usually performed so that they did not cause the interrupt as long as the processor will not give them this command; and such elimination of the interrupt signal is under the control of software. Therefore, the above limitations can be observed in a simple way, through appropriate programming techniques.

By applying the above technical solutions to stop the pipeline execution 260. Then the pipeline execution of subsequent commands are not performed and thus the conveyor control is populated. After the pipeline control 240 is full, the decoder 230 is stopped, as he can no longer send the decoded commands to the pipeline control, and with the time with this address interface 200 may fetch commands just before this time, because the pipeline execution 225 or conveyor SC 280 are filled. As mentioned above, the pipeline execution 225 will be filled for the reason that the decoder commands 230 will no longer be read commands from the conveyor 225. Therefore, it is clear that stopping the pipeline execution 260, ultimately, will determine the termination of the operation of the microprocessor.

Using 'In'. command that already exists in most sets of commands of the microprocessor, there is no need for a new team and you can ensure compatibility of software with the majority of available codes. Skilled in the art it will be obvious that the lock and release cycles control of asynchronous control circuits can be applied to other solutions, and the use of 'In'. command is not essential.

The above has been described a specific embodiment of the invention, but it should be understood that the invention is not limited to them, and the range of the disclosure this invention also includes many changes and additions to it.

1. A processing unit that contains a lot of asynchronous control circuits, each asynchronous control scheme the COI management and is configured to exchange data signals, at least one other scheme from a specified set of asynchronous control circuits, and the first scheme of many of these asynchronous control circuits includes a stopping circuit for blocking the control signal in the cycle control first asynchronous control circuit, thereby preventing the exchange of data signals with the specified at least one other scheme from a specified set of asynchronous control circuits, resulting in control cycles of a specified set of asynchronous control circuits are blocked.

2. The device under item 1, in which the stopping circuit is configured to block the request signal generated by the control cycle of the request-confirmation.

3. The device under item 1 or 2, wherein the first asynchronous control circuit is configured to execute commands, and the device also includes a comparison circuit for comparing subject performance teams with a predetermined command, indicating that the control cycle of the first asynchronous control circuit should be blocked.

4. The device according to p. 3, also contains a decoder commands, and the comparison circuit is contained in the decoder commands.

5. The mouth is her command.

6. Device according to any one of paragraphs. 3-5, in which the stopping circuit includes a first logic circuit having inputs for receiving one or more interrupt signal and a stopping signal generated by the comparison circuit indicates that subject to the execution of the command is consistent with the predetermined command.

7. The device according to p. 6, in which the first logic circuit also includes an input for receiving the signal of execution, which is used to confirm that the control signal in the cycle control first asynchronous control circuit to block.

8. The device under item 6 or 7, in which the first logic circuit is a gate AND IS NOT made with the possibility of deducing the value of a logical 0 when all inputs are set to logic 1, and one or more interrupt signal is set to logic 1 when it is inactive, while the other input signals are set to logic 1, when they are active.

9. Device according to any one of paragraphs. 6-8, in which the stopping circuit also includes a second logic circuit having inputs for receiving the request signal cycle management request-confirm and exit the pen.

10. The device under item 9, in which the second logic circuit is a gate And is configured to not output the request signal when the output signal of the first logic circuit is set to a logical 0.

11. Device according to any one of paragraphs. 1-10, in which the interrupt signal is used to unlock the control signal is blocked by the stopping circuit, resulting in the possibility of exchanging data signals between the control circuits and thereby cause the unlocking control cycles.

12. Device according to any one of paragraphs. 1-11, in which the cycles of the control request-confirm using the communication Protocol level signaling.

13. Device according to any one of paragraphs. 1-12, in which many of asynchronous control circuits contains a set of interacting asynchronous pipelined circuits.

14. The microprocessor contains a device according to any one of paragraphs. 1-13.

15. The way data is processed in the processing unit, according to which use many used for data processing of asynchronous control circuits of the control cycle request-confirm to control the flow of data in each asynchronous who's with, at least one other scheme from a specified set of asynchronous control circuits of block control signal in the cycle of the first control scheme from a specified set of asynchronous control circuits, in response to compliance with predetermined conditions, resulting in preventing the exchange of data signals with the specified at least one other scheme from a specified set of asynchronous control circuits to block control cycles specified multiple asynchronous control circuits.

 

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FIELD: technology for blocking source registers in data processing device.

SUBSTANCE: device contains processor, having conveyer for executing a series of commands, a set of source registers for storing source data, requested by processor during execution of commands in series. Blocking mechanism is utilized for blocking source registers, depending on adjustable criterion. Processor works in two operation modes. In first operation mode, processor, after determining one or several extreme states during execution command, may execute process, external relatively to conveyer. In second mode processor finishes execution of command in conveyer even in case of detection of one or more extreme states.

EFFECT: increased efficiency of conveyer data processing.

2 cl, 20 dwg

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