Flags code conditions for data processing

 

(57) Abstract:

The invention relates to data processing systems. The technical result is to increase functionality by providing separate flags the status code for each of the individual parallel operations. A data processing system includes arithmetical-logical unit having N-bit information channel and supporting software command word for parallel operation. Independent arithmetic operations are performed arithmetical-logical unit in parallel with (N/2)-bit words of the input operands. There are two sets of flags code conditions N, Z, C, V, SN, SZ, SC, SV, responsive to a single arithmetic operation. The method describes the operation of this system. 2 s and 5 C.p. f-crystals, 7 ill., 60 table.

Document faxing (see graphic part).

1. A device for processing data, and the specified device contains a set of registers (10) for storing data words to be manipulated, each of these registers has a capacity of at least N bits, and arithmetical and logical unit (4) having N-bit information channel and responsive to mnimi command words, wherein said arithmetical-logical unit responds to at least one software command word for parallel operation, which separately performs the first arithmetical and logical operation on an information word of the first (N/2)-bit input operand and the second arithmetical and logical operation on an information word of the second (N/2)-bit input operand; and the specified arithmetical-logical unit sets the first set of code flags conditions (N, Z, C, V) depending on the specified first arithmetical and logical operations, and sets the second set of flags code conditions (SN, SZ, SC, SV) depending on the specified second arithmetical and logical operations, wherein the specified arithmetical-logical unit responds to the conditional command selection (SEL), which moves or information word of the first (N/2)-bit input operand stored in the register of the first source, or the information word of the first (N/2)-bit input operand stored in the register of the second source, in the destination register from the specified set of registers depending on the specified first set of flags conditions, and moves or information word of the second (N/2)-bit input operand, stored in the second register source to the specified destination register depending on the specified second set of flags conditions.

2. The device under item 1, in which the specified software command word for parallel operation determines the register source among a specified set of registers with the specified first (N/2)-bit input operand that is stored in the upper bit positions specified register source, and the second (N/2)-bit input operand stored in younger bit positions specified register of the source.

3. The device under item 1 or 2, wherein said arithmetical-logical unit includes a signal channel, which functions as a chain transfer between bit positions in arithmetical and logical operations, and the execution of a software command word for parallel operation of the specified signaling channel is torn between the specified information word of the first (N/2)-bit input operand and the specified information word of the second (N/2)-bit input operand.

4. Device according to any one of the preceding paragraphs in which the specified software command word for parallel operation performs one of the x (N/2)-bit addition; (ii) parallel subtraction, when running two parallel (N/2)-bit subtraction; (iii) parallel shift, when running two concurrent operations (N/2)-bit shift; (iv) parallel addition/subtraction, which are performed in parallel (N/2)-bit addition and (N/2)-bit subtraction; (v) the parallel determination of the minimum/maximum when running two parallel (N/2)-bit operations determine the minimum/maximum and (vi) parallel scaling when running two parallel (N/2)-bit scaling operations.

5. Device according to any one of the preceding paragraphs, wherein said first set of flags code conditions and the specified second set of code flags include at least one of the flags indicating that the immediately preceding operation (i) gave a result that was equal to zero (Z); (ii) gave a result that was negative (N); (iii) issued overflow (V) and (iv) issued the transfer (S).

6. Device according to any one of the preceding paragraphs, in which arithmetical-logical unit is adapted to perform one of the following operations: convolution, filtering operations, operations interviewer is sure of the word, subject to manipulation, in many registers, each of these registers has a capacity of at least N bits, and in response to a software command words performed by using arithmetical-logical unit having N-bit information channel, arithmetical and logical operations defined by the specified software command words, which in response to at least one software command word for parallel operation is carried out by the individual performing the first arithmetical and logical operations on information word of the first (N/2)-bit of the input operand and the second arithmetical and logical operations on information word of the second (N/2)-bit input operand, set the first set of flags code conditions depending on the specified first arithmetical and logical operations and establish a second set of flags code conditions depending on the specified second arithmetical and logical operations, wherein in response to the conditional command selection provide navigation or information words of the first (N/2)-bit input operand stored in the register of the first source, or the information words of the first (N/2)-bit input operand, KTI from the specified first set of flags code conditions and moving or information word of the second (N/2)-bit input operand, stored in the first source register or data word of the second (N/2)-bit input operand stored in the register of the second source to the specified destination register depending on the specified second set of flags code conditions.

 

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