# High-speed multiplying device for multiplying the digital signals periodic signals

(57) Abstract:

The invention relates to digital multipliers and is intended for multiplying the digital signal (CA) signal in the form of periodic waves, predominantly sinusoidal. The technical result consists in the simplification of the device. The device contains a digital oscillator with periodic phase varying sawtooth law, and uses the approximation of the samples of the function Ksin algebraic sums of values of a positive power of two for each value of the phase, and K is a coefficient, constant for all values of phase. The CA work on algebraic sum can be obtained quickly, simply and without the use of tables of sines. The decoder, which is phase f, determines the installed power of two, and the division carries out the multiplication of powers of two under the control of the decoder. One or two adder allows to receive the sums of powers of two. The result is an approximate value of works sin. Also presented the scheme of the receiver signal of the positioning satellite, using this multiplier device. 5 S. and 9 C.p. f-crystals, 5 Il., 3 that the l digital samples in the form of a periodic wave, predominantly sinusoidal.Although the following describes a specific application of the invention, the receivers detect signals from the satellites included in the system global satellite positioning system (GPS) or the global orbiting navigation satellite system (GLONASS), it should be emphasized that proposed in the present invention a method for rapid multiplication and multiplying device for its implementation can be used and in other cases when it is necessary to multiply the digital signal with digital samples of a periodic signal.Receivers GPS or GLONASS system are devices allows you to receive RF signals from many forming a constellation of satellites in earth orbit, and calculate using the above signals, the exact location of the receiver and, if necessary, its speed and absolute time.In the GPS or GLONASS RF signals have a carrier with a fixed frequency, phase modulated binary pseudo-random code and other digital data. The radiation level of the satellites is extremely low and pseudo-random code is used for a more EF is produce the correlation of the received signal, carrying a pseudo-random code with an identification code that is locally generated in the receiver.In the known receiver signal processing for realization of the specified correlation is fully digital, and the signal passed from the satellite locations are digitized with a preliminary adjustment of the carrier frequency to a value low enough that the specified digitization was possible. Next, produce a correlation.However, for correlation to take into account, on the one hand, you want the Doppler effect, and on the other hand, the duration of signal propagation in the atmosphere and the presence of a feedback circuit for phase and frequency. The specified path is part of the schema of digital signal processing.The frequency of the digitized signal may be further converted in the specified feedback circuit in a purely digital form, the signal (represented by uniform samples, encode multiple bits) Peremohy with envelope sine wave (digitized). In the result of multiplying receive the digital signal with the converted carrier carrying the original modulation pseudorandom code; this is the signal to be correlated with identichnosti links are directly enter the digital sine wave signal. To obtain use generator with digital phase control that generates a periodic digital phase f, changing according to the linear-sawtooth law in the interval from 0 to 2 radians.To convert the specified digital sawtooth signal into a sinusoidal signal is in principle possible to use a table of sines or cosines (in the General case it is advisable to have both so that the signal was presented in the quadrature phase). This table is formed by a permanent storage device, in which for each of its addresses or codes number of its cell contains exactly the sine (or cosine when using a table of cosines) of the digital values of the specified address. As the address, for example, 4 bits, is used, the phase of f, so that the memory, taking on input the address of f, converts it into sin.Digital sinusoidal signal sin then is multiplied by the known binary multiplier on the digitized signal from the satellite.This solution has physical boundaries, when the speed of the calculation results is increased. A multiplier device, as well as the ROM, is a factor slowing down. On the other hand, these circuit elements are costly, because random elements.In the present invention to avoid the above limitations, we propose a new method of multiplication and corresponding new multiplying device for multiplying the digital signal with the digitized envelope of a periodic wave.The invention is based on the fact that according to the above-described method, the result of the multiplication can be defined up to the K-factor: a valid order of multiplication is frequency conversion or modulation of a digital signal wave envelope; in this case, the multiplication can be performed with an accuracy of up to a factor, which is constant, within the required accuracy during sustained operations of multiplication.The proposed method involves using a digital phase f, varying sawtooth periodic law, and the specified phase is fed to the input of the decoder, which uses as a function of the decoding table N approximate integer values Ai of N integers Ksini/N, where i denotes the index from 0 to N-1 and K denotes a number that is identical for all indexes i, and approximate integers Ai are algebraic sums of one or more values of InEU wave is for each index i, the corresponding phase 2i/N, the multiplication signal CA for different values of powers of two, which form a number of Ai under the control of the decoder, and in the formation of the algebraic sums received as a result of such multiplication signals to obtain a digital value, which is the product of the CA on the approximate value of Ai. Algebraic sum of Ai include at least for some values of i a certain amount of several different values of powers of two.Multiplying the values of powers of two in front of the summation in fact, is to shift the digital signal from one or more of the weights and forth as they rise relative to the inputs of the adder, which ultimately carries out the summation, and the zero lower values of these weights. The inversion signal is in addition to the unit and the adding unit.Described in more detail below, the advantages offered by the invention method, however, even from the above description it is clear that this multiplication can be performed using a limited number of schemes, namely simple decoding scheme for the separation of signals and a small amount of the tion for implementing the method are also proposed scheme digital multiplication, designed for intermittent multiplying the digital values of CA on the envelope sine wave, characterized in that it contains:- block the formation of the digital periodic phase f, varying sawtooth law;

a decoder, receiving the phase f and resulting in compliance with all the values 2i/N phase f, where i is the index, which varies from 0 to N-1, one or more positive integer values of powers of two, marked with some sign of the algebraic sum of which is the number of Ai, representing an approximate value Ksin2i/N, where K is a constant for all values of Ai;

- division units managed by a decoder for admission to phase him 2i/N, for forming one or more signals ij, since the signal CA, and the signal Cij represents the signal CA is multiplied by one of the powers of two that has some character and is used in the amount of Ai;

the summation blocks are controlled by the decoder and configured to receive and sum the signals Cij received from blocks separation of the signals in the case when the decoder is phase 2i/N;

diagram, the output of which a signal is generated CSA, predstavlyayushie is.N is preferably equal to or greater than twelve, and, if the phase encoded binary code in R bits, then N is equal to 2

^{R}.At least some values of Ai is obtained by summation of several different powers of two.Is It mainly chosen small enough so that the number of values that are powers of two used in the adders included in the maximum of several units (for example, 3 or 4) and that the number of summirovanii made to determine phase was limited as much as possible to two or, exceptionally, up to three.The preferred value is equal To 13 or 8, if the phase encoded with 4 bits and contains N=2

^{4}samples in the period. Below is the resulting sum of the Ai. Is It preferable to choose equal to seven, if the phase takes 12 values for the period. In the limiting case for 12 samples per period K can be equal to 3 and in this case, as described below, the sinusoidal envelope of the wave is really coming to the triangular form.It is obvious that in a broader sense, the invention may find application by multiplying the digital signal to the envelope of the periodic wave F(f) non-sinusoidal shape. what La two detected values, approximating a function KF(f) simple algebraic sums of powers of two, using periodic phase f sawtooth waveform generated by the digital generator, with N samples phase F for the period.The greatest interest the invention is in the case when the number N of different phase values for the period is large and when the digital signal is encoded with more bits.Below the invention is illustrated by examples of its implementation with reference to the accompanying drawings, which depict:

in Fig.1 is a schematic diagram of a multiplication according to the invention;

in Fig.2 is a simplified example of implementation;

in Fig.3 is an embodiment of the circuit according to Fig.2;

in Fig.4 - generator sawtooth phase according to one of embodiments;

in Fig.5 - application of the multiplier in a digital feedback loop of the phase of the satellite signal receiver.First, a specific example describes the basic principle which is the basis for the creation of the proposed scheme.According to the invention using digital generator phase forming phase f, which changes periodically in accordance with the sawtooth law, and get a piece of the digital signal is always phase-coded R=4 bits; N= 2

^{4}= 16, i.e., when the sine wave is defined by 16 points in space /8. The phase in this case takes the values f = 2i/8, where i denotes the index varies from 1 to N-1.The invention is based on the following fact: you can make tables for each value of the phase of f, i.e., for each index i get an approximate value Ai value Ksin, so that the specified value of Ai can be described as a simple algebraic sum of powers of two. The number K is a constant for the entire table: it is to some extent determines the amplitude of the sine wave used for multiplication.If, for example, the selected K=8, you can create the following table for the phase values in the interval from 0 to /2 (the values of the other phases can be derived from the obtained values using classical trigonometric ratios, in particular with the use of inversion for phase 2.It is obvious that the multiplication signal CA to the value sin calculated value of f, it would be preferable to multiply the CA a sine wave sin using values Ai as approximate values. In this case, really is enough to have the opportunity to:

thus the number of or each other, either signal CA or CA.These operations are the simplest logical schema containing only one decoder, controlled digital phase f, several schemes of separation signals and one adder, and separation of signals and the adder are controlled by the decoder in the function from the phase at a particular point in time.Thus, at the output of the circuit receives a composite signal representing an approximate value of works sin, which is the approximate value of the product signal CA on envelope sine wave, where K represents the amplitude of the wave envelope.The errors shown in the last column of table 1 are based on estimates of expected accuracy. It should be noted that in any case the operation digitize sinusoidal wave on a limited number of samples (for example, 16 samples per period) makes accuracy much higher compared to the error arising from the conduct of the above-mentioned approximation, which indicates the possibility of free use of the specified approximation.You can easily install other acceptable values of K. In any case, the increase may privetera achieve an acceptable compromise between the wave form, close to sinusoidal, and a limited number of additional cascades is the value of K =13, and is constantly in the case of phase encoding 4 bits with N=2

^{4}samples. Table approximation by a sum of powers of two can be presented in table 2.In the previous example, the phase encoded in four bits. You can find the value of K, which allows approximation of the total values of the degree number two, if the phase encoded with a lower or higher number of bits, and similarly, if the phase-coded by the number of samples that are not powers of two.For example, if the phase takes N=12 values for the period, the digital oscillator phase generates a phase code representing the increment /6 and the decoder governing the separation of signals, and the adders configured to decode the codes transmitted by the generator. In this case, while approximately 3 receive the triangular approximation of a sine wave 3sin. The error can reach 15%. However, if It is equal to 7 for phase encoded in 12 bits, the approximation of sums As may be presented in table 3.In this table additionally contains a column before the data or any of the other options is easy.In Fig. 1 schematically shows the structure of the schema. The signal that is multiplied by the envelope sine wave phase f is the signal CA, coded, for example, 4 bits, one of which refers to the sign.Digital phase formed by the generator phase with digital control (MCC), the designated position 10. Used phase f is encoded in four bits. Below is described the structure of the generator used to change the digital frequency GPS receiver.The principle of construction of the generator is reduced to the following. It contains the memory register, the input to which is served in a digital form the value of the phase increment f, adder and generator of clock pulses with a fixed frequency Fc. Each quantum is added to increment the contents of the register, and the resulting value is entered in the memory. If the contents of the memory reaches a value corresponding 2 radian, the register is reset to zero. The register contains the instantaneous value of phase, oscillating linearly (and not the law of sine wave between 0 and 2. The output signal generator represents the contents of the register, changing on a periodic sawtooth law.Resolution is, however, most of the time phase, used to multiply the signal CA, can be encoded with fewer bits, in this example four. In this case it is enough to take 4 bits with high coefficients of generator output to the signal CA was multiplied by the envelope of a sine wave, diskretisierung the 16 cycles per period.The scheme depicted in Fig.1, includes a decoder 12, a receiving 4 bits of phase f, which controls the circuit 14 of the separation signals. The splitting of the signals fed a digital signal CA, which is encoded in this case, for example, four bits which must be multiplied by the envelope of a sine wave; however, this splitting can also take the opposite signal-CA, mainly in the case when the algebraic sum of AI contain negative values. Differentiation scheme produces signals depending on the state of the decoder 12 for a given phase Of one or more digital values ij, CSC,..., each of which is a product of the CA on the whole positive power of two, with a specific character.Multiplication CA or CA on 2j to obtain ij you can perform a simple division. In fact, it is SUP>2respectively, and the sign bit CA with a weight of 2

^{3}), the assignment of weights 2

^{j}, 2

^{j+1}, 2

^{j+2}three bits values, one weighting factor 2

^{j+3}sign bit and add lines j to 2

^{0}...2

^{j-1}.The scheme of separation of the signals is designed to perform the shifts of weight coefficients CA and additions bits with low weights to zero for establishing signals ij and CSC required to fetch the first phase.Adders SUM, SUM allow you to add pairs of signals ij, UCik,.. . according to the model sums Ai to obtain at the output S of the sum ij+ZSK+..., is equal to the product CSA, i.e., the required approximation CKsin.

In Fig. 2 presents a simplified example of execution, the corresponding approximation defined in table 2 (K=13).According Fig. 2 you must perform the following calculations depending on the sampling phase i:

i=0, f=0 setting 0 output circuits;

i=1, f = /8 - division CS

^{3}and CA at the inputs of the adder;

i=2, f = /4 - division CS

^{3}and CA at the inputs of the adder;

i=3, f = 3/8 - division CS

^{3}and CS

^{2}at the inputs of the adder;

i= 4, f = /2 - division CS

^{3}and CS

i=5, f = 5/8 - for (i=3;

i=6, f = 3/4 for i=2;

i=7, f = 7/8 - for i=1;

i=8, f = - for (i=0;

i= 9 to 1=12 for i=l to i=4, respectively, but with the result that the opposite is received, or using the opposite (-CA) is a CA;

i=13, f = 13/9 - for i=11;

i=14, f = 7/4 for i=10;

i=15, f = 15/8 - for i=9.Two adder SUM, SUM necessary due to the fact that the phase /2 and -/2 the addition shall be three members.The decoder 12 receives four bits determine phase F. Phase generator in this case is not presented. The decoder has four outputs D1, D4, D8, representing respectively the multiplication instructions CA 1, 4, 8, and exit signs SGN intended for these multiplications as a function of phase. Full decoding table shown in Fig.2 and corresponds to the approximation defined by this table. Output D8-1 indicates the necessity of multiplying by 4; output D4-1 indicates the necessity of multiplying by 4; output D1-1 indicates the necessity of using pomnojennogo signal CA and, finally, the output SGN-1 indicates the need for inversion of the resulting signal.Scheme 14 the separation of the signals contains only three groups of logic circuits "And". Each group made in the form of one is allowing you to either skip, or you can delay the signal CAS in accordance with the logic level present at the control input.The first circuit is controlled by the signal D8 and if D8 is equal to 1, produces a signal CA at the first input E1 of the first adder SUM with a simultaneous shift of 3 bits of the weighting values of the CA to implement multiplication by 8: weights of the values of CA are served to the inputs of the adder with weighting factors 3-6, with inputs with weights 0-2 are set to zero. If D8 is equal to 0 at the input E1 is fed 0. Under these conditions, you can take that to the specified first circuit serves either 0 (for sampling phase 0, 1, 7, 8, 9, 15), or is cs (for samples 2, 3, 4, 5, 6, 10, 11, 12, 13, 14).The second circuit is controlled by D4 and D4 is equal to 1, produces a signal CA with weights 2-5 (multiply by 4) the second input E2 of the adder SUM. Input signals with weights 0 and 1 are set to zero. Inputs weights 6 is assigned to the sign bit signal CA (the sign bit is received at the input weights 5). At the input E2 is 0, if D4 is 0.The adder SUM produces either CS, if D4=1 and D8=0, or CS if D8= 1 and D4=0, or CS+CS and, therefore, CS if D4 and D8 is equal to 1, or, finally, 0, ESM.The third scheme is controlled by the signal D1 and generates a signal CA, if D1= 1, or 0, if D1 is equal to zero. The output signal of the scheme is supplied to the second input E4 of the adder SUM, and the weights correspond to the number of CAS weights 0-3 specified input that corresponds to no multiplication CA. The sign bit (weighting factor 3) signal CA re-copied to weight the inputs 4-6.At the output of the adder SUM receive either 0 or CA, or CS or CS or CS or CS depending on the decode tables.The sign bit SGN decoder 12 (sign 0 for phase 0-7/8, mark 1 for the other phases) is assigned to the schema changes sign, which receives the signal from the output of the adder SUM. This scheme changes the sign contains the logical schema additions to the unit circuit EXCLUSIVE OR, following the scheme of incrementor that adds a set of weighting coefficients from the lowest level to the magnitude of the output signal of the XOR circuit. The output signal S of incrementor provides approximation sin, in this case, 8 bits, one bit for the sign.In this simplified embodiment, there are three schemes split the signal two sue and addition of signals can be performed using a single adder and additional circuits. In Fig.3 shows an example of executing with a single adder, which contains from two to five inputs, instead of from two to seven according to Fig.2, and which allows to carry out the same functions as scheme And two adder according to Fig.2, since the outputs D1, D4, D8 decoder 12.The example of execution according to Fig.3 are only intended to show the possibility of using different options perform the same function.According to some variants of execution, one example of which is the receiver of the satellite signals, the phase f is not allocated directly from the output signals with high weights digital phase generator. However, in order to obtain arbitrarily noisy phase noise lower bit weighting coefficients lowest level to be used in the multiplication signal CA, summarize the total output signal generator with a pseudo-random phase noise. The introduction of this noise is intended to exclude spurious periodic components of the signal spectrum sin arising from restrictions phase 4 bits in the circuit of Fig.1. In the case of a receiver of satellite signals specified components of the signal spectrum can stat/P> Thus, in a typical case, if the generator provides a phase in 16 bits, it adds a little noise in 12 bits to obtain the noisy phase, which limit using only four bits of high weight. The spectrum of the signal Ksin at the output of the multiplier does not contain more restrictive spurious spectrum.The structure of the generator 10 used in the circuit of Fig.1, shown in Fig. 4. The control generator MCC 18 includes a clock input with a frequency Fc and a digital control input frequency and phase. This input determines the phase increment added at the outputs of each quantum. 16-bit output signal generator MCC are added in the adder 20 to 12 bits of noise generated by a pseudorandom sequence generator. 12-bit noise applied with corresponding weight factors to the 12 bits of the weighting coefficients of the low level of the adder. The generator 22 noise can be, for example, a generator capable of generating a pseudorandom sequence of length

i=5, f = 5/8 - for (i=3;

i=6, f = 3/4 for i=2;

i=7, f = 7/8 - for i=1;

i=8, f = - for (i=0;

i= 9 to 1=12 for i=l to i=4, respectively, but with the result that the opposite is received, or using the opposite (-CA) is a CA;

i=13, f = 13/9 - for i=11;

i=14, f = 7/4 for i=10;

i=15, f = 15/8 - for i=9.Two adder SUM, SUM necessary due to the fact that the phase /2 and -/2 the addition shall be three members.The decoder 12 receives four bits determine phase F. Phase generator in this case is not presented. The decoder has four outputs D1, D4, D8, representing respectively the multiplication instructions CA 1, 4, 8, and exit signs SGN intended for these multiplications as a function of phase. Full decoding table shown in Fig.2 and corresponds to the approximation defined by this table. Output D8-1 indicates the necessity of multiplying by 4; output D4-1 indicates the necessity of multiplying by 4; output D1-1 indicates the necessity of using pomnojennogo signal CA and, finally, the output SGN-1 indicates the need for inversion of the resulting signal.Scheme 14 the separation of the signals contains only three groups of logic circuits "And". Each group made in the form of one is allowing you to either skip, or you can delay the signal CAS in accordance with the logic level present at the control input.The first circuit is controlled by the signal D8 and if D8 is equal to 1, produces a signal CA at the first input E1 of the first adder SUM with a simultaneous shift of 3 bits of the weighting values of the CA to implement multiplication by 8: weights of the values of CA are served to the inputs of the adder with weighting factors 3-6, with inputs with weights 0-2 are set to zero. If D8 is equal to 0 at the input E1 is fed 0. Under these conditions, you can take that to the specified first circuit serves either 0 (for sampling phase 0, 1, 7, 8, 9, 15), or is cs (for samples 2, 3, 4, 5, 6, 10, 11, 12, 13, 14).The second circuit is controlled by D4 and D4 is equal to 1, produces a signal CA with weights 2-5 (multiply by 4) the second input E2 of the adder SUM. Input signals with weights 0 and 1 are set to zero. Inputs weights 6 is assigned to the sign bit signal CA (the sign bit is received at the input weights 5). At the input E2 is 0, if D4 is 0.The adder SUM produces either CS, if D4=1 and D8=0, or CS if D8= 1 and D4=0, or CS+CS and, therefore, CS if D4 and D8 is equal to 1, or, finally, 0, ESM.The third scheme is controlled by the signal D1 and generates a signal CA, if D1= 1, or 0, if D1 is equal to zero. The output signal of the scheme is supplied to the second input E4 of the adder SUM, and the weights correspond to the number of CAS weights 0-3 specified input that corresponds to no multiplication CA. The sign bit (weighting factor 3) signal CA re-copied to weight the inputs 4-6.At the output of the adder SUM receive either 0 or CA, or CS or CS or CS or CS depending on the decode tables.The sign bit SGN decoder 12 (sign 0 for phase 0-7/8, mark 1 for the other phases) is assigned to the schema changes sign, which receives the signal from the output of the adder SUM. This scheme changes the sign contains the logical schema additions to the unit circuit EXCLUSIVE OR, following the scheme of incrementor that adds a set of weighting coefficients from the lowest level to the magnitude of the output signal of the XOR circuit. The output signal S of incrementor provides approximation sin, in this case, 8 bits, one bit for the sign.In this simplified embodiment, there are three schemes split the signal two sue and addition of signals can be performed using a single adder and additional circuits. In Fig.3 shows an example of executing with a single adder, which contains from two to five inputs, instead of from two to seven according to Fig.2, and which allows to carry out the same functions as scheme And two adder according to Fig.2, since the outputs D1, D4, D8 decoder 12.The example of execution according to Fig.3 are only intended to show the possibility of using different options perform the same function.According to some variants of execution, one example of which is the receiver of the satellite signals, the phase f is not allocated directly from the output signals with high weights digital phase generator. However, in order to obtain arbitrarily noisy phase noise lower bit weighting coefficients lowest level to be used in the multiplication signal CA, summarize the total output signal generator with a pseudo-random phase noise. The introduction of this noise is intended to exclude spurious periodic components of the signal spectrum sin arising from restrictions phase 4 bits in the circuit of Fig.1. In the case of a receiver of satellite signals specified components of the signal spectrum can stat/P> Thus, in a typical case, if the generator provides a phase in 16 bits, it adds a little noise in 12 bits to obtain the noisy phase, which limit using only four bits of high weight. The spectrum of the signal Ksin at the output of the multiplier does not contain more restrictive spurious spectrum.The structure of the generator 10 used in the circuit of Fig.1, shown in Fig. 4. The control generator MCC 18 includes a clock input with a frequency Fc and a digital control input frequency and phase. This input determines the phase increment added at the outputs of each quantum. 16-bit output signal generator MCC are added in the adder 20 to 12 bits of noise generated by a pseudorandom sequence generator. 12-bit noise applied with corresponding weight factors to the 12 bits of the weighting coefficients of the low level of the adder. The generator 22 noise can be, for example, a generator capable of generating a pseudorandom sequence of length

^{20}bit.The output signal of the adder is limited to 4 bits high-level weighting coefficients to provide phase F.In Fig. 5 shows the use of the IU GLONASS.The receiver includes an antenna 30 for receiving RF signals sequentially enabled circuit 32 amplification and frequency conversion, and then analog-to-digital Converter (ADC) 34. The output signal from the ADC is a digital signal representing a sample carrier (with the frequency converted, for example, 20 MHz), phase modulated pseudo-random code with the transition frequency of 1.023 MHz and a duration of 1 millisecond.The digitized signal is fed to a digital processing circuit that contains multiple identical parallel channels for receiving signals simultaneously from several satellites. In Fig.5 presents one channel.To separate the carrier from the baseband component to produce a digitized frequency subject to digitization of the signal CA. This conversion is made by multiplying the digitized signal CA, a sine wave with a frequency equal to the frequency converted carrier.This multiplication operation is performed in accordance with the above explanations, i.e., by forming the phase f and the multiplication signal CA to the amount of Ai powers of two approximate values Ksin.In General zelasko on Ksin (multiplier 36), but also s (multiplier 38). Obviously, the implementation of the multiplication circuit on s simultaneously flows from the implementation of the multiplication circuit on sin.The signals from the output circuits of sine and cosine, which include modulation of the initial phase, but with the frequency converted to the result of the multiplication, served on the correlator 40, whose function is to indicate the degree of synchronization between the pseudo-random code contained in these schemes sine and cosine, and pseudo-random code generated locally by the local code generator 42. The local code generated by the generator, identical to the expected code of the satellite.The frequency of the sine wave is the frequency, theoretically corresponding to the magnitude of the frequency converted carrier digital signal CA. Phase f of this wave is generated by phase generator 44 shown in Fig.4. The specified generator is used to synchronize the frequency and phase corresponding to the frequency and phase of the converted carrier adopted from the satellite. This allows you to account for signal applied to the correlator, all the frequency shifts caused, for example, Doppler effect, between theoretical value of the frequency signal received from the satellite, and the real is the Ummah of the control signal frequency and signal phase error and carrier frequency, and the resulting calculation (computational scheme 46) on the basis of signals from the correlator 40.Simultaneously, the generator 42 of the code of the local pseudo-random code is controlled by the generator, the frequency and phase of which are controlled digitally, depending on the results of calculations made on the basis of the output of the correlator 40, to synchronize the local code received by the code.The feedback signals generated by the computing circuit 46, and the modes of the generator 42 and code generator 44 phase are used as data to determine the location of the receiver.Thus, the above described exemplary embodiment of the circuit according to the invention. 1. The method of multiplying the digital signal CA on envelope sine wave using digital phase f, periodically changing in accordance with the sawtooth law, characterized in that the specified digital phase fed to the input of the decoder (12), using as a function of the decoding table N integer approximate values Ai of N integers Ksin2i/N, where i is an index from 0 to N-1, and K is some constant for all indexes i, when this approximate integers Ai are whole positive power of two or the algebraic sum of several positive integer powers of two is the first number two; the signal CA for each index i, the corresponding phase 2i/N, multiplied by different values of powers of two, the number of components Ai, under the control of the decoder; produce the algebraic summation multiplied thus signals to obtain a digital value, which is the product of the CA on the approximate value of Ai.2. The method according to p. 1, characterized in that the multiplication by powers of two is made with the help of the device (14) separate signal controlled by a decoder (12).3. The method according to p. 1, characterized in that the decoding function uses the following values Ai, where i denotes the index from 0 to 15: A0= 0; A1= 4+1; A2= 8+1; A3= 8+4; A4= 8+4+1, and the value of A5-A8 correspond to the values A3-A0 and the value of A9-A15 respectively opposite values A1-A7.4. The method according to p. 1, characterized in that the decoding function uses the following values Ai, where i denotes the index from 0 to 15: A0= 0; A1= 2+1; A2= 4+2; A3= 8-1; A4= 8, the values of A5-A8 coincide with the values of A3-A0, respectively, and the values of A9-A15 opposite values A1 to A7, respectively.5. The method according to p. 1, characterized in that the decoding function uses the following values Ai, where i denotes the index, izmenami A2-A0, but the A7-A11 opposite values A1-A5, respectively.6. The method of multiplying the digital signal CA on the envelope of a periodic wave F(f) using a digital phase f, which changes periodically in accordance with the sawtooth law and receiving sequentially the values F during the period, where i is the index, which varies from 0 to N-1, where N corresponds to the number of samples phase used during the period, wherein the specified digital phase fed to the input of the decoder (12), using as a function of the decoding table of N integers approximate values Ai of N integers KF(F), where K denotes a constant for all values of index i, with the whole approximate values Ai are whole positive power of two or the algebraic sum of several positive integer powers of two, fitted with a sign, and at least some of the values Ai are the sums of several different powers of two; signal CA for each index i, the corresponding phase F, multiplied by different powers of two, forming a number of Ai under the control of the decoder; and algebraically sum obtained by multiplying the signals to obtain digital C is I for periodic multiplying the digital values of CA on the envelope sine wave, characterized in that it includes a phase generator (10) digital control to generate digital periodic phase f, varying sawtooth law; decoder (12), receiving the phase f and resulting in a match for all values of 2i/N phase f, where i is the index, which varies from 0 to N-1, one or more positive integer powers of two, fitted with a sign of the algebraic sum of which is an approximate value Ksin2i/N, where K is a constant for all values of Ai, moreover, at least some of the values Ai are formed by the sum of several different powers of two; device (14) separation of the signals driven by the decoder when applying for them phase 2i/N, to generate one or more signals CA_{ij}on the basis of the signal CA, and the signal CA_{ij}is the product of the signal CA is one of the powers of two, fitted with a sign and used in the amount of Ai; block controlled by a decoder summation made with the possibility of receiving and combining signals CA_{ij}generated by the device separation of the signals received at a decoder phase 2i/N; however, this circuit has the output (S) on which a signal is generated CSA representing p is PP.8. The diagram on p. 7, characterized in that the device separation signals under the control of the decoder to produce the product of CA on powers of two, corresponding to the following amounts of Ai, where i is the index, which varies from 0 to 15: A0= 0; A1= 4+1; A2= 8+1; A3= 8+4; A4= 8+4+1, with values of A5-A8 are identical respectively to the values of A3-A0, and the values of A9-A15 opposite values A1 to A7, respectively.9. The diagram on p. 8, characterized in that it contains a first adder for obtaining the sum A0-A3; A5-A11; A13-A15 and part of each of the amounts of A4 and A12 and a second adder for receiving the balance amount A11 and the amount A12.10. The diagram on p. 7, characterized in that the device separation signals under the control of the decoder to produce the product of CA on powers of two, corresponding to the following values Ai, where i is the index, which varies from 0 to 15: A0= 0; A1= 2+1; A2= 4+2; A3= 8-1; A4= 8, the values of A5-A8 are identical respectively to the values of A4-A0, and the values of A9-A15 opposite respectively the values of A1-A7 and contain the summation blocks on a single adder.11. The diagram on p. 7, characterized in that the device separation signals under the control of the decoder to produce the product of CA on the degree of the number D4; A2= 6; A3= 7, and the magnitude of A4-A6 coincide respectively with the values A2-A0, and the value of A7-A11 opposite respectively the values of A1-A5 and contain the summation blocks on a single adder.12. The digital circuit multiplication for periodic multiplying the digital values of CA on the envelope of a periodic wave F(f) using a digital phase f, which changes periodically in accordance with the sawtooth law and receiving sequentially the values F for the period, where i is the index, which varies from 0 to N-1, where N denotes the number of samples phase used for the period, characterized in that it includes a phase generator (10) digital control for the formation of a periodic digital phase f, varying sawtooth law; decoder (12), receiving the phase f and resulting in a match for all values Of phase F. the amount of Ai one or more positive integer powers of two, fitted with a sign, where i is the index, which varies from 0 to N-1, with Ai corresponds to the approximate value of KF(F), where K is a constant for all values of Ai, and at least some of the values Ai are formed by the sum of several different powers of two; device (14) separation signal is SUB> on the basis of the signal CA, and the signal CA_{ij}is the signal CA is multiplied by one of the powers of two, fitted with a sign and used in the amount of Ai; the summation blocks are controlled by the decoder and configured to receive and store signals CA_{ij}produced by the device separation of the signals received at a decoder phase F, while this circuit has the output (S) on which a signal is generated CSA, which is the product of the signal envelope of the wave, the value of which is close to the envelope of a periodic wave(f).13. The receiver signal of the positioning satellite, comprising loop digital feedback, the receiving signal CA from satellite, converted in frequency into digital form, and the feedback circuit generates the phase error signal to adjust the local phase value of f on the phase of the satellite signal, the signal phase error obtained from the calculation of at least one result in the form Csin, wherein the feedback circuit includes a multiplier circuit according to one of paragraphs. 7-11, the receiving signal CA and issuing the sin, and where the control signal of the phase generator digital control for the formation of the.14. The receiver signal of the positioning satellite by p. 13, characterized in that it further comprises a summation block with pseudo-random noise included in the output of the phase generator digital control, and the feed block at the decoder output only bits high-level weighting phase, the resulting summation.

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1 dwg