Device for frame synchronization

 

(57) Abstract:

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal. Device for frame synchronization includes the decoder, detector, generating equipment, environment device and the storage device, the distributor specifying the device, the two devices match, three trigger inverter, the four elements And three elements OR. Device for frame synchronization allows you to extend the functionality of the device by synchronizing the various transmission information with asynchronous merging of digital streams, to reduce the search time synchronism with a significant reduction equipment, which is the technical result achieved in its implementation. 3 Il.

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal.

A device for frame synchronization [1], containing the detector clock analyzer coincidence of timing, input devices, bloemen And element OR register connected in a certain way.

This device reduces the time of entering into synchronism due to the additional register. However, this device has several disadvantages:

- increase search time of synchronism, especially when sequential search, when the distortion of the characters synchronously;

- large enough hardware costs through the use of input registers, as the cycle length can reach several thousand bits, leads to an increase in the input bit register to that value;

unstable operation of the analyzer matches, as if changing atmospheric conditions (temperature, humidity) parameters of the capacitor, resistor and diode can vary widely, and different intervals between the positions of synchronously in digital communication systems require for each case, selection of the parameters of capacitance and resistors.

The closest to the technical nature of the claimed invention is selected as a prototype receiver clock [2], containing the detector, consisting of a shift register and decoder, the holding device synchronism, consisting of the first device, generator equipment, items I1, I3, NOT1, OR1, device matching, consisting of the drive input in synchronism, the device forming weight coefficients K2, frequency divider, trigger and elements S2, S4, NET, ILI, the block selection clock frequency and channel distributor, United in a certain way.

The disadvantages of this device are:

- the impossibility of one and the same receiver to perform cyclic synchronization of a wide class of digital transmission of information;

- increase search time of synchronism when the distortion of synchronously associated with the distortion of the characters in a linear path;

- increase of hardware cost due to the use of the shift register with a large number of bits frame synchronization of the various transmission information;

- complication of the device by applying for phasing two rather complicated devices search and retention of synchronism, which also leads to an increase in the equipment.

Incremental searches distortion of synchronously at the initial stage of the search matching leads to the doubling time of detection of the first synchronously, and when the distortion of the N-ruutelem search first synchronously in the absence of distortion is:

t(n/2)2,

where t is the duration of the transmission cycle information;

n is the number of positions in the loop.

An object of the invention is enhanced functionality, allowing synchronization of the various transmission information with asynchronous merging of digital streams, reducing search time of synchronism and reducing equipment.

This task is solved in that the device for frame synchronization, containing the decoder, detector, environment unit (FU) and generating equipment (TH), and clock input devices for frame synchronization (CA) is connected to the corresponding inputs of the decoder, detector and TH, and the information input device for the CA is connected with the corresponding input of the decoder, the output response of the detector is connected with the respective input FU, the zero output state of which is connected to the respective input, output availability synchronization FU is the output device for the CA, address 1 - N outputs TH are the corresponding outputs of the device for the CA entered a storage device (memory), the distributor specifying the device, the first and second device matches the first, velemeny OR and address 1 - N inputs ZU connected with the corresponding outputs, the output position of the end of the cycle the memory is connected with the corresponding input and an output device for the CA, the outputs values of synchronously and position of synchronously memory connected to respective inputs of the decoder, the output position of the end of synchronously ZU connected with the respective input of the distributor, a clock input connected to a clock input of the device for the CA, the clock inputs of the second and third triggers are connected with a clock input devices for the CA, the output of the decoder is connected to the second input of the first element OR the second inputs of the first, second and third elements, And and with the fourth inputs of the fourth and fifth elements And the input resolution of the detector is connected to the output of the third element OR the first output and the third output of the distributor are connected to the corresponding inputs of the detector, the second output of the distributor is connected to the corresponding inputs of the detector, and FU, as well as with the input set to zero second and third triggers, input set to the maximum state FU is connected to the output of the first device matches the input set to zero FU is connected to the output of the second STRAVAGANZA, the outputs of the criteria options input in synchronism 1 - 1,..., L - 1 setting device connected to the corresponding inputs of the first device matching, and outputs the criteria options exit synchronism 1 - 2,..., K - 2 setting device connected to the corresponding inputs of the second device matches the information input of the first flip-flop is connected to the power bus, the clock input of the first trigger is connected to the output of the zero state of the FU, the input set to zero the first flip-flop connected to the output of the second state FU, the output of the first flip-flop connected to the input of the inverter and the second inputs of the fourth and fifth elements, And the output of the inverter connected to the first input of the first element And whose output is connected to the first input of the third element OR the first input of the second element And is connected to the output mode setting 0 setting device, the output of the second element And is connected to a second input of the third element OR the output of the second trigger connected to the first input of the first element OR to the first input of the third element And the third input of the fourth element And the first input of the fourth element And is connected to the output mode setting 1 setting device, the output of the fourth element And connected with others who, the output of the third element And is connected to a second input of the second element OR the output of which is connected to the information input of the third trigger, the output of which is connected to the first input of the second item OR the third input of the fifth element And the first input of the fifth element And is connected to the output mode setting 2 setting device, the output of the fifth element And is connected to the fourth input of the third element OR.

The novelty of technical solutions is available in the claimed device new circuit elements: mass storage device, dispenser, setting device, the first and second device matches the first, second and third trigger inverter, the first, second, third, fourth and fifth elements And the first, second and third elements OR.

Thus, the invention meets the criterion of "novelty."

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional units known. However, their introduction into the device for frame synchronization with the above links gives it new properties. Introduced functional units interact in such a way that allow you to extend Hakim way the invention meets the criterion of "Inventive step", as it is for the expert is not obvious from the prior art.

The invention can be used in digital transmission systems higher-order Association with asynchronous digital stream.

Thus, the invention meets the criterion of "Industrial applicability".

In Fig.1 shows a structural electrical diagram of the device for frame synchronization, Fig.2 is an electrical diagram of the generating equipment of Fig.3 is an electrical diagram of the environment of the device.

Device for frame synchronization (CA) contains the storage device 1 (ZU), a decoder 2, a detector 3, the generating equipment 4 (TH), environment unit 5 (FU), the distributor 6, the setting device 7, the first and second device matches 8 and 9, the first, second and third triggers 10, 11 and 12, an inverter 13, the first, second, third, fourth and fifth elements 14, 15, 16, 17 and 18, first, second and third elements 19, 20 and 21, moreover, the clock input devices for the CA is connected to the corresponding inputs of the decoder 2, the detector 3 and TH, and the information input device for the CA is connected to soutetsu state which is connected with the corresponding input, the output of the availability of synchronization FU is the output device for the CA, address 1-N outputs TH are the corresponding outputs of the device for the CA, address 1 - N inputs ZU connected with the corresponding outputs, the output position of the end of the cycle the memory is connected with the corresponding input and an output device for the CA, the outputs values of synchronously and position of synchronously memory connected to respective inputs of the decoder 2, the output position of the end of synchronously ZU connected with the respective input of the distributor 6, a clock input connected to a clock input devices for CA the clock inputs of the second and third triggers 11 and 12 are connected with a clock input devices for the CA, the output of the decoder 2 is connected to the second input of the first element ILI, the second inputs of the first, second and third elements 14, 15 and 16, and with the fourth inputs of the fourth and fifth elements 17 and 18, the input resolution of the detector 3 is connected to the output of the third element ILI, the first output and the third output of the distributor 6 is connected to the corresponding inputs of the detector 3, the second output of the distributor 6 is connected to the corresponding inputs of the detector 3, and FU, and with the input set to zero second, trateg the I 8, the input set to zero FU is connected to the output of the second device matches 9, outputs 1 - m discharges FU connected to respective inputs of the first and second device matches 8 and 9, outputs, parameters, criteria input in synchronism 1 - 1,..., L - 1 setting device 7 is connected to the corresponding inputs of the first device matches 8, and the outputs of the criteria options exit synchronism 1 - 2,..., K - 2 setting device 7 is connected to the corresponding inputs of the second device matches 9, the information input of the first flip-flop 10 is connected to the power bus, the clock input of the first flip-flop 10 is connected to the output of the zero state of the FU, the input set to zero the first flip-flop connected to the output of the second state FU, the output of the first trigger TH is connected to the input of the inverter 13 and the second inputs of the fourth and fifth elements 17 and 18, the output of the inverter 13 is connected to the first input of the first element 14, the output of which is connected to the first input of the third element ILI, the first input of the second element 15 is connected to the output mode setting 0 setting device 7, the output of the second element 15 is connected to a second input of the third element ILI, the output of the second trigger 11 is connected to the first input of the first element ILI, the first is Dinan exit setup mode 1 setting device 7, the output of the fourth element 17 is connected to the third input of the third element ILI, the output of the first element ILI connected to the information input of the second trigger 11, the output of the third element 16 is connected to a second input of the second element ILI, the output of which is connected to the information input of the third trigger 12, the output of which is connected to the first input of the second element ILI and the third input of the fifth element I, the first input of the fifth element I is connected to the output mode setting 2 setting device 7, the output of the fifth element I connected to the fourth input of the third element ILI.

Generating equipment 4 (Fig.2) contains remover tact 22, consisting of flip-flops 23, 24, 25 and 26, inverters 27 and 28, the elements I and 30, item counter 31, and the input RS generator equipment (TH) connected respectively to the input To the trigger 23, the input D of which is connected to the Log. "1", the output of the trigger 23 is connected to the input D flip-flop 24 and the input of the inverter 27, the output of inverter 27 is connected to the inputs R of the trigger 24, 25 and 26, a clock input connected to the FIRST inputs To the trigger 24, 25, 26 and to the first input element I, the trigger output 24 connected to the input of a D flip-flop 25 and to the first input element I, the output of the trigger 25 is connected to the input D triggered element I, the output of which is connected to the input of the inverter 28, the output of which is connected with the second input element I, the output of which is connected with a clock input To the counter position 31, the input RES-C which is connected to the input of CC (input position of the end of the cycle), the address outputs 1 - N item counter 31 is connected with the corresponding outputs.

Environment unit 5 (Fig.3) contains inverters 32, 33, 34 and 35, the elements I, 37, 38 and 39, the elements ILI and 41, the trigger 42, and a reversible counter 43, the decoders 44, 45 and 46, and the input IC (input response opoznavatel) environment unit (FU) is connected to the input of the inverter 32, the first input element I and entrance +/- reversing counter 43, and the entrance RS (the signal input from the second input of the distributor) FU connected with the second inputs of the elements I, 37 and input To the trigger 42, the outputs of the inverters 32 and 33 are connected respectively with the first and third inputs of the element I, the output of inverter 34 is connected to the third input element I, the outputs of the elements I and 37 are connected respectively with the first and second inputs of the element ELI, the output of which is connected to the input To the reversible counter 43, the outputs of the digits 1-m reversible counter 43 is connected to the corresponding inputs of the decoders 44, 45 and 46 and are appropriate vyhodyaschim output FU, output DC2 (second state) of the decoder 45 is connected with the corresponding output FU, "m" (the maximum output state of the decoder 46 is connected to the input of the inverter 34 and the second input element ILI, the output of the trigger 42 is connected with the first inputs of the elements ILI and I, the second input element I connected to the input R (input set to zero) FU, the output element I connected to the inputs R reversible counter 43 and the trigger 42, the input of the D flip-flop 42 is connected to the output element ILI, the trigger output 42 is connected to the input of the inverter 35 and is output to the availability of synchronization FU, the output of the inverter 35 is connected to the first input element I, the second input is connected to the input S (input set to the maximum condition) FU, the output element E connected to the input S reversible counter 43.

Device for frame synchronization works as follows.

In the discharge of the storage device 1 in particular it addresses 1 - N in accordance with the structure of a digital information transmission stores the following parameters:

- CZ - position end loop;

- UCS - position synchronously;

- PCC - values synchronously;

- KSK - end positions of synchronously.

As saponi the ROM), the number of which is determined by the number of different digital transmission of information, either one programmable memory (EPROM). When frame synchronization of a wide class of digital transmission of information necessary to carry out reprogramming the EPROM on the relevant parameters of a particular transmission. The storage device 1 is structurally connected with the device for frame synchronization using sockets.

With the aim of choosing the optimal time search mode synchronization depending on the noise linear reception path using the setting device 7 are set to the following modes:

- search synchronism with undistorted noise of synchronously;

- search of synchronism when the distortion noise one bit of synchronously;

- search of synchronism when the distortion of the interference of two bits of synchronously.

When the distortion of the three bits of synchronously and more to perform its decoding is impractical, as in a digital signal, especially when the distortion of the interference will be desirious a large number of false singlecompany that will lead to a significant increase in search time of synchronism. Also poei under this criterion input in synchronism refers to the difference between the number of the decrypted synchronously and dadesiforum. When we achieve this by the difference between the setpoint device for frame synchronization is included in the mode matching and retention, as will be described below. Under criterion exit synchronism refers to the difference between the number dadesiforum and decrypted synchronously. When we achieve this by the difference between the setpoint device for frame synchronization goes out of synchronism and goes back to his search. Entrance criteria in synchronism and out of synchronism are also taking into account the noise linear path.

At the initial stage of the search of synchronism in the absence of the output IC (output response) of the detector 3 positive feedback about deciphering synchronously environment unit 5 (FU) is set in the zero state. The output signal from the zero state of the latter is fed to a corresponding input of generator equipment 4 (TH) and next to the entrance of his remover tact 22, allowing the work item I. Clock pulses from clock input T of the device for frame synchronization (CA) are fed to the corresponding input ON further inputs To the trigger 24, 25 and 26 remover tact 22 and through the element I to the clock input of counter positions 31. The signal is upominalsja device 1 (ZU), and to the outputs for the CA. The signal output from CC (output position of the end of the cycle) ZU through the corresponding input ON the input of RES - item counter 31, the last on the leading edge of the next clock pulse is set to the zero state (synchronous reset). The output signal from the CSC (the output end positions of synchronously) ZU went to a corresponding input of the distributor 6, performing the timing of this signal. The output signal RS (second output) of the distributor 6, coming through the appropriate entrance to the entrance To the trigger 23 remover tact 22, the trigger is set to one state, allowing through an inverter 27 to the operation of the trigger 24, 25 and 26. The output signal of the trigger 24 at the input of element I and then through an inverter 28 to the second input element I, are prohibited from passing through the last one clock pulse at the clock input of counter positions 31. The output signal from the trigger 26 remover tact 22 sets the trigger 23 to the zero state. Then the output signal of the low level of the Log. "0" trigger through the inverter 27 are set in the zero state other triggers 24, 25 and 26 remover beat 22. After this is about PKE decryption of synchronously, received from the output response of the detector 3 to the appropriate input FU, accompanied by a signal from the second output of the distributor 6, arriving at the appropriate entrance FU, the latest changes from "0" to "1". When this signal of negative polarity supplied from the output of the zero state FU to the appropriate input, in the latter prohibited the removal of the clock pulse. The search of synchronism starts to be carried out on the same positions of the digital signal.

Environment unit 5 operates as follows. Positive response to decipher synchronously output response of the detector 3 through the corresponding input environment of the device 5 (FU) is fed to the input +/- reversing counter 43 FU, allowing adding it to the unit. This positive response is supplied to the first input element I, allowing his work. The signal from the second output of the distributor, acting through the appropriate entrance FU and forth through the open element I and element ILI input To the reversible counter 43, increases its status on the unit. A negative response to decipher synchronously, acting on input +/- reversing counter 43, permits the reduction of its condition signal with the second output of the distributor, received on the corresponding input FU, reversible counter the latter reduces its state by one.

In the search mode matching trigger 42 FU is in the zero state. Its output signal through an inverter 35 allows for the first input work item I, thereby allowing the passing of the signal output from the device match 8 on the input set to the maximum state of the reversible counter 43 FU.

When reaching the reversible counter 43 state defined by the difference between the number of positive and negative feedback when deciphering synchronously and specified using the options criteria input in synchronism 1 - 1, ..., L - 1 setting device 7 is supplied to corresponding inputs of the device matches 8, other inputs 1,..., m which receives signals from the respective outputs of the reversible counter 43 through the respective outputs FU, a positive output signal from the output device matches 8, coming through the input set to the maximum state FU and forth through the open element I on the input set to the maximum state of the reversible counter 43, the latter following a signal from the second output distribution the local signal output from the maximum state of the decoder 46 through the element ILI fed to the input of a D flip-flop 42 and a negative edge signal from the second output of the distributor, received on the corresponding input FU, this trigger is set in one state, its output signal through an inverter 35 closing element I and opening the item I. Then FU goes into the hold and out of synchronism. The output signal of the trigger 42 is supplied to the output f (output availability synchronization) FU, who is also an output device for a CA to indicate the mode of the device.

On hold and search synchronism with the achievement of the reversible counter 43 FU state defined by the difference between the number of negative and positive responses to the comprehension of synchronously and maintained by signals from the outputs of the criteria options exit synchronism 1 and 2 . .., K - 2 setting device 7 is supplied to corresponding inputs of the device matches 9, to the other inputs of the digits 1 - m which receives signals from the corresponding FU, a positive output signal from the output device matches 9 input to the input set to zero FU and then through the element I, R is reversible counter 43 and to the input R of the trigger 42, the latter are set in the zero state, and a device for CA again translated in the search mode, the sync decoder 44 through the inverter 33 is prohibited work item I and therefore, it is prohibited signal on the clock input To the reversible counter 43 with a negative response. Thus prohibits the reversible transition of the counter from the zero state to the maximum state.

If reversible counter 43 is in the maximum state, the output signal from the decoder 46 through the inverter 34 is prohibited work item I and, therefore, prohibited the passage of the signal on the clock input To the reversible counter 43 with a positive response. Thereby forbidden transition is reversible counter 43 of the maximum state to the zero state.

Decoder 2 devices for the CA performs elementwise decoding the current values of synchronously digital signal, attitudes and values which are set in the memory and received from the output of the latter to the corresponding inputs of the decoder 2, the information and the clock input of which receives respectively the information and clock pulses from the respective inputs of the device for the CA.

The appearance of the output of the decoder 2 to the positions of synchronously signal unit level indicates an error of interpretation. When deciphering the true undistorted noise symbols is tel 3 works as follows. In the absence of the error decoding elements synchronously on the input of the EU (input resolution) of the detector 3 from the output of the third element ILI signal zero level, prohibiting the operation of the detector 3, and at its output response is held a single signal level that corresponds to positive response when deciphering synchronously. If there is an error decoding the symbols of synchronously to the input resolution of the detector 3 receives the signal of a single level. Then on a signal received from the first output of the distributor 6 to the corresponding input of the detector 3, the output response negative response to decoding synchronously. Signal is positive or negative response to the decoding of synchronously output response of the detector 3 and the signal from the second output of the distributor 6 is coming to corresponding inputs of a FU. After the sequential receipt of signals from the second and third outputs of the distributor 6 to the corresponding inputs of the detector 3 of the last set in one state, thus preparing the next cycle of operation.

Search mode synchronism with undistorted noise of synchronously is following the course of the second element, And 15, allowed the use of the latter. The fourth element 17 and the fifth element I closed zero signals at their first inputs respectively from outputs of modes 1 and 2 setting device 7. The first error signal when the decoding of the symbols of synchronously comes from the output of the decoder 2 via the open second element 15 and the third element ILI to the input resolution of the detector 3, while at its output response negative response. In the absence of the error signal at the output of the decoder 2 output response of the detector 3 is formed of a positive response, and a device for CA searches for matching, as mentioned previously.

The search mode of synchronism when the distortion noise one bit of synchronously as follows. Single output mode setting 1 setting device 7 is supplied to the first input of the fourth element 17, to the second input of this element receives a single signal output from the first flip-flop 10, the same signal is fed to the input of inverter 13. The zero output signal from the inverter 13 closes the first input of the first element 14. The second element 15 and the fifth element I closed by the zero level signals from outputs Osterby the trigger 10 is set in one state signal, arriving at its clock input from the output of the zero state of the FU. The first error signal when the decoding of the symbols of synchronously through the first element ILI is supplied to the information input of the second trigger 11. The next clock pulse received from the clock input devices for the CA to the clock input of the second trigger 11, the latter is set in one state and is held in this state by a single signal from its output to the information input through the first element ILI. A single output signal of the second trigger 11 is also fed to the third input of the fourth element 17, allowing his work. Now a second pulse of the error from the output of the decoder 2 via the fourth element 17 and the third element ILI is fed to the input resolution of the detector 3. Upon reaching FU state "2" output signal from the output of the second state DC2 first trigger 10 is set in the zero state, its output a zero signal prohibiting the fourth element 17 and the fifth element I and permitting through the inverter 13 of the first element 14. Now the signal of the first error decode symbols of synchronously comes from the output of the decoder 2 via the first element 14 and the third element ILI packageno synchronously. The second and third triggers 11 and 12 are set in the zero state signal received at their inputs setup to zero with the second output of the distributor 6. Thus, to achieve FU state "2" by the positive response to the output response of the detector 3 is formed as in the absence of the error decode symbols of synchronously, and with a single distortion of their interference.

The search mode of synchronism when the distortion of the interference of two bits of synchronously as follows. At the first input of the fifth element I served enable signal of a single level output mode setting 2 setting device 7. To the second input of this element is supplied enable signal of a single level from the output of the first flip-flop 10. On the first inputs of the second element 15 and the fourth element 17, respectively, with the output mode setting 0 1 setting device 7 receives a deny signal zero level. The first error signal decoding symbols of synchronously, as described earlier, sets the second trigger 11 in one state. The output signal of the second trigger 11, when the first input of the third element 16, enables the latter. The second error signal to decode the symbol information to the third input of the trigger 12, after the last clock pulse from clock input devices for the CA is set in one state, its output signal to the third input of the fifth element I, allowing the latter's work. Then upon receipt of the third error signal decoding symbols of synchronously through the fifth element I and the third element ILI to the input resolution of the detector 3, the latter at its output response generates a negative response. Further, the device operates as described earlier for the case of distortion interference of one symbol of synchronously. Thus, to achieve FU state "2" by the positive response to the output response of the IC detector 3 is formed as in the absence of the error decode symbols of synchronously and distortion of one or two bits.

For the technical realization of the device for frame synchronization uses persistent storage device (ROM) or programmable permanent memory (EPROM), and user-programmable logic integrated circuits (PPLIS).

The present invention allows to extend the functionality of the device for frame synchronization, the search time synchronism with a significant reduction equipment.

Sources of information

1. RF patent N 2019046, H 04 L 7/08.

2. Levin, L. S. , Plotkin, M. A. Digital communication system. M.: Radio and communication. S. 102-103. Fig.4.4.

Device for frame synchronization, containing the decoder, detector, environment unit (FU) and generating equipment (TH), and clock input devices for frame synchronization (CA) is connected to the corresponding inputs of the decoder, detector and TH, and the information input device for the CA is connected with the corresponding input of the decoder, the output response of the detector is connected with the respective input FU, the zero output state of which is connected to the respective input, output availability synchronization FU is the output device for the CA, address 1 - N outputs TH are the corresponding outputs of the device for the CA, characterized in that that introduced a storage device (memory), the distributor specifying the device, the first and the second device matches the first, second and third trigger inverter, the first, second, third, fourth and fifth elements, And first, second and third elements OR, with address 1-N inputs ZU connected with the corresponding outputs, the output position of the end of the cycle, a memory connected to the soo is recombinatio memory connected to respective inputs of the decoder, the output position of the end of synchronously ZU connected with the respective input of the distributor, a clock input connected to a clock input of the device for the CA, the clock inputs of the second and third triggers are connected with a clock input devices for the CA, the output of the decoder is connected to the second input of the first element OR the second inputs of the first, second and third elements And, fourth inputs of the fourth and fifth elements And the input resolution of the detector is connected to the output of the third element OR the first output and the third output of the distributor are connected to the corresponding inputs of the detector, the second output of the distributor is connected to the corresponding inputs of the detector, GO and FU, as well as with the input set to zero second and third triggers, input set to the maximum state FU is connected to the output of the first device matches the input set to zero FU is connected to the output of the second device matches the outputs of the 1-m discharges FU connected to respective inputs of the first and second devices is a match, outputs, parameters, criteria input in synchronism with a 1-1 . . . L-1 setting device connected to the corresponding inputs of the first device matching and output parameters Crete the device matches the information input of the first trigger is connected to the power bus, a clock input connected to the output of the zero state of the FU, the input set to zero the first flip-flop connected to the output of the second state FU, the output of the first flip-flop connected to the input of the inverter and the second inputs of the fourth and fifth elements And the output of the first inverter connected to the first input of the first element And whose output is connected to the first input of the third element OR the first input of the second element And is connected to the output mode setting 0 setting device, the output of the second element And is connected to a second input of the third element OR the output of the second trigger connected to the first input of the first element OR the first input of the third element And the third input of the fourth element And the first input of the fourth element And is connected to the output mode setting 1 setting device, the fourth output element And is connected to the third input of the third element OR the output of the first element OR connected to the information input of the second trigger, the output of the third element And is connected to a second input of the second element OR the output of which is connected to the information input of the third trigger, the output of which is connected to the first input of the second cell battery (included) the 2 setting device, the output of the fifth element And is connected to the fourth input of the third element OR.

 

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1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

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