Digital generator for digital tracking systems correlation signal processing

 

(57) Abstract:

The invention relates to electronics, and more specifically to digital generators designed for use in digital servo systems correlation signal processing, mainly of signals of satellite radio navigation systems or satellite systems. The technical result is reduced energy consumption. The device comprises a frequency register, two combinational adder and two register phase, performed low-rank and high sampling frequency, and the register code frequency, the adder and the register phase, completed high RES and working with low sampling frequency. 2 Il.

The invention relates to electronics, and more specifically to digital generators designed for use in digital servo systems correlation signal processing, mainly of signals of satellite navigation systems (SNS) or satellite communication systems (SCS).

Feature of digital correlation processing signals GPSr or CCC is that the selection of the information contained in the processed signal generated by closed figures is first compared the copy with the signal in the process of tracking the carrier and the delay signal, see, for example [1, S. 269-271, Fig.15.3], [2, part I, S. 82-85, Fig. 9. 10], [3, S. 24-31, Fig.1.14 - 1.21]. Typically, such digital servo systems contain solvers (digital processors, digital mixers, demodulators, drives, and managed computer digital generators (digital synthesizers), see, for example [4]. Managed computer digital generator that generates digital values of the phase of the reference oscillation used in digital servo systems correlation signal processing (mainly signals SNS or SNS), are considered in this application.

It is known the use of digital generators as generators of the carrier and clock frequency code in digital servo systems, performing correlation processing signals SRNS GPS (NAVSTAR") (USA) and GLONASS (Russia).

For example, in known integrated receiver signal GPSr [5] each channel digital correlator contains the managed digital carrier generator [5, Fig.4-5, block 30], which is an element of the digital servo system for carrier ("schema-tracking carrier"). The digital carrier generator generates a digital current values of the phase of the carrier frequency of the reference signal IP is atomnogo Converter, for "removing" the carrier and transfer the spectrum of the processed signal to the zero frequency at which subsequent operations are carried out demodulation and accumulation. The management of digital carrier generator is controlled by signals of the transmitter that is included with integrated receiver, in particular from the transmitter receives the data code carrier frequency. The data coming from the transmitter is converted into nakaplivaya the adder of the digital carrier generator according to a certain law and are stored in the output register, forming digital signals, determining the current values of the phase of the generated reference signal. In addition to the digital carrier generator in the integrated receiver signal GPSr [5] each channel digital correlator contains controlled digital oscillator clock frequency code (numeric code generator) [5, Fig.4-5, block 32] , which is an element of the digital servo system delay code (the"scheme tracking delay"). The digital code generator generates a digital current values of the phase of the reference clock signal C/a code (1.023 MHz for GPS and 0,511 MHz for GLONASS). The structure of the digital code generator is similar to the structure of the digital carrier generator.

The basis of resumator, managed computer. Using the calculator allows to realize high accuracy formation of the reference signals required for the operation of the digital tracking systems that allows, in particular, high-precision measurement of time delays and Doppler shifts the frequency of the received signals SRNS.

General principles of digital generators based on the accumulative adders known and widely represented in the sources.

For example, in [2, part I, S. 89-91, Fig.18] described the structural diagram of the digital signal generator (frequency synthesizer), used to generate the reference signal of the carrier frequency in the receiver signal SRNS "NAVSTAR". The basis of this digital generator is 21-bit accumulating adder, made in the form of series-connected 21-bit combinational adder, a first input which is the input code Doppler", and 21-bit memory register, working with sampling frequency fs = 5,115 MHz, the output of which is connected to a second input of the combinational adder. In this digital generator is implemented by a known method of direct digital synthesis frequency, based on the accumulation plyvushego adder performed controlled digital code generator of the receiver signals SRNS "NAVSTAR", described in [2, part II, S. 72-73, Fig.36].

Considered digital generators, made on the basis of accumulating adder and implement a method of direct digital synthesis frequency, form of digital current values of the phase reference signals. If necessary, on the basis of these digital signals, characterizing the current values of phase analog signal is formed, for example, using the code Converter according to "table of sines (cosines), and digital to analogue Converter.

Among digital generators designed for use in digital servo systems correlation processing signals that implement a method of direct digital synthesis, closest to the claimed digital generator in its execution is a digital generator presented in [6, 90-92 C., Fig.34], which is selected as a prototype.

Digital generator for digital tracking systems correlation processing of signals selected as a prototype, made in the form of cumulative module containing sequentially connected To the-bit register code frequency and accumulating adder, working with sampling frequency fs. Accumulating adder to perform the entrance is accumulating adder, and register-memory (register phase), the output bits of which is connected to the second input combinational adder. Information input code register frequency forms a control input, and the output bits of the register phase output digital generator, taken as a prototype.

Digital generator, selected as a prototype, generates at its output a digital signal representing the results of the savings of the current phase. These signals are used when performing correlation processing, for example, in schemes for tracking carrier" measuring the Doppler shift, or "schemas tracking delay, measuring the shift of the reference code regarding code of the processed signal [6, S. 87-90, Fig.33].

Digital generator, selected as a prototype that implements the method of direct digital synthesis frequency with the accumulation of the current phase. This is done as follows. The information input is accumulating adder, i.e., at the first input of which is included in its composition combinational adder output register code frequency receives the control signal in the form of a K-bit number N, which is proportional to the specified increment the current phase of each clock signal discretize the carrier" or "schema tracking delay". In nakaplivaya the adder to the second input of the combinational adder with frequency fs is supplied To the bit number that specifies the value of the current phase accumulated in the register phase of this cycle. The result of the sum of these numbers is sent back to the register phase. Thus, at the output of the accumulating adder with frequency fs generated current values of the phases that geometrically interpreted (in the coordinate system of the phase - time) speed line. The slope of this line determines the speed of the increment of the phase and thus the frequency of the synthesized signal. The slope of a line, and hence the frequency of the synthesized signal can be changed by changing the number N. This is very convenient for the exercise of direct control of the generator from the transmitter, for example, the formation of the Doppler frequency shift.

Requirements as to the number of bits (K) accumulating adder are set based on the desired value of the frequency setting (increment phase), determined by the specific terms of the correlation signal processing. Requirements for the sampling frequency (fs) are based on the spectrum of the processed signal. As practice shows, when the correlation signal processing CPA sampling) and simultaneously high RES (ten digits) accumulating adder. However, generators that use such high frequency and simultaneously accumulate high RES adders are characterized by a high level of energy consumption, which can be a problem, particularly for portable equipment operated from self-contained battery power.

Technical problem on which the invention is directed, is the creation of a digital generator, which implements the direct digital synthesis with the accumulation of the current phase, in which the specified conditions of use for digital tracking systems correlation processing of signals, types of signals GPSr (CAS) allows you to reduce power consumption.

The task is solved by the proposed changes to the structure of the digital generator, namely by using two cumulative modules - cumulative frequency module operating at a predetermined sampling frequency fs1and using this accumulating adder with reduced number of bits (for example, less than ten), and low-frequency module operating at a lower sampling rate and using the accumulating adder with the number of bits determined from the conditions which poisons). The required characteristic of the accumulation of the current phase of the synthesized signal is provided at this by summing up the phase values of both cumulative modules. The proposed structure is based on two cumulative modules - high-frequency low-rank and low-frequency high RES, allows you to declare the generator to reduce the power consumption compared to traditional generator framework, which uses one cumulative module - high-frequency and simultaneously high RES.

The invention consists in that in a digital generator for digital tracking systems correlation processing signals containing the first cumulative module, made in the form of serially connected register first code frequency information input which is the first managing digital input generator, and accumulating adder, working with sampling frequency fs1made in the form of series-connected combinational adder, a first input of which is an information input of this accumulating adder, and register phase, the output bits of which are connected in this accumu is ideal serially connected register of the second code frequency information the input of which forms the second control input of the digital signal generator, and accumulating adder, working with sampling frequency fs2= fs1/k, where k is an integer greater than one, made in the form of series-connected combinational adder, a first input of which is an information sign that is accumulating adder, and register phase, the output bits of which are connected in this nakaplivaya the adder to the second input combinational adder, the said elements of the first rollup module is made TO1-bit, as specified elements of the second cumulative module - K2-bit and2> K1in the digital generator also introduced a series-connected TO a1-bit output combinational adder and working with sampling frequency fs1register the total phase, the output bits of which forms a first output of the digital oscillator, the first input of the output combinational adder coupled to the output bits of the register phase accumulating the first cumulative adder module, and the second input - output K1high-order bits of the register phase accumulating summate which forms the second output of the digital generator.

The invention, its feasibility and the possibility of industrial application are explained shown in Fig.1 is a structural diagram of the inventive digital generator, as also shown in Fig.2 charts illustrating the processes of forming the phase values in the inventive generator.

The inventive digital generator for digital tracking systems correlation processing signals includes, see Fig 1, the first cumulative module 1 made in the form of serially connected register 2 of the first code frequency information input which is the first managing digital input generator, and accumulating adder 3 working with sampling frequency fs1made in the form of series-connected combinational adder 4, the first input by the information input is accumulating adder 3, and the register phase 5, the output bits of which are connected in nakaplivaya the adder 3 to the second input combinational adder 4.

The inventive digital generator also includes a second cumulative module 6 made in the form of serially connected register 7 of the second code frequency information input of which forms the second is UB>2made in the form of series-connected combinational adder 9, the first input by the information input is accumulating adder 8, and the register phase 10, the output bits of which are connected in nakaplivaya the adder 8 to the second input combinational adder 9.

The elements of the first cumulative module 1 (case 2 of the first code frequency, combinational adder 4, the register phase 5) is executed K1bit, and the elements of the second cumulative module 6 (register 7 of the second code frequency, combinational adder 9, the register phase 10)2-bit and2> K1. For example, when implementing a digital generator of the carrying values of K1and K2can be selected in relation TO a2= 25, K1= 5, and in case of implementation of the code generator is in the ratio2= 23. K1= 2.

The sampling frequency fs2associated with the sampling frequency fs1the expression fs2= fs1/k, where k is an integer greater than one. For example, for the case shown in Fig. 2, k = 6, for the case considered below example of estimation of power consumption k = 8.

Based on these razrjadnaja and sample rates for the first nakopitelny module 6 - as low frequency high RES module.

The inventive digital generator also includes a series-connected TO a1-bit output combinational adder 11 and the register total phase 12 working with sampling frequency fs1.

The first and second inputs of the output combinational adder 11 are connected respectively with the output of the K1bits of the register phase 5 is accumulating adder 3 of the first cumulative module 1 and K1high-order bits of the register phase 10 is accumulating adder 8 second cumulative module 6.

The output of the K1bits of the register total phase 12 forms a first output of the inventive digital generator, and the output M = K2- K1least significant bits of the register phase 10 is accumulating adder 8 second cumulative module 6 forms a second output of the inventive digital generator.

In the inventive digital generator, the first signal sampling frequency fs1is supplied to the clock input of the register phase 5 is accumulating adder 3 of the first cumulative module 1, and the clock input of the register total phase 12. The second signal sampling frequency fs2arrives at the clock input region is synchronous, provided that the formation of the second signal sample from the first by dividing the frequency fs1in k times.

In practical circuits, the register 2 of the first code frequency and the register 7 of the second code frequency in addition to the information inputs are the inputs of the record (Fig. 1 not shown), which writes the input data to these registers. In practical circuits, registers 2, 5, 7, 10, 12 may have inputs reset (Fig.1 not shown), which in the initial work can be submitted Abdoulaye signal that sets the registers in the initial (zero) state. Questions data record and reset registers in the framework of this application are not considered as well-known and not related to the essence of the claimed invention.

The elements included in the inventive digital generator are known elements of digital technology. The General structure of the accumulative adders 3, 8 are known, for example, from [3, S. 50-51, Fig.2.13], Combinational adders 4, 9, 11 may be made under the scheme combinational adder serial transfer, described, for example, in [7, S. 523-536, Fig.6.96, 6.97] , which is preferable from the viewpoint of reducing consumption, or sh, 10, 12 may be made in the form of registers memory-based triggers (e.g., D-flip-flops) that can record, store and read data in parallel binary code, see, for example [7, S. 348-354, Fig.5.85].

The inventive digital generator works as follows.

At the first control input of the claimed digital generator comes K1bit number N1proportional to a given increment1the current phase in nakaplivaya the adder 3 of the first (high-frequency low-rank) cumulative module 1 in each step of signal sampling frequency fs1. The number of N1set the transmitter (Fig.1 not shown), for example, based on operating conditions of the scheme tracking carrier" or "schema tracking delay". The number of N1arrives in the form of a digital signal to an information input of the register 2 of the first code frequency, where is recorded on the corresponding recording signal. From the output of the register 2 number1arrives at the first input of the combinational adder 4. To the second input of the combinational adder 4 with a frequency of fs1comes TO1-bit number that specifies the value of the current phase accumulated in the register phase 5 to dannemiller adder 3 with a frequency of fs1are formed (in digital form) the current values of phase1that geometrically interpreted (in the coordinate system of the phase - time) step function shown in Fig.2 the curve "I". The slope of the curve "I" determines the rate of the increment of the phase and thus the frequency f1signal synthesized cumulative module 1. This slope, and hence the frequency f1can be changed by changing the number of N1. The phase1taken with a frequency of fs1output register phase 5 is accumulating adder 3 high-frequency low-rank cumulative module 1 (Fig.2, curve "I"), arrives at the first input of the output combinational adder 11.

At the second control input of the claimed digital generator is delivered TO2bit number N2proportional to a given increment 2the current phase in nakaplivaya the adder 8 second (low frequency high RES) cumulative module 6 in each step of signal sampling frequency fs2. The number of N2set the transmitter (Fig. 1 not shown) in accordance with the number of N1on the basis of operating conditions of the scheme tracking carrier" or "schema tracking delay". The number of N22arrives at the first input of the combinational adder 9. To the second input of the combinational adder 9 with a frequency of fs2comes TO2-bit number that specifies the value of the current phase accumulated in the register phase 10 to this measure. The result of the sum of these numbers is sent back to the register phase 10. Thus, at the output of the accumulating adder 8 with a frequency of fs2are formed (in digital form) the current values of phase2that geometrically interpreted (in the coordinate system of the phase - time) step function shown in Fig. 2 curve "II". The slope of the curve "II" defines the speed increment phase and, consequently, the frequency fs of the signal synthesized cumulative module 6. This slope, and hence the frequency f2may change when the number of N2.

The phase2(up to K1senior level) removed from output K1high-order bits of the register phase 10 is accumulating adder 8 low-high RES cumulative module 6 (Fig.2, curve "II"), comes with a frequency of fs2to the second input of the output combinational adder 11, which is formed with a value of phase1entering epiteleo module 1 (Fig.2, speed curve "I").

The sum of the phases1+2=presented on Fig.2 speed curve "III". This result is recorded in the register of the total phase 12, which with frequency fs1goes to the first output of the proposed generator.

The slope of the speed curve "III" determines the speed increment total phaseand, therefore, the frequency fthe signal synthesized by the inventive generator. This slope, and hence the frequency fthat changed when changing any of the constituent parts of the curve "I" and/or "II".

Thus formed on the first output of the proposed generator digital signal values of the total phasethen can be converted to an analog signal using a code Converter that implements, for example, a table of sines (cosines) and based on a persistent storage device (ROM), see, for example [3, S. 75-76, Fig.3.12 ]. To improve the accuracy of such conversion, if necessary, can be used the signal produced by the second generator output, i.e., output M = K2- K1least significant bits of the register phase 10 is accumulating adder 8 second cumulative module 6.

the AE curve III shows, that generated the claimed generator values of total phasetaken from the first output of the proposed generator, coincide with the reference values at the moments corresponding to the cycles of the signal sampling frequency fs2. In other moments generated values of total phase different from the reference, and this difference is systematic. This bias is uniquely determined by the ratios of the phases of the first and second sampling signals, therefore, can be easily calculated and then taken into account when digital tracking systems correlation signal processing. In particular, the account of the systematic error is made in the exercise of absolute phase measurements. In cases where the absolute phase measurements are not carried out, formed of the inventive digital generator values of total phase used without correction of systematic errors.

The peculiarity of the proposed generator, in which the formation of the output values of the phaseby summing the two components (high-frequency 1and low-frequency2), is an obvious limitation on the size of each is eklow generated phase valuesincrement the total phase at each step of the sampling rate should not be less than zero and greater than 180o().Taking into account this constraint selects a specific ratio between razryadnitsy K1TO2cumulative adders 3, 8, and values written to them integers N1N2and select the desired cycle of operation (periods of overflow) accumulative adders 3, 8.

Thus, the claimed digital generator synthesizes the output signal in the form of digital values of the total phase, are generated by two cumulative modules (high-frequency low-rank and low-frequency high RES). This solution allows you to reduce power consumption in comparison with the generator, made the traditional way using a single (high-frequency high RES) cumulative module.

Rate if possible win on the power consumption of the proposed digital generator compared to a traditional generator structure on the example of the implementation of the digital generator C/a code signals SRNS GPS. Of the conditions for performing correlation processing let us assume that the generator must generate a frequency five times greater than case should be fs1= 20 MHz, and the desired discrete frequency setting f = 1 Hz.

Given these circumstances, the necessary width To the generator traditional patterns determined from the formula f = fs1/2Kis the value of K = 25.

The inventive generator in this case is as follows: accumulating adder 3 high-frequency low-rank cumulative module 1 is 2-bit (K1= 2), works with frequent sampling rate fs1= 20 MHz and synthesizes the frequency f1= 5 MHz; accumulating adder 8 low-high RES cumulative module 8 is 23-bit (K2= 23), operates with a sampling frequency of fs2= fs1/8 = 2.5 MHz and synthesizes the frequency f2= 0,115 MHz.

About the power consumption (P) digital generator can be estimated using the empirical formula

P = Pg x Kg x F,

where Pg is the consumption of one standard element (depending on technology);

Kg - number of standard elements defined by a width;

F is the frequency, MHz.

In this case, for both traditional and inventive generators consumption of one standard element (Pg) in the use of the ke-power generators.

Given this simplification, the consumption of traditional generator (R0) can be described as

P0= F x Kg = fs1x (Ks0+Kr0)

where Ks0- bit combinational adder;

Kg0the bit width of the register phase.

The consumption of the proposed generator (Pi) is estimated as

P1= F x Kg = fs1x (Ks1+Kr1) x 2 + fs2x (Ks2+ Kr2)

where Ks1- bit width high-frequency Raman adders 4, 11;

Kg1- bit frequency register 5, 12;

Ks2- width of the low-frequency Raman adder 9;

Kr2- width low register phase 10.

We assume that the consumption per one digit adder and register phase, implemented, for example, using D flipflops, about the same [8]. Given this assumption, the consumption of traditional generator (R0and consumption of the proposed generator (P1for the purposes of comparative analysis can be written as follows:

P0= fs1x (Ks0+Kr0) = fs1x To x 2 = 20 x 25 x 2 = 1000;

P1= fs1x (Ks1+Kr1) x 2 + fs2x (Ks2+ Kr>and P1it is seen that the gain in power consumption at the proposed digital generator compared to a traditional generator patterns in terms of this example is more than 3.6 times. Really win on power consumption is higher because the generator traditional patterns of high-frequency high RES combinational adder must contain additional circuit parallel transfers are not considered in the above example, which leads to an increase in the volume of this adder and, accordingly, its power several times. For the proposed generator such circuits no, because the combinational adder 4 first cumulative module 1 has little bits, and combinational adder 9 second cumulative module 6 operates at a sufficiently low frequency, which allows the use of adders with a serial transfer.

Of the above it is seen that the inventive digital generator for digital tracking systems correlation signal processing, implements a method of direct digital synthesis with the accumulation of the current phase, technically feasible, implement industrial and solves the technical problem to reduce Energo the s for its use, for example, in a portable multichannel equipment consumers SRNS signals (SSS), including those running on battery power.

Sources of information

1. Varakin L. E. communication System with samopodoben signals. M, Chapman and hall, 1985.

2. The Air A. And, Kudryavtsev I. C., Mishchenko, I. N., Shebshaevich B. C. Equipment potrebitelei SRNS "NASCAR", part I, II. Foreign electronics, 1983, 4, 1983, S. 70-91, 5, S. 59-83.

3. Digital radio receiving system: Reference /M And, Azishski, R. B. Mazepa, E. P. Ovsyannikov, and others / edited by M. I. of Adissage, M., Radio and communications, 1990.

4. RF patent 2090902 (C1), CL G 01 S 5/14, publ.20.09.97.

5. RF patent 2146378 (C1), CL G 01 S 5/14, publ. 10.04.2000.

6. On-Board satellite navigation device / I. C. Kudryavtsev, I. N. Mishchenko, A. I. the air and others; Ed. by B. C. Shebshaevich. M, Transportation, 1988.

7. G. I. Puhal, T. J. Novoseltsev. Digital devices. Polytechnic. St. Petersburg, 1996.

8. Catalogue of the elements of the company "Samsung" - "STD 80/STDM80 0.5 m 5V/3.3 V Standard Cell Library Data Book, 1996, Samsung Electronics Co., Ltd."on

Digital generator for digital tracking systems correlation processing signals containing the first cumulative module, executed in the form of a succession of the input digital generator and accumulating adder, working with sampling frequency fs1made in the form of series-connected combinational adder, a first input of which is an information input of this accumulating adder, and register phase, the output bits of which are connected in this nakaplivaya the adder to the second input combinational adder, characterized in that the input of the second cumulative module, made in the form of serially connected register of the second code frequency information input of which forms the second control input of the digital signal generator, and accumulating adder, working with sampling frequency fs2= fs1/k, where k is an integer greater than one, made in the form of series-connected combinational adder, a first input of which is an information sign that is accumulating adder, and register phase, the output bits of which are connected in this nakaplivaya the adder to the second input combinational adder, the said elements of the first rollup module is made TO1-bit, as specified elements of the second cumulative module - K2-bit and K2>K1, the adder and working with sampling frequency fs1register the total phase, the output bits of which forms a first output of the digital oscillator, the first input of the output combinational adder coupled to the output bits of the register phase accumulating the first cumulative adder module, and the second input - output K1high-order bits of the register phase accumulating adder of the second rollup module in which the output of the M least significant bits of the register phase, where M = K2-K1forms a second output of the digital generator.

 

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2 dwg, 1 tbl

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