Analog-to-digital converter logical deployment

 

(57) Abstract:

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code. The technical result is to increase speed ADC by applying the optimal logical procedure of selection of the output code, taking into account the statistical characteristics of the signal. The device comprises a comparison circuit, a block allocation of the absolute values of the two comparator, clock, trigger, two element, And the element is NOT, d / a Converter, register, ROM. table 1. , 2 Il.

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code.

Known analog-to-digital Converter (ADC) the witness of the type with a voltage comparator, oscillator, item, count, voltage reference and digital-to-analogue Converter (DAC) (microelectronic device automation: Educational. manual for schools/ A. A. Sazonov, V. I. Nikolaev and others ; Ed. by A. A. Sazonova. - M. : Energoatomizdat, 1991. -S. 153, Fig. 2.29).

The disadvantage of this device is izkuyu the technical nature of the offer is a successive approximation ADC, contains a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage, and the output connected to the first input register of the successive approximation (RPA), the first outputs of which are connected to the inputs of the digital to analogue Converter (DAC) and are simultaneously outputs of the ADC, the DAC output is connected to the second input of the comparison circuit, the second input of the successive approximation register is the second ADC input, a third input connected to the output element And the second output to the second input of this element, the first input of which is connected to the generator output clock pulses (Chernov Century, Device I / o analog information to digital systems of data collection and processing, - M. : Mashinostroenie, 1988, - S. 85, Fig. 57, Functional diagram and the timing diagram of the ADC successive approximation).

The disadvantage of this device is a low speed, because it does not takes into account statistical characteristics of the signal.

The purpose of the invention is improving the performance of the ADC by applying the optimal logical procedure of selection of the output code, taking into account the statistical characteristics of the signal.

The goal dostigaetsya convert the input voltage and the first input device, and to the second input connected to the DAC output, the inputs of which are connected to the outputs of the register are output devices, a generator of clock pulses, the output of which is connected to the first input element And the output of which is connected to the first input register, entered the block allocation of the absolute values of the first and second Comparators, the trigger, the second element And the element and NOT a permanent storage device (ROM) whose outputs are connected to the third inputs of the register, the first address inputs connected to the outputs of the register and the second address input is connected to the output of the second comparator, the first input of which is connected to the bus "earth", and the second input is connected to the output of the comparison circuit and the input circuit of the allocation of the absolute value, the output of which is connected to the first input of the first comparator, the second input is a second input device, and the output connected to the first input of the second element And a second input connected to the trigger output and the second input of the second element And the third input is connected with the output element, and the output connected to the second input of the trigger, the first input of which is the third input device, the output of the generator is connected to the input element, the second input register is the th same time, that it entered the block allocation of the absolute values of the two comparator, the trigger element And the element is NOT constant storage device, which are standard nodes analog and digital computers. However, despite the fact that the blocks are standard nodes analog and digital computing techniques, their introduction, as well as the emergence of new functional connections between them and the existing units gives the chance to appear in the device to a new property. Namely: ADC logical deployment can reduce the conversion time of the measured value through the application of optimal logical procedure code selection taking into account the probability parameters of the measured value. The optimal procedure code selection can be made using methods known in theory of automatic control, for example, the method of "half-split", method time-likelihood and other (automation of radio. Edited by B. N. Balashova. - M. : Soviet radio, Moscow (1966). -S. 428-463). The optimal procedure can reduce the number of steps in the selection code corresponding to the input voltage and, consequently, to increase the speed of the ADC. Crwoj code with a given error.

Structural diagram of the ADC is shown in Fig. 1, where 1 - comparison circuit; 2 - block allocation of the absolute value of the input signal; 3, 4, the first and second Comparators; 5 - clock 6 - trigger; 7, 8, the first and second elements; 9 - item NOT; 10 - d / a Converter DAC; 11 - register; 12 - permanent memory (ROM).

Comparison circuit 1 is intended to compare the input to be converted voltage and voltage output DAC 10. Using block allocation of the absolute value of 2 is determined by the absolute value of the difference between the input is converted by the voltage UIand the voltage output from the DAC 10. The first comparator 3 is triggered if the voltage at the output of block allocation of the absolute value of 2 is less than the voltage level supplied to the second input of the comparator 3 from the second ADC input (this input is energized, which specifies the maximum error in conversion ). The signal at the output of the comparator 3 actually defines the end of the conversion. Using the second comparator 4 determines which of the voltages is greater: convert the input voltage or the output voltage of the DAC 10. The clock pulse is the first time with the arrival of the pulse at the third input of the ADC start trigger 6 has a status of "I". Upon completion of the conversion trigger 6 switches into state "0" by a signal from the output of the second element And 8. Element And 7 permit the passage of pulses from the generator 5 to the input capture register 11 when the ADC is converting the measured value. The second And gate 8 is designed to generate pulse at the control input of the trigger 6 and transfer it to the state "0" at the end of the conversion cycle. Item NO 9 inverts the pulses from the output of the generator 5, thereby avoiding the formation of the pulse at the output of the element And 8 (i.e., sounding an alarm about the end of conversion) due to transients in the ADC. DAC 10 converts the code coming from the output of the register 11, an analog voltage. Register 11 contains the current value of the code. The number of bits of the register 11 is equal to the word length of the ADC. In the initial state trigger 6 is set by the supply of the pulse at the input "set initial state" of the ADC. Record the information in the register 11 is a flow pulse to the first input of the register 11. In permanent memory (ROM) 12 stores the optimal sequence of code values. While the current code from the output of the register 11 is supplied to the younger address bits of the ROM 12, and the output from the comparator 4 comparator 4 (which is determined by the ratio between the input converted voltage and the voltage output from the DAC 10). Before operating the ADC in the ROM 12 must be recorded in the desired sequence codes, which will be selected code to the DAC 10.

Description of the operation of the device will consider for the case of 4-bit ADC and implementation of a logical procedure code selection in accordance with Fig. 2 (for example the method used half-split). In accordance with Fig. 2 initially in register 11 write the code corresponding to the number 8. In the next step, if the voltage at the DAC output 11 will exceed the level of the converted voltage UIat the output of the second comparator 4 will be a logic level "0", and therefore in accordance with Fig. 2 in register 11 will be recorded code corresponding to the number 4. If the output of the second comparator 4 will be a logic level "I", the following code is the number 12. Similarly, there is a regular choice code values in other cases. The contents of the ROM 12 in implementing this search procedure is given in the table. As can be seen from the table, if the current code value in the register 11 is 8 and at the output of comparator 2 will be the level to "0" at the output of the ROM 12 and the code will equal 4. However, if the output of the comparator will be the level "1", then the address input the odes in the remaining cells of the memory.

The process of converting an analog voltage into a digital code from the ADC logical deployment is as follows.

When the device is in the register 11 is filled in with the initial value code (in this case, the code number 8) submission of a pulse on input "Setting to its original state". The output of the DAC 10 is set to the appropriate voltage, which is compared with an input voltage UI. The voltage Uccthe output of the comparison circuit 1 will be equal to the difference between the input voltage and voltage output DAC UDAC: USS= UI-UDAC. The resulting value of the difference using the second comparator 4 is compared with the value zero. Depending on the ratio between the input voltage and the voltage output from the DAC 10 at the output of the second comparator 4 will be a logic level "0" or "1". This signal is applied to senior address digit ROM 12. Code at the output of the ROM 12 will depend on the current value of the code stored in the register 11, the incoming low-order bits of the ROM 12, and a signal level at the output of the second comparator 4. Thus at the input of the register 11 will receive a different code, depending on the level of the output signal of the comparator 4, and accordingly on the ADC trigger 6 is transferred into the state "1" and permit the passage of pulses from the clock generator 5 through the first element And 7 to the first input of the register 11. With the arrival of the next pulse at the first input register 11 will be recorded next code value in accordance with Fig. 2. Thus will be the procedure of the selection code, which is determined by the contents of the ROM 12.

In that case, if the voltage at the output of block allocation of the absolute value of 2 is less than the voltage supplied to the second input of the ADC (the level of this signal corresponds to the desired value conversion error), work first comparator 3, and then at the end of the next pulse from the clock generator 5 will trigger the second element And 8 pulses to the input element And 8 come from the output of the generator 5 through the element is NOT 9). The pulse from the output element And 8 will set the trigger 6 to the initial state and the conversion process will be completed. In register 11 will be written to the code value corresponding to the converted voltage with a given error in conversion. The output of the trigger 6 is supplied to the second output of the ADC, thereby indicating the state in which the ADC.

Unless the pulse PA input "Setting in the initial state, when the next cycle of the conversion selection code will be made, starting with the code that was stated is but the conversion time will obviously decrease.

It should be noted that upon reaching the hanging vertices in Fig. 2, the following code value in accordance with the data table will be the source code value (in this case, the number 8), and the conversion process will begin with the initial code.

Thus, ADC logical deployment can reduce the conversion time by applying optimal matching code, taking into account the statistical characteristics of the signal. In addition, the ADC allows the transformation with a given error.

Analog-to-digital Converter comprising a comparison circuit, the first input of which being the first input of the Converter, is designed to input the converted voltage and the second input of the inverter connected to the output of the digital-to-analog Converter (DAC), the inputs of which are connected to the outputs of the register and are the first outputs of the inverter, the generator of clock pulses, the output of which is connected to the first input of the first element And whose output is connected to the first input register, characterized in that it introduced the block allocation of the absolute values of the first and second complaceny to the third inputs of the register, the first address inputs connected to the outputs of the register and the second address input is connected to the output of the second comparator, the first input of which is connected to the bus "earth", the output difference of the input voltage and the voltage from the DAC output of the comparison circuit connected to the second input of the second comparator and to the input of block allocation of the absolute values, the output of which is connected to the first input of the first comparator, the second input is a second input transducer and the output is connected to the first input of the second element And a second input connected to the output of the trigger, allowing the passage of pulses from the clock pulses through the first element And the third input of the second element And is connected to the output element, and the output connected to the second input of the trigger, the first input of which is the third input device, and the output trigger is designed to alarm on the second output transducer of the state in which the Converter, the generator output clock pulses connected to the input element, the second input register is the fourth input device.

 

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