# Generator sinusoidal signal to the electromagnetic multifrequency structuremap

(57) Abstract:

The unit refers to the measurement technique and can be used in conjunction with electromagnetic structurename for non-destructive testing of objects, in particular, by the method of eddy currents. The device includes a pulse generator controlled frequency divider, a counter, the unit's permanent memory, digital to analog Converter and filter low frequency. The structure of the device introduced two block switches the unit inverters and switch. The first set of switches is used for switching the address inputs of the unit's permanent memory. In each of the sectors of the unit's permanent memory codes stored instantaneous values of a sine wave signal for a half period of the sine wave. Each sector corresponds to the number of sampling points for the period of the sinusoidal signal. The second set of switches, the unit inverters and switch are used to restore sinusoidal signal at half of its full period. This method of storing code sample allows you to make the frequency at which the counter is equal to the sampling frequency. The invention extends the frequency range of the generated signal in the direction of increasing the maximum the IDT with electromagnetic structurename for fault detection and structurele products, in particular, the method of eddy currents.Known sine wave signal generator of electromagnetic StructureMap containing series-connected generator of rectangular pulses of fixed frequency, variable frequency divider and counter series-connected unit's permanent memory, digital to analog Converter, a filter and a control unit, connected to an adjustable frequency divider. C. the USSR 1000896, CL G 01 N 27/90, publ. 28.02.83, bull. 8).The disadvantage of the generator is the limited frequency range of the generated sinusoidal signal. In the case of a large number of sampling points for the period of a sinusoidal signal of a lower frequency of the generated sinusoidal signal is very low. It is obvious that the minimum sampling period T_{DMP}cannot be less than the value of

T

_{DMP}= t

_{WITH}+t

_{A}+t

_{DAC}, (1)

where t

_{WITH}the time switch counter (with submission to the counting input of the counter output signal of the controlled frequency divider to establish a new output of the counter code); t

_{AND}- sampling time addresses a persistent storage device (ROM) used as a block postelennyh characteristics of modern element base shows for common chip permanent storage devices sampling time address ranges from 45 (1500 RT 416) 60 NS (CR 556 RT 18), and for relatively inexpensive high-speed digital to analog converters the conversion code in the current ranges from 5 (1118 PA 6 (a) to 20 NS (1118 PA 1 (a). Thus, the minimum sampling period (even without taking into account the time needed to switch the meter) ranges from 50 to 80 NS, which corresponds to the sampling frequency f

_{D}not above 12.5. . . 20 MHz. At the same time, the frequency of the generated sinusoidal signal f

_{WITH}equal to the sampling frequency f

_{D}divided by the number of sampling points for the period of a sinusoidal signal of n

_{D}< / BR>

f

_{WITH}= f

_{D}/n

_{D}, (2)

where f

_{WITH}the frequency of the generated sinusoidal signal; f

_{G}- frequency square wave generated by the oscillator square wave of fixed frequency;

_{D}- sampling rate; n

_{D}- the number of sampling points for the period of the sinusoidal signal.Therefore, when the number of sampling points n

_{D}= 512 and the sampling frequency f

_{D}12,5. . . 20 MHz maximum frequency of the generated sinusoidal signatureimage sinusoidal signal is for use with this device limited frequency f

_{Max}of the order of tens of kHz; at the same time for multi-frequency electromagnetic structuroscopes often required test sinusoidal signal with a frequency of one MHz. Thus, the above mentioned device (analog) is not wide enough frequency range of the generated sinusoidal signal. The extension of the frequency range of the generated sinusoidal signal is impossible, since at high frequencies, it is impossible to use a large number of sampling points for the period of a sinusoidal signal of n

_{D}due to the limited performance of the hardware components, and at low frequencies in a small number of sampling points for the period of the sinusoidal signal decreases the accuracy of the generated sinusoidal signal (i.e., increases the harmonic content of the generated sinusoidal signal).Closest to the proposed device is a generator of sinusoidal signals to electromagnetic multifrequency StructureMap containing connected in series generator of rectangular pulses of fixed frequency controlled frequency divider and counter series-connected unit's permanent memory, digital-to-analogue converted into uchenykh between the outputs of the least significant bits of the counter and the inputs of the least significant bits of the unit's permanent memory. C. the USSR 1118908, CL G 01 N 27/90, publ. 15.10.84, bull. 38).The disadvantage of the prototype is also limited frequency range of the generated sinusoidal signals. Some extension of the frequency range of the generated sinusoidal signal achieved by reducing the number of sampling points for the period of the sinusoidal signal at high frequencies, what is the unit keys. The unit key is used for switching the inputs of the unit's permanent memory: by disabling the unit's permanent memory from the least significant bits of the counter decreases the number of sampling points for the period of the sinusoidal signal, because when you disable one LSB of the counter from entering the unit's permanent memory is read from the unit's permanent memory code every second point sampling, and the number of sampling points for the period of the sinusoidal signal is reduced by half; when disconnecting the two least significant bits of the counter from the input unit constant memory is read from the unit's permanent memory code every fourth point sampling, and the number of sampling points per period is reduced four times; when disconnecting the three least significant bits of the counter from the unit's permanent memory p is misali for the period reduced by 8 times, and so D. , ie when you are disconnected from the inputs of the unit's permanent memory m least significant bits of the counter (where m is a positive number, the maximum value of which is determined by the ratio of the maximum number of sampling points for the period of the sinusoidal signal to the minimum number of sampling points for the period of the sinusoidal signal) number of sampling points in the period decreases in the 2

^{m}time. The reduced number of sampling points for the period increase is achieved the maximum frequency of the generated signal; however, at low frequencies is the maximum (for this device) number of sampling points for the period, and with increasing frequency of the generated signal, the number of sampling points, if necessary, reduced. The decrease in the number of sampling points for the period of the sinusoidal signal leads to the deterioration of the quality of the generated sinusoidal signal. Frequency side of the spectrum components of the generated signal is determined by the formula

f

_{m}= f

_{WITH}(in

_{D}1)= f

_{D}if

_{WITH}, (3)

where f

_{WITH}the frequency of the generated sinusoidal signal (the frequency of the main harmonic of the generated signal; n

_{D}- the number of sampling points for the period of sinusoidal the second harmonic generated signal; other (positive) values of i correspond to the side constituting the spectrum of the generated signal. As can be seen from (3), reducing the number of sampling points for the period of the sinusoidal signal causes the frequency of adverse components are drawn to the undamental that hampers their suppression nepertraukiamam filter low frequency. However, for high frequencies generated sinusoidal signal the deterioration of its quality by reducing the number of sampling points for the period of the sinusoidal signal is less than for low frequencies. Indeed, from (3) it follows that with increasing frequency of the generated sinusoidal signal f

_{WITH}the absolute difference between the frequencies of the main and side harmonics increases, therefore, the sideband suppression of the spectrum of the generated signal using the filter of low frequencies easier.For the case when all inputs to the unit's permanent memory connected to respective outputs of the counter

f

_{WITH}= f

_{G}/n

_{D}k

_{D}, (4)

where f

_{WITH}the frequency of the generated sinusoidal signal; f

_{G}- frequency square wave generated by the square wave generator the rate of frequency division of the controlled frequency divider.As for the case when all inputs to the unit's permanent memory connected to respective outputs of the counter, the relation is valid:

f

_{D}= f

_{G}/k

_{D}, (5)

where f

_{D}- sampling rate; f

_{G}- frequency square wave generated by the oscillator square wave of fixed frequency;

_{D}the division ratio of the frequency of the controlled frequency divider;

the expression (4) can be transformed to mind

f

_{WITH}= f

_{G}/n

_{D}, (6)

where f

_{WITH}- frequency square wave generated by the oscillator square wave of fixed frequency;

_{D}- sampling rate; n

_{D}- the number of sampling points for the period of the sinusoidal signal.Expression (6) applies to cases where one or more least significant bits of the counter is disconnected from the outputs of the unit's permanent memory. From (4) and (6) shows that the decrease in the number of sampling points for the period of a sinusoidal signal of n

_{D}should lead to an increase in the frequency of the generated sinusoidal signal. Note, however, that for the prototype when the number of sampling points for the period of the sinusoidal signal by the turn off is easy to determine, disabling the m least significant bits of the counter from Junior address inputs of the unit's permanent memory reduces the sampling rate to 2

^{m}time. Indeed, the sampling frequency is determined by the switching frequency of the LSB of the counter is connected to the input of the unit's permanent memory. For the LSB counter switching frequency equal to the frequency of the output signal of the controlled frequency divider, i.e., is determined by the ratio f

_{G}/k

_{D}where f

_{G}- frequency rectangular pulses generated by the generator of rectangular pulses of fixed frequency;

_{D}the division ratio of the frequency of the controlled frequency divider. For the next digit counter switching frequency 2 times lower than the switching frequency of the LSB, and so on : the switching frequency of each of the next (older) level 2 times lower than the switching frequency of the previous (lower) level. It follows that when disabling the m least significant bits of the counter from the unit's permanent memory sampling frequency f

_{D}decreases in the 2

^{m}time.Therefore, according to (6) when the number of sampling points for the period of the sinusoids is priuilege sinusoidal signal f

_{WITH}does not change as the number of sampling points for the period of the sinusoidal signal, and the sampling frequency are reduced in equal number (2

^{m}) times, and therefore, the ratio of f

_{D}/k

_{D}remains constant.Thus, reducing the number of sampling points for the period of a sinusoidal signal of n

_{D}disabling least significant bits of the counter from the unit's permanent memory does not increase the frequency of the generated sinusoidal signal. To increase the frequency of the generated sinusoidal signal, it is necessary to disconnect the m least significant bits of the counter decrease, respectively, in the 2

^{m}once the division ratio of the frequency of the controlled frequency divider k

_{D}, thereby increasing the output frequency of the controlled frequency divider 2

^{m}time. Thus, the sampling frequency remains constant, but the frequency f

_{SC}running counter increases by 2

^{m}time. Therefore, for the prototype while maintaining the sampling frequency is a constant frequency at which the counter is increasing. Obviously, compared with the equivalent for the prototype the number of sampling points for the period can be changed from the n

_{Dmah}to n

_{DMP}where is sonalnogo signal, when maintaining a constant sampling rate reduces the requirements to the performance of digital to analogue Converter and the unit's permanent memory, therefore, the maximum frequency of the generated sinusoidal signal

_{Max}may be increased.However, since the frequency at which the counter is not reduced to the base of the counter, generator of rectangular pulses of fixed frequency and a controlled frequency divider still are overly stringent requirements. Thus the operating frequency of the generator of rectangular pulses of fixed frequency and a controlled frequency divider (f

_{G}) may be higher than the operating frequency of the counter f

_{SC}that depends on the range of variation of the division factor of the frequency k

_{D}the controlled frequency divider: with a minimum division ratio of the frequency of the controlled frequency divider, equal to k

_{DMP}the working frequency f

_{G}generator of rectangular pulses of fixed frequency and a controlled frequency divider in k

_{DMP}times greater than the frequency f

_{SC}running counter, and k

^{DMP}2

^{m}times the sampling frequency (in the particular case when k

_{DMPSC}).Thus, to the base of the prototype, namely the base of the counter, controlled frequency divider and generator of rectangular pulses of fixed frequency are overly stringent requirements. So, if the maximum number of sampling points for the period of a sinusoidal signal of n

_{Dmah}= 512, and the minimum n

_{DMP}= 8 (n

_{DMP}<8 the quality of the generated sinusoidal signal is poor due to the significant growth of the amplitudes side of the spectrum components of the output signal of the prototype, whose frequencies are close to the frequency of the generated signal, resulting in difficulty suppressing side of the spectrum components of the output signal of the prototype and increasing the harmonic content of the generated sinusoidal signal). In this case, when the maximum frequency of the generated signal frequency f

_{SC}running counter exceeds the sampling rate in n

_{Dmah}/n

_{DMP}= 512/8= 64 times (the smallest number of sampling points for the period of a sinusoidal signal of n

_{DMP}corresponds to the maximum frequency of the generated signal f

_{Max}and therefore, the maximum number of disconnected from the least significant bits of the counter is 1 MHz and the number of sampling points for the period of a sinusoidal signal of n

_{D}= 8, the sampling frequency is

f

_{D}= f

_{WITH}n

_{D}= 81= 8 MHz,

as the operating frequency of the counter f

_{SC}exceeding the sampling frequency f

_{D}in n

_{Dmah}/n

_{DMP}= 64 times

f

_{SC}= f

_{D}(n

_{Dmah}/n

_{DMP})= 864= 512 MHz.Accordingly, the frequency f

_{G}which is operated by the frequency divider and generator of rectangular pulses of fixed frequency should be at least 512 MHz. At the same time, even switching frequency triggers a fast series of logic circuits is not more than 1500 300 MHz (for other common series of logic circuits, such as 555, 1533, and even 500 and 1554 switching frequency of triggers does not exceed the specified value, and for some of these series is even smaller). It is obvious that the maximum switching frequency of the trigger determines the maximum operating frequency counter circuits of the above series, which will be even smaller than the maximum switching frequency of triggers. Thus, the frequency of the generated sinusoidal signal is significantly limited temporal characteristics (performance) of the element base, and if similar with the first performance of the unit's permanent memory and digital to analogue Converter, for prototype obstacle to a greater extent are the parameters of the element base generator of rectangular pulses of fixed frequency of the controlled frequency divider and counter. The prototype allows to reduce the requirements only to the temporary parameters (speed) of the unit's permanent memory and digital to analogue Converter, which is not enough to build broadband sinusoidal signal generator.An object of the invention is the extension of the frequency range of the generated sinusoidal signal while maintaining the quality of the generated sinusoidal signal.The technical problem is solved by the fact that the generator of sinusoidal signal to the electromagnetic multifrequency StructureMap (hereinafter referred to as the device) containing series-connected generator square wave of fixed frequency, a controlled frequency divider, a counter, and the unit's permanent memory and series-connected d / a Converter and filter low frequency, is connected to a managed frequency divider control unit, characterized in that it is equipped with block switch block switch codes DAMI counter (except output the most significant bit of the counter), and the second input unit switches to the outputs of the control unit, the input control unit switches connected to the outputs of the control unit, the output unit switches connected to the inputs of the unit's permanent memory (with the exception of the older unit's permanent memory); one unit switches codes discretization connected to the outputs of the unit's permanent memory, and other inputs unit switches code sample with the outputs of the unit inverters, the outputs of block switches code sample connected with the inputs of the digital to analogue Converter, the inputs of the unit inverters are connected to the outputs of the unit's permanent memory, the input control unit switches codes discretization coupled to the output switch, the inputs of the switch are connected to the outputs of the counter and the control inputs of the switch are connected to the outputs of the control unit senior unit's permanent memory connected to the control unit.The invention is illustrated by drawings, where Fig. 1 shows the block diagram of the device, and Fig. 2 is an example schematic distribution of the address space of the unit's permanent memory for the number of sampling points n

_{DMP}= 16 to n

_{Dmah}= 256 for the period of the sinusoidal signal, the ri n

_{DMP}= 2, which is the minimum possible number of sampling points for the period of the sinusoidal signal, the total amount of the unit's permanent memory will remain the same).The device has connected in series generator of rectangular pulses of fixed frequency 1, the controlled frequency divider 2, a counter 3, the unit switches 4, the unit's permanent memory 5, a switch 6, the unit of the inverter 7, the unit switches code sample 8, a d / a Converter 9, the LPF 10, the control unit 11.The device operates as follows. Rectangular pulses of fixed frequency f

_{G}from the output of the generator of rectangular pulses of fixed frequency 1 arrives at a controlled frequency divider 2, the division ratio of the frequency of k

_{D}which is set by the control unit 11. The pulses from the output of the controlled frequency divider 2 is coming to the counting input of the counter 3. Count frequency f

_{SC}counter 3, therefore, is determined by the frequency generation

_{G}generator of rectangular pulses of fixed frequency 1 and the division ratio of the frequency of k

_{D}the controlled frequency divider 2, which is set by the control unit is - the frequency at which the counter 3; f

_{G}- generation frequency generator of rectangular pulses of fixed frequency 1; k

_{D}the division ratio of the frequency of the controlled frequency divider 2; f

_{D}- sampling rate.Because when the number of sampling points for the period of a sinusoidal signal of n

_{d}= 2

^{N}(where N= log

_{2}(n

_{D}) is a positive integer equal to the number of inputs of the unit's permanent memory 5 connected to the outputs of the counter 3 switch 4) values of the function |sin(x)| (i.e., the module of the function sin(x)) are repeated during the period of the sinusoidal signal, at least twice, to conserve address space of the unit's permanent memory 5 in the unit's permanent memory 5 is stored codes sampling a sinusoidal signal only for 1/2 of the period of the sinusoidal signal, calculated by the formula

< / BR>

where 2

^{N}= n

_{D}- the number of sampling points for the period of a sinusoidal signal (N is the number of inputs of the unit's permanent memory, connected by a switch with 4 outputs of the counter 3); i is the number of point sampling, i = 0 . . . n

_{D}-1; A - amplitude sinusoidal signal is determined by the formula

< / BR>

where M - bit output code block is round(A), accordingly, the minimum value of the sinusoidal signal corresponds to the code 0 and the maximum value of the sinusoidal signal code (2

^{M}-1), i.e. the minimum and maximum values of the output digital code of the unit's permanent memory 5 correspond to the minimum (i.e. -1 corresponds to a code sample 0) and maximum (i.e. 1 corresponds to the code sample 2

^{M}-1) the values of the sinusoidal signal.In this case, codes discretization of the second half period of the sinusoidal signal can be determined without the use of complex (and relatively slow compared to the more simple logical elements of the same series) arithmetical-logical unit by simply inverting the code of the corresponding instantaneous values of a sinusoidal signal of a first half period of the sinusoidal signal. Uses the well-known relation sin(x) = -sin(x+); if the minimum value of the sinusoidal signal corresponds to a code sample 0 and the maximum value of the sinusoidal signal corresponds to a code sample (2

^{M}-1), where M - bit output code of the unit's permanent memory 5, it is fair to codes of sampling a sinusoidal signal, bycicle a positive number in the range 1. . . ((n

_{D}/2)-1); n

_{D}- the number of sampling points for the period of the sinusoidal signal. Point sampling with the number 0 corresponds to the code rate corresponding to the zero value of sin(x). Data for the second half of the half period sine wave values are identical to those obtained by the formula (8) in all cases, except for i= 0 (which corresponds to the zero value of the function sin (x)), i.e., when i= 1. . . ((n

_{D}/2)-1).The peculiarity of this method of encoding and subsequent recovery sinusoidal signal from its digital values, as you can see, is the representation of null values sinusoidal signal of two values code 1000. . . 0000 and 0111. . . 1111 in binary notation). A= 2

^{M}-1 is an odd number, hence A/2= (2

^{M-1}-1/2)= (2

^{M-1}-0,5) - a non-integer number, the fractional part is equal to 0.5. When the conversion result A/2 in binary code with subsequent rounding will receive a number of 1,000. . . 0000 in binary representation, i.e., 2

^{M-1}that when inverting gives a value of 0111. . . 1111, i.e., (2

^{M-1}-1), where M - bit output code of the unit's permanent memory 5.Therefore, calculated according to the formula (8) is the code rate R that is. 111. It is easy to see that in fact, and in another case, the error in the representation of null values is not greater than the rounding error of 1/2

^{M+1}or 2

^{-(M+1)}where M - bit output code of the unit's permanent memory 5, and does not provide (at a sufficiently large value of M) a significant impact on the quality of the generated sinusoidal signal. In addition, increasing the bit M code sampling a sinusoidal signal (i.e., the bit of the output code of the unit's permanent memory 5, respectively, and the input code d / a Converter 9) this error can be reduced.The unit's permanent memory 5 is divided into sectors, each of which codes stored sampling a sinusoidal signal to 1/2 period of the sinusoidal signal, with each sector corresponds to the number of sampling points for the period of a sinusoidal signal of n

_{j}(respectively j-sector has a volume of n

_{j}). For two adjacent frequencies of sampling number of sampling points for the period of a sinusoidal signal of n

_{D}differs twice (respectively the volumes of the respective sectors of the unit's permanent memory 5 also differ by half).Switching from what is the number of sampling points on the period of the generated sinusoidal signal of n

_{D}. Sectors of the unit's permanent memory 5 have a volume of 2

^{n}where n is a positive integer, and is located in the address space of the unit's permanent memory 5 so that the start address of each sector multiple of its size (i.e., the starting address of the sector size of 2

^{m}the address space of the unit's permanent memory 5 is a multiple of 2

^{m}).The minimum number of sampling points for the period of a sinusoidal signal of n

_{DMP}depends on the quality of the generated sinusoidal signal. Obviously, the minimum number of sampling points for the period of the sinusoidal signal

_{DMP}may not be less than 2. In the case of n

_{DMP}= 2 the output signal of the digital to analogue Converter 4 has the shape of a meander. Using the LPF 10 of the meander can also be obtained sinusoidal signal, but in this case, the parameters of the LPF 10 meet very stringent requirements, since the amplitude of the side components of the generated signal (i.e., high-frequency harmonics) in this case is great.Sector unit's permanent memory 5, which reads codes sampling a sinusoidal signal (a value is considered as the sector unit's permanent memory 5 (the number of sampling points for the period of the sinusoidal signal

_{D}) is determined by the number of bits of the counter 3 which are connected with inputs of the unit's permanent memory 5, and the coordinates of the start sector in the address space of the unit's permanent memory 5 outputs a control unit 11, connected by a block of switches 4 inputs of the unit's permanent memory 5. The status of the older unit's permanent memory 5 (connected to the outputs of the control unit 11) remains unchanged, and the state Junior address inputs of the unit's permanent memory 5 (connected to the outputs of the counter 3) is changed in accordance with the status of the corresponding bits of the counter 3. For switching the inputs of the unit's permanent memory 5 is a block switches 4. The control unit switches 4 is performed by the control unit 11 setting code input unit control switches 4. Changing the code to the inputs of the control unit switches 4 inputs of the unit's permanent memory 5 are connected either to the outputs of the respective bits of the counter 3, or outputs of the control unit 11. In the first case, the input status of the unit's permanent memory 5 connected to the outputs of the block of switches 4, is changed in accordance with the status of the corresponding bits of the counter 3, and the second is the permanent memory 5 (sector unit's permanent memory 5), from which it reads codes instantaneous values of a sine wave signal. The choice of sector unit's permanent memory 5 and sets the number of points sampling a sinusoidal signal for the period of a sinusoidal signal of n

_{D}so, is performed by the control unit 11 using the unit switches 4.Thus, for the proposed unit installation codes at the inputs of the control unit switches 4 determines the number of sampling points for the period of the sinusoidal signal and the frequency of the generated sinusoidal signal f

_{WITH}: when reducing or increasing the number of sampling points for the period of a sinusoidal signal of n

_{D}the sampling frequency f

_{D}(i.e., in this case, the repetition rate of the sample code sampling instantaneous values of a sine wave signal of the unit's permanent memory 5) remains unchanged, however, since the number of sampling points for the period of a sinusoidal signal of n

_{D}decreases the frequency of the generated signal f

_{WITH}accordingly increases (decreasing the number of sampling points for the period of a sinusoidal signal of n

_{D}) or decreases (with increasing number of sampling points for the period of sinusoid is carried out in two ways: first, by changing the division ratio of the frequency of k

_{D}the controlled frequency divider 2, and secondly, by changing the number of sampling points for the period of the sinusoidal signal

_{D}using the unit switches 4 and control unit 11. The first method changes the frequency of the generated sinusoidal signal f

_{WITH}(changing the division ratio of the frequency of k

_{D}the controlled frequency divider 2) applies in the relatively low frequency of the generated sinusoidal signal, while the parameters of the element base unit's permanent memory 5, a d / a Converter 9, the unit of the inverter 7 and the unit switches code sample 8 can increase the sampling frequency f

_{D}. After reaching the maximum possible sampling frequency f

_{Dmah}the frequency of the generated sinusoidal signal f

_{WITH}increased by reducing the number of sampling points for the period of a sinusoidal signal of n

_{D}using the unit switches 4 and the control unit 11 (up to values of n

_{DMP}corresponding to the maximum frequency of the generated sinusoidal signal f

_{Cmax}).The volume of the smallest and largest sectors of the unit's permanent memory 5 is determined by sootvetstvenno. In General, the distribution of codes of sampling a sinusoidal signal in the address space of the unit's permanent memory 5 is performed as follows. The address space of the unit's permanent memory 5 is divided into two equal parts (i.e., in half). In one half of the address space of the unit's permanent memory 5 is stored codes 1/2 period of the sinusoidal signal with the highest number of points in the sample period sinusoidal signal (n

_{Dmah}the length of this largest sector is n

_{Dmah}/2). The remaining (second) half of the address space of the unit's permanent memory 5 is also divided in half; the length of each half is equal to 1/4 of total address space of the unit's permanent memory 5. In the first half (equal to 1/4 of total address space of the unit's permanent memory 5) stored codes discretized sinusoidal signal with the number of sampling points for the period of a sinusoidal signal of n

_{D}and 2 times less n

_{Dmah}(i.e., n

_{Dmah}/2). The second half (1/4 of all the address space of the unit's permanent memory 5) again divided in half: the first half (1/8 of the address space of the unit's permanent memory 5) stored codes discretization for sirovina (1/8 of the address space of the unit's permanent memory 5) again divided in half: one half (equal to 1/16 of the address space of the unit's permanent memory 5) stored codes 1/2 sampling period of the sinusoidal signal with the number of sampling points for the period of a sinusoidal signal of n

_{Dmah}/8, and the second half (equal to 1/16 of the address space) is divided in half again and so on, as a result, the capacity of the unit's permanent memory 5 is not increased compared to the capacity of the unit's permanent memory of the prototype. In this case, if the maximum number of sampling points for the period of the sinusoidal signal is equal to 2

^{k}the capacity of the unit's permanent memory 5 will be equal to 2

^{k}. An example of the arrangement of sectors in the address space of the unit's permanent memory 5 for the number of points sampling rate from 16 to 256 shown in Fig. 2.It is easy to see that with the described method of storing codes of sampling a sinusoidal signal state senior address input of the unit's permanent memory 5 remains static regardless of the frequency of the generated sinusoidal signal f

_{WITH}. State senior address input of the unit's permanent memory 5 determines which part (half) of the address space of the unit's permanent memory 5 is read codes sampling a sinusoidal signal. In the process of generating a sinusoidal signal state senior address input of the unit's permanent memory 5 remains static. Note also that with the minimum number of points discretes who should remain static, resulting in the output block of the flash memory 5 is constantly present code corresponding to a minimum (i.e., 000. . . 000), or, on the contrary, the maximum (i.e., 111. . . 111) the code value of the sample rate. The waveform at the output of digital-to-analogue Converter 9 is formed due to the fact that during one half period of the generated output signal code of the unit's permanent memory 5 is inverted, and during the second half of the period is not inverted.With this method of storing codes of sampling a sinusoidal signal and restore sinusoidal signal according to the instantaneous values while maintaining the quality of the generated sinusoidal signal frequency range generated sinusoidal signal is significantly increased, and the capacity of the unit's permanent memory 5 in comparison with the prototype remains unchanged. Thus, the proposed device is less demanding time components and does not require permanent memory blocks larger (compared to the prototype) capacity, which is important for the generator of sinusoidal signals with a wide range of generated frequencies: since the capacity of integrated circuits ROM with the small sampling time addresses (i.e., the 1 watt per case and more for the domestic chip ROM), and improving the quality sinusoidal signal is achieved by increasing the number of sampling points n

_{D}for the period of the sinusoidal signal, it makes sense possible a more efficient use of address space block permanent memory 5. Otherwise you have to use chips ROM larger (or multiple chip ROM), and therefore, the inevitable increase in the power consumed by the unit's permanent memory 5, and the mass and deterioration of characteristics of the device as a whole. More efficient use of address space block permanent memory 5 is stored codes discretization only for 1/2 of the period of the sinusoidal signal, so you can put in the address space of the unit's permanent memory 5 codes sample rate for different numbers of sampling points for the period of the sinusoidal signal, which, in turn, makes the switching frequency of the counter 3 is equal to the sampling frequency f

_{D}by reducing, thus, the maximum frequency, which is operated by the circuit elements of the device, in n

_{Dmah}/n

_{DMP}times in comparison with the prototype, and hence to increase the maximum frequency of the generated sinusoidal signal

_{Max}in soo the project for a signal control unit switches code sample 8. The inputs of the switch 6 receives the codes from the output of the counter 3, and the control inputs of the switch 6 - control code output from the control unit 11. The code on the control inputs of the switch 6 is set by the control unit 11 so that the input control unit switches code sample 8 connects the discharge of the counter 3 with the number (N+1), where N is the number of bits of the counter 3 which are connected with inputs of the unit's permanent memory 5 (the minimum number corresponds to the low order counter 3). I.e., the input unit control switch 8 is connected to the next most senior category of the counter 3, United at the moment through the switch 4 to the address input of the unit's permanent memory 5. It is obvious that the frequency of the pulses at the output of the counter 3 with the number (N+1) 2 times lower than the frequency of the pulses at the output number N. thus, the state transition signal control unit switches code sample 8 once during the period of the generated sinusoidal signal. The number n in this case can be defined as N= log

_{2}(n

_{j}/2)= log

_{2}(n

_{j})-1, where n

_{j}- the number of sampling points for the period of the sinusoidal signal for the j-th sector.Digital code (code dis is toanalogue Converter 9. D / a Converter 9 converts the digital code outputs of block switches code sample 8 to the inputs of digital-to-analogue Converter 9, the analog signal. Because the state of the input control unit switches code sample 8 is changed once during the period of the generated sinusoidal signal during one half period of the generated sinusoidal signal to the input of digital-to-analogue Converter 9 is fed straight line, but during the second half of the period of the generated sinusoidal signal is inverted code from the output of the unit's permanent memory 5. And during the first and during the second half of the period of the generated sinusoidal signal from the unit's permanent memory 5 are read the same codes of sampling a sinusoidal signal, the formation of a sine wave is performed by inverting the code sample.Switching between the outputs of the unit's permanent memory 5 and the unit of the inverter 7 is a block switches code sample 8. Output d / a Converter 9, and thus is formed a stepped sine wave, the form of which depends on the number of sampling points for the period is;2) or square wave (with n

_{D}= 2). Filter low frequency 10 suppresses side components of the spectrum of the generated signal (i.e., high-frequency harmonics that are present in the spectrum of the output signal digital to analogue Converter). Thus, at the output of the LPF 10 is formed sinusoidal signal with frequency f

_{WITH}is determined by the frequency f

_{G}generator of rectangular pulses of fixed frequency 1, the division ratio of the frequency of k

_{D}the controlled frequency divider 2, managed by the control unit 11, and the number of sampling points for the period of a sinusoidal signal of n

_{D}that is set by the control unit 11 using the unit switches 4, switching the younger the address inputs of the unit's permanent memory 5

f

_{WITH}= f

_{G}/k

_{D}n

_{D}, (11)

where f

_{WITH}the frequency of the generated sinusoidal signal; f

_{G}- frequency rectangular pulses generated by the generator of rectangular pulses of fixed frequency 1; k

_{D}the division ratio of the frequency of the controlled frequency divider 2; n

_{D}- the number of sampling points for the period of the sinusoidal signal. A sinusoidal signal generator to electrom the oscillations of fixed frequency, controlled frequency divider, a counter, and the unit's permanent memory and series-connected digital-to-analog Converter and filter low frequency, is connected to a managed frequency divider control unit, characterized in that it is equipped with block switch block switch codes sampling unit inverters and switch, and some of the inputs of the block of switches connected to the outputs of the counter (except for the output of the most significant bit of the counter), and the second input unit switches to the outputs of the control unit, the input control unit switches connected to the outputs of the control unit, the outputs of the block of switches connected to inputs of the unit's permanent memory (with the exception of the older unit's permanent memory); one unit switches codes discretization connected to the outputs of the unit's permanent memory, and other inputs unit switches code sample with the outputs of the unit inverters, the outputs of block switches codes discretization connected to inputs of digital-to-analog Converter, the input unit inverters are connected to the outputs of the unit's permanent memory, the input control unit switches codes discretization connected to the output of the comş the control unit, senior unit's permanent memory connected to the control unit.

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1 dwg, 1 tbl