The receiver of signals of satellite radio navigation systems

 

(57) Abstract:

The invention relates to radio navigation systems, particularly to a receiver of signals of satellite radio navigation systems GPS and GLONASS frequency band L1. The receiver includes a radio frequency Converter, the N-channel digital correlator, the transmitter, the driver signals a time stamp, each channel digital correlator contains the correlation processing module, the digital carrier generator and the digital code generator. Each of the digital generator carrier and code contains accumulating adder and the forming unit counts. Each of the accumulative adders each of the digital generator carrier and code executed in the form of high frequency and low frequency cumulative modules, and includes series-connected output combinational adder and the output register phase. When this high frequency cumulative module contains serially connected first register code frequency, the first combinational adder and the first register phase, the output of which is connected to the second input of the first combinational adder and to the first input of the output combinational adder. Low frequency cumulative module is gistr phase, the output of which is connected to the second input of the second combinational adder, and the output of the corresponding high-order bits to the second input of the output combinational adder. The clock input of the output register phase and the clock input of the first register phase high frequency cumulative module form a clock input is accumulating adder - clock input of the corresponding digital generator. The clock input of the second register phase low frequency cumulative module forms an additional input of the digital generator. Informational inputs registers code frequency high frequency and low frequency cumulative modules form the control inputs accumulating adder. The outputs of the respective bits of the output register phase form the output generated by the reference signal digital generator. The receiver also introduced shaper additional low-frequency clock signals for the digital carrier generator and the digital code generator, made in the form of the frequency divider and its associated register reference phase, and the first and second outputs of the low-frequency clock signals of the frequency divider are connected respectively with additional digital inputs generator is not what tatom is reduced power consumption. 5 Il.

The invention relates to the field of navigation, and specifically to the equipment users operating on the signals of satellite navigation systems (SNS) GLONASS (Russia) and GPS (USA) frequency range L1, forming signals to determine the location and signals high-precision time stamp, tied to the timeline SRNS.

The equipment users working on the GLONASS signals [1] and GPS [2] , is used to determine the coordinates (latitude, longitude, altitude) and velocity of the moving object, and for generating signals high-precision timestamps. The use of signals with frequency range L1 c code modulation C/a codes - codes "standard accuracy - provides a "standard" position accuracy.

The main differences between GLONASS and GPS are using different, though adjacent frequency bands, using different pseudo-random modulation codes, and the use of, respectively, the frequency and code division signals of different satellites. So, in the GPS frequencies L1 satellites emit modulated to different pseudo-random code signals on the same carrier frequency is slichnih bearing (lettered) frequencies, lying in adjacent frequency domain. For the frequency range L1 zero lettered frequency f0= 1602 MHz, and the interval between lettered frequencies f = 0,5625 MHz. Distribution lettered frequencies among functioning GLONASS satellites is set by the almanac transmitted in the frame of official information. Lettered frequencies are entered in accordance with the "Interface control document" [1] . Currently used lettered frequencies of "0" to "12" in the further transition to the lettered frequencies "-7" - "4".

Despite the differences between GPS and GLONASS, their proximity to destination, ballistic build satellites constellation and the used frequency range allows you to design the equipment working simultaneously on the signals of the two systems. The achieved result is to increase the reliability, validity and accuracy of the positioning, in particular, due to the possibility of working constellations with the best values of the geometrical factors [3, S. 160] .

Known, see , for example, [3, 158-161 C., Fig. 9.8] , the single-channel receiver user equipment operating on signals from GPS and GLONASS frequency diperbaiki signals and means for computing. Part of the radio-frequency Converter includes a frequency divider ("diplexer") performing frequency division of GPS and GLONASS, bandpass filters and low-noise amplifiers channels GPS and GLONASS, the switch serving to signal input of the first mixer GPS or GLONASS, the switch connecting the reference input of the first mixer signal of the first local oscillator to convert GPS or GLONASS. In the receiver by a corresponding shaping of the frequency of the first local oscillator of the first intermediate frequency is constant for GPS and GLONASS and the receiver path including the second mixer and the analog-to-digital conversion is implemented as common to these signals. Part of the funds for correlation processing signals includes a multiplexer with a permanent storage device, digital generator lettered frequencies, the generator of pseudo-random codes and digital correlator. The receiver is implemented multiplex (alternate) mode according to the signals from both GPS and GLONASS. The receiver allows you to implement parallel (multi-channel) signal processing GPS and GLONASS, which increases the time required to obtain navigatio the belt and reception of multi-channel (parallel) correlation processing of GPS and GLONASS, in particular, the frequency range L1 Functionally finished part of a device, receipt and correlation processing of GPS and GLONASS frequency band L1, includes radio frequency Converter N-channel digital correlator, the transmitter, and the driver signals a time stamp. The clock input of the driver signals a time stamp associated with a clock output of the RF Converter. The output of the measuring gate driver signals a time stamp associated with the corresponding inputs of each channel N-channel digital correlator. The driver signals a time stamp and channel N-channel digital correlator connected by bus to exchange data with the computer. Each channel N-channel digital correlator contains the correlation processing module and associated controlled transmitter digital generator carrier and code. Using correlation processing module, transmitter and digital generators carrier and code is highlighting the information contained in the received signal. The allocation information is performed using a closed digital tracking systems correlation processing, the so-called "schemes tracking naively signals and subsequent correlation than copies of the actual signals. When the managed computer digital generator carrier and code generate the necessary reference signals.

For the purposes of digital correlation processing of signals, including signals SRNS-driven evaluator digital generators are based on the accumulative adders implementing a method of direct digital synthesis frequency [5, 75-76 C., Fig. 3.12; 6, 90-92 C., Fig. 34] . Direct control from the transmitter is implemented in such generators, provides the required accuracy of formation of the reference signals used in the circuits of the track carrier" measuring the Doppler shift, or "schemas tracking delay, measuring the shift of the reference code regarding code of the processed signal [6, S. 87-90, Fig. 33] .

Closest to the claimed receiver is known to the receiver GPSr [7] , receipt and multichannel correlation processing of GPS and GLONASS frequency band L1, in which the channels of the digital correlator as generators of the carrier and code applied to managed digital generators, made on the basis of accumulating adder. The signal receiver GPSr described in [7] , is adopted as a prototype.

Each channel N-channel digital correlator receiver-prototype contains associated with computer bus communication module correlation processing, digital carrier generator and the digital code generator. Each of these generators has related with computer bus interchange corresponding accumulating adder and the corresponding forming unit counts, connected to the output data accumulating adder. The outputs of the reference signal digital generator formed by the corresponding outputs of their accumulative adders, connected with the control inputs m is plavusa adders, and the measuring inputs of the gates formed by the measuring inputs of the gates blocks the formation of the samples, respectively connected with a clock input and the input of the measuring gates correlation processing module. Signal inputs, a clock input and the input of the measuring gates correlation processing module form the corresponding inputs of the channel N-channel digital correlator.

In the receiver-prototype radio frequency Converter includes an input unit, the block of the first frequency conversion of the signals of GPS and GLONASS, the first and second channels of the second frequency conversion of signals respectively GPS and GLONASS, as well as the signal of clock and heterodyne frequencies. The input unit of the radio-frequency Converter performing pre-filtering the input signals of GPS and GLONASS is performed on the basis of the bandpass filter. Block of the first frequency conversion signal of the radio frequency Converter performing the first frequency conversion of the signals of GPS and GLONASS is performed on the basis of the mixer, the mixer uses the signal of the first heterodyne frequency (Fr1). The first and second channels of the second frequency conversion signal, carry out the TRS, mixers and blocks analog-to-digital conversion. Mixers of the first and second channels using, respectively, the second signals (Fr2) and third (FG3) heterodyne frequencies. The output clock signal (clock Fň) unit generating signals of clock and heterodyne frequencies, together with the outputs of the channels of the second frequency conversion of signals comprise a clock signal and outputs the RF Converter.

In the receiver prototype in each channel N-channel digital correlator, the correlation processing module includes a switch input signals, digital mixers, digital demodulator, a programmable delay line, the generator of the reference C/a code, blocks of accumulation and the control register. The reference inputs of digital mixers and generator reference C/a code form the reference inputs of the module. Signal inputs switch input signals to form a signal input module. Clock inputs of blocks accumulation and programmable delay lines form a clock input of the module. The measuring inputs of the gates of the generator of the reference C/a code form the input of the measuring gate module. The outputs of blocks accumulation and input-output data generator reference C/a to the

The receiver prototype works as follows.

Received antenna signals of GPS and GLONASS frequency band L1 arrive at the signal input of the radio frequency Converter, where it is filtered in the bandpass filter of the input unit, is converted by the frequency mixer block of the first frequency conversion of the signals are then separated systems (GPS and GLONASS) in the corresponding channels of the second frequency conversion signal is converted in frequency (the second frequency conversion) and subjected to analog-to-digital conversion, for example the case of double-bit quantization level.

Output RF Converter GPS and GLONASS are received on the corresponding input channel N-channel digital correlator, where they are digital correlation processing. First switch input signals are selected signals to one of the systems - GPS and GLONASS. Then, using digital mixers are the selection signals a particular satellite system chosen and the transfer of the spectrum of these signals at baseband frequencies (at zero frequency), which uses the reference signals generated by the digital carrier generator.

The reference is astate. The digital carrier generator is controlled by the signal transmitter, in particular, the transmitter receives the data code frequency setting increments increment phase at the output of the accumulating adder. Work is accumulating adder is implemented with a sampling frequency determined by the clock frequency Fň. Also in the digital carrier generator with forming unit counts to derive the reference phase of the carrier and the data readout cycles (periods) of the carrier, which with frequency measurement gates Fandgo on the computer.

With outputs digital mixers the processed signals are sent to the signal inputs of the digital demodulators, which carry their correlation comparison with the exact "P" (Punctual) and differential "E-L" (Early-Late) the copies of the relevant reference C/a code (GPS or GLONASS). These copies of the code produced by the programmable delay line, which is under the control of the transmitter (on the signals generated by the control register) changes the interval between the early "E" and later "L" copies of the C/a code from 0.1 to 1 duration symbol C/a code, thus forming narrow discriminator" ("narrow correlator") in the tracking system code, as described, in particular, in [8 - 1 the anal digital correlator generator reference C/a code, receiving this reference clock frequency code 1.023 MHz for GPS or 0,511 MHz for GLONASS. The choice of the type produced by a pseudorandom code sequence is performed on the basis of data from the transmitter via the control register. The formation of the reference clock frequency code is via a digital code generator.

The digital code generator generates the current values of the phase reference clock frequency C/a code (1, 023 MHz for GPS, 0,511 MHz for GLONASS). The digital code generator is controlled by the signal transmitter, in particular, from transmitter data concerning the value of the clock frequency of the code that establishes the discrete increment of the phase at the output of the accumulating adder. Work is accumulating adder is implemented with a sampling frequency determined by the clock frequency Fň. Also in the digital code generator using its forming unit counts to derive reference share code symbol, which frequency measurement gates f and enter in the calculator.

Measuring the gates (signals its own timestamp receiver) is formed in the driver signals timestamp under the action of the clock signal from the output of the block forumini signals, coming from the transmitter, and, if necessary, under the action of external clock signals. In accordance with the measurement gates in the receiver prototype is an internal process synchronization correlation processing and navigation measurements, in particular, is a reference quasiballistic, the phase of the carrier and the number of cycles of the carrier.

The results of correlation comparisons are accumulated in the respective blocks accumulation. Accumulation period equal to the period of C/a code, i.e. 1 MS. The accumulated data is periodically read by a computer, which implements all the algorithms, i.e. algorithms of search signals, tracking the carrier and code processing service information.

As noted above, in the receiver-prototype digital generator carrier and code is executed on the basis of the accumulating adder, which implements the direct digital frequency synthesis with the accumulation of the current phase. The characteristics of the electricity accumulating adder traditional patterns depend on the sampling frequency, the value of which is in the receiver prototype is determined by the clock frequency (F22 MHz), selected on the basis of the spectrum of the processed signal). Almost in the receiver prototype to achieve the objectives of the correlation signal processing digital generator carrier and code must have a high frequency (about 20 MHz) and simultaneously high RES (ten digits) accumulating adder. However, digital generators, carrier and code that uses such high frequency and simultaneously accumulate high RES adders consume increased power, which can be a problem, in particular, to a portable multi-channel receiver signals GPSr designed to operate from self-contained battery power.

Technical problem on which the invention is directed, is the reduction of the power consumption of the receiver signals GPSr. The problem is solved due to new digital generator carrier and code, namely the transition to a dual-frequency digital generators, synthesizing their output signals of two components - high frequency and low frequency, and the synthesis of high frequency components is performed with the sampling frequency of the primary clock frequency Fň, and the low-frequency - sampling rates determined additionally formed when the IR signals of satellite radio navigation systems, containing radio frequency Converter, the input of which forms the signal input of the receiver, the N-channel digital correlator, the signal and clock inputs of each of the channels of which are connected with the corresponding outputs of the radio frequency Converter, calculator, and the driver signals a time stamp, the control input of which is connected by a bus interchange with the transmitter clock input to clock output of the radio frequency Converter, and the output of the measurement gates with inputs measurement gates each channel N-channel digital correlator, each channel N-channel digital correlator contains associated with computer bus communication module correlation processing, the digital carrier generator and the digital code generator, and each of these digital generators contains associated with computer bus interchange accumulating adder and the forming unit counts, information whose input is connected to the output data accumulating adder, the outputs of the reference signals specified digital generators formed by the corresponding outputs of their accumulative adders, connected with the control inputs of the module pair correlation is that adders, and the measuring inputs of the gates formed by the measuring inputs of the gates blocks the formation of counts, are connected, respectively, with a clock input and the input of the measuring gates correlation processing module, a clock input, measurement gates and signal inputs which form the corresponding inputs of the channel N-channel digital correlator, unlike the prototype introduced shaper additional low-frequency clock signals for the digital carrier generator and the digital code generator, made in the form of the frequency divider and its associated register reference phase, and the clock input of the frequency divider is connected to a clock output of the radio frequency Converter, the input of the measuring gates register reference phase is connected to the output of the measuring gate driver signals timestamp output register reference phase is connected by bus to exchange data with the evaluator and the first and second outputs of the low-frequency clock signals of the frequency divider are connected respectively with the additional inputs of the digital carrier generator and the digital code generator of each channel N-channel correlator, in each of these digital generators nakaplivaetsya sequentially output combinational adder and the output register phase, moreover, cumulative frequency module includes serially connected first register code frequency, the first combinational adder and the first register phase, the output of which is connected to the second input of the first combinational adder and to the first input of the output combinational adder, low frequency cumulative module contains serially connected second register code frequency, the second combinational adder and the second register phase, the output of which is connected to the second input of the second combinational adder, and the output of the corresponding high-order bits to the second input of the output combinational adder, the clock input of the output register phase and coupled with it the clock input of the first register phase high frequency cumulative module form a clock input is accumulating adder - clock input digital generator, the clock input of the second register phase low frequency cumulative module forms an additional input digital generator, the information inputs of the first and second registers code frequency high frequency and low frequency cumulative modules form respectively first and second control inputs accumulating adder, tie least significant bits of the second register phase low frequency cumulative module form the output data accumulating adder, linked through the forming unit counts with the evaluator, and the outputs of the respective bits of the output register phase form the output of the reference signal digital generator connected with the corresponding reference input of the correlation processing module channel N-channel digital correlator.

The essence of the invention, the possibility of its implementation, and industrial applications are illustrated by the drawings, is shown in Fig. 1-5, where:

in Fig. 1 shows a structural diagram of the proposed receiver SRNS in this example implementation;

in Fig. 2 shows the generalized block diagram of a digital carrier generators and code of the proposed receiver SRNS in this example implementation;

in Fig. 3 shows a structural diagram of one channel of the N-channel digital correlator of the proposed receiver SRNS in this example implementation, illustrating the module correlation processing;

in Fig. 4 shows a structural diagram of the radio-frequency Converter of the proposed receiver SRNS in this example implementation;

in Fig. 5 shows graphs illustrating the principle of work is emy signal receiver SRNS in this example implementation includes, see Fig. 1-4, the radio-frequency Converter 1, the input of which forms the signal input of the receiver, the N-channel digital correlator 2, containing N channels 3 (31, 32, . . . , 3N), signal and clock inputs are connected to respective outputs of the radio-frequency Converter 1, the transmitter 4, the associated bus communication with each of the N channels 3 (31, 32, . . . , 3N), and the imaging unit 5 signals timestamp, the control input of which is connected by a bus to exchange data with the computer 4, a clock input connected to a clock output (output clock signal Fň) radio-frequency Converter 1, and the output of the measurement gates (f and) with the measuring inputs of the gates of each of the N channels 3 (31, 32, . . . , 3Ndigital correlator 2.

Each of the N channels 3 (31, 32, . . . , 3Ndigital correlator 2 lists evaluator 4 bus communication module 6 correlation processing, digital carrier generator 7 and the digital code generator 8. The output of the reference signals of the digital carrier generator 7 and the output reference signals of the digital code generator 8 connected to respective reference inputs of the module 6. Clock inputs of digital gene is Odom measurement gates of module 6. Signal inputs module 6, as well as its clock input and the input of the measuring gates form the corresponding inputs of channels 3 (31, 32, . . . , 3Ndigital correlator 2.

The inventive receiver GPSr contains shaper 9 additional low-frequency clock signals for the digital carrier generator 7 and the digital code generator 8. The imaging unit 9 contains a frequency divider 10 and its associated register 11 reference phase. The clock input of the frequency divider 10 is connected to a clock output (output clock signal Fň) radio-frequency Converter 1. The input of the measuring gates of the register 11 is connected to the output of the measuring gates (f and) shaper 5 signals timestamp. The output of the register 11 is connected to the bus data exchange with the computer 4. The outputs of the first (F1) and second (F2) additional low-frequency clock signals of the frequency divider 10 is connected with additional inputs, respectively, of the digital carrier generator 7 and the digital code generator 8 of each channel 3 (31, 32, . . . , 3Ndigital correlator 2.

The digital carrier generator 7 and the digital code generator 8 in the aggregate (Fig. 2) contain accumulating adder 12 and block 13 formirovalas 4, the information input unit 13, the formation of the times connected to the output data accumulating adder 12.

Outputs the generated reference signals of the digital carrier generator 7 and the digital code generator 8 is formed corresponding outputs of their accumulative adders 12. These outputs are connected to respective reference inputs of the module 6. Clock inputs of digital generators 7 and 8 is formed by a clock input their accumulative adders 12. These inputs are connected to a clock input of the module 6. The measuring inputs of the gates digital generators 7 and 8 are formed by the measuring inputs of the gates blocks 13 of formation samples. These inputs are connected to the input of the measuring gate module 6.

Accumulating adder 12 of each of the generators 7 and 8 are in the form of high-frequency 14 and the low-frequency 15 cumulative modules, and contains serially connected output combinational adder 16 and the output register phase 17. High-frequency 14 and the low-frequency 15 cumulative modules are well-known scheme of a digital synthesizer that implements the method of direct digital frequency synthesis, see , for example, [5, S. 50-51, Fig. 2.13] .

In each of the generators 7 and 8 vysokochastotnyye the adder 19 and the first register phase 20, the output of which is connected to the second input of the first combinational adder 19 and to the first input of the output combinational adder 16. Low frequency cumulative module 15 contains serially connected second register code frequency 21, the second combinational adder 22 and the second register phase 23, the output of which is connected to the second input of the second combinational adder 22, and the output of the corresponding high-order bits to the second input of the output combinational adder 16. The clock input of the output register phase 17 and connected with it the clock input of the first register phase 20 cumulative frequency module 14 form a clock input is accumulating adder 12 to the clock input of the corresponding digital generator 7, 8. The clock input of the second register phase 23 low frequency cumulative module 15 forms an additional input of the corresponding digital generator 7, 8. The information inputs of the first 18 and second registers 21 code frequency 14 and the low-frequency 15 cumulative modules form respectively first and second control inputs accumulating adder 12, connected by a bus to exchange data with the computer 4. The outputs of the bits of the output register phase 17 and outputs the output data accumulating adder 12, connected to the information input unit 13 forming samples whose output via the bus data exchange associated with the computer 4. The outputs of the respective bits of the output register phase 17 is formed in each of the digital generators 7, 8 output generated reference signals.

Digital generators 7 and 8 to the clock input of the first register phase 20 cumulative frequency module 14, and the clock input of the output register phase 17 receives the high frequency clock signal frequency Fň. To the clock input of the second register phase 23 low frequency cumulative module 15 receives the low-frequency clock signal, namely, the generator 7 - low-frequency clock signal of frequency F1, and the generator 8 - low-frequency clock signal of frequency F2. High-frequency Fň and low frequency F1, F2 clock signal synchronous, which is provided by the formation of a low-frequency clock signals F1 and F2 of the clock signal Fň by dividing the frequency Fň in the frequency divider 10 of the imaging unit 9.

In practical circuits combinational adders 16, 19, 22 can be made under the scheme combinational adder serial transfer, described, for example, in [11, S. 523-536, Fig. 6.96, 6.97] that is before inim transfer, described, for example, in [11, S. 523-536, Fig. 6.100] . Registers 17, 18, 20, 21, 23 can be made in the form of registers memory-based triggers (e.g., D-flip-flops) that can record, store and read data in parallel binary code, see , e.g., [11, S. 348-354, Fig. 5.85] . In practical circuits the registers 18 and 21 of the code frequency in addition to these information inputs are the inputs of the record (Fig. 2 is not shown), which writes the input data to these registers. In practical circuits, registers 17, 18, 20, 21, 23 can have inputs reset (Fig. 2 is not shown), which in the initial work can be submitted Abdoulaye signal that sets the registers in the initial (zero) state.

The coincidence of its generalized structural diagram (Fig. 2) digital generator bearing 7 and code 8 different specific execution units 13 of formation samples, razryadnitsy 14 and the high-frequency low-frequency 15 cumulative modules, as well as the specific values of additional clock frequencies F1 and F2 used low frequency cumulative modules 15. So, in the digital carrier generator 7 block 13 of formation samples contains a register form in accordance with m sledovatelno United cycle counter and the register, forming in accordance with the measurement data strobes counting the number of cycles (periods) of the bearing, see , for example, [7, Fig. 5, the elements 41, 42, 44] . The digital code generator 8 block 13 of formation samples contains a register form in accordance with the measurement data strobes reference share code symbol, see , for example, [7, Fig. 5, the element 45] . In the digital carrier generator 7 items cumulative frequency module 14 (the first register code frequency 18, the first combinational adder 19, the first register phase 20), the output combinational adder 16 and the output register phase 17 is made of K1bit, and elements of the low-frequency cumulative module 15 (the second register code frequency 21, the second combinational adder 22, the second register phase 23) is made TO a2bit, where K2>K1for example, K2= 25, K1= 5. The digital code generator 8 similar items cumulative frequency module 14, and output combinational adder 16 and the output register phase 17 is made TO3bit, and elements of the low-frequency cumulative module 15 is made TO4bit, where K4>3for example, K4= 23, K3= 2. Work low Akopian additional low-frequency clock signal F1. This signal is generated by the imaging unit 9 additional low-frequency clock signal by dividing the main clock frequency Fň by a factor of k1for example k1= 10. Work low frequency cumulative module 15 digital code generator 8 is performed with a frequency depending on the second additional low-frequency clock signal F2. This signal is generated by the imaging unit 9 by dividing the main clock frequency Fň by a factor of k2for example k2= 20. Practically in this case, the second clock frequency F2 may be formed from the first F1 by dividing it into two.

In the inventive receiver signals GPSr module 6 correlation processing each of the channels 3 (31, 32, . . . , 3Ndigital correlator 2 can be implemented in accordance with well-known, see , for example, [7, Fig. 4] , the block diagram. In accordance with this scheme module 6 correlation processing in this example implementation includes (Fig. 3) switch 24 input signals, blocks 25, 26, 27 and 28 of the accumulation register 29 control, generator 30 of the reference C/a code (GPS and GLONASS), a programmable delay line 31, the digital mixers 32 and 33, respectively sinpas is the R blocks 25-28 accumulation, input-output data register 29 control and generator 30 of the reference C/a code connected by bus to exchange data with the computer 4. The first ("GPS") and the second ("GLONASS") signal inputs of the switch 24, forming a signal input module 6 (signal input channel 3) connected to the respective signal outputs of the radio-frequency Converter 1. Clock inputs of blocks 25-28 accumulation and programmable delay lines 31, forming a clock input of module 6 (clock input channel 3) connected to the clock output of the radio-frequency Converter 1. The inputs of the measuring gate generator 30 of the reference C/a code forming the input of the measuring gate module 6 (the input of the measuring gate channel 3) connected to the measuring output of the gate driver 5 signals timestamp. The control input of switch 24 is connected to the first output register 29 management. The second and third outputs of the register 29 control connected respectively to the control input of the programmable delay line 31 and the first control input of the generator 30 of the reference C/a code. The output of switch 24 is connected with the first inputs of digital mixers 32 and 33, the second inputs of which forming the first reference input module 6 connected to the output operowych demodulators 34, 35 and 36, 37 respectively. Second input of the digital demodulator 34, 37 and 35, 36 are connected with the corresponding outputs of the programmable delay line 31 outputs the exact "P" (Punctual) and differential "E-L" (Early-Late) copies of the reference C/a code. Signal input of the programmable delay line 31 is connected to the output of generator 30 of the reference C/a code forming the C/a code GPS or GLONASS depending on the commands received from the computer 4. The second control input of the generator 30 of the reference C/a code, forming a second reference input module 6 connected to the output of the reference signals of the digital code generator 8. The digital outputs of the demodulators 34-37 are connected respectively to the inputs of blocks 25-28 accumulation.

In the present receiver signal SNS RF Converter 1 can be implemented in accordance with well-known, see , for example, [7, Fig. 3] , the block diagram. In accordance with this scheme the RF Converter 1 in this example implementation includes (Fig. 4) the input unit 38 connected to its output unit 39 of the first frequency conversion of the signals of GPS and GLONASS, and also connected to the output of block 39 of the first 40 and second 41 channels of the second frequency conversion of signals respectively GPS and GLONASS. To the entrance Blackie block 42 generating signals of clock and heterodyne frequencies. The channel 40 of the second frequency conversion signal (the channel of the second frequency conversion of GPS signals) contains serially connected filter 43, the inlet of which is the entrance channel, the mixer 44 and the block 45 analog-to-digital conversion, the output of which forms the output of the channel 40 to output the converted GPS signals to radio frequency Converter 1. The channel 41 of the second frequency conversion signal (the channel of the second frequency conversion of signals GLONASS) contains serially connected filter 46, the inlet of which is the entrance channel, the mixer 47 and the block 48 analog-to-digital conversion, the output of which forms the output of the channel 41 to output the converted signals GLONASS RF Converter 1. In the radio frequency Converter 1, the input unit 38, a crucial task pre-filtering the input signals of GPS and GLONASS frequency band L1 contains at least one bandpass filter; block 39, which solves the problem of the first frequency conversion of the signals of GPS and GLONASS contains at least one mixer; mixer 44, 47 channels 40, 41 includes frequency converters and amplifiers, for example amplifiers with adjustable gain; blocks 45, 48 analog-to-digital p is antofalla level. Block 42 generating signals of clock and heterodyne frequencies contains tunable synthesizers frequency based on a voltage-controlled oscillators (VCO) with a phase-locked loop circuits (PLL) that operates from a single common reference oscillator. In a block 42, if necessary, may include switchable dividers (multipliers) frequencies, providing in conjunction with the frequency synthesizer formation of the desired grid of clock and heterodyne frequencies. When the output signal of the first heterodyne frequency (Fr1") unit 42 coupled to the reference input of the block 39, formed by the reference input of the corresponding mixer output signals of the second ("Fr2") and third ("Fr3") heterodyne frequency unit 42 is connected with the control inputs of the mixers 44, 47 channels 40, 41. The outputs of the channels 40 and 41, which signal outputs of the radio-frequency Converter 1 ("GPS" and "GLONASS"), connected to respective signal inputs of channels 3 (31, 32, . . . , 3Ndigital correlator 2. The output signal of the clock frequency ("Fň") block 42, which is clocked by the output of the radio-frequency Converter 1, is associated with the respective clock inputs of channels 3 (31, 32, . . . , 3N) digitally the I additional low-frequency clock signals for the digital carrier generator 7 and the digital code generator 8 (Fig. 1). The input control signal ("Uy") unit 42 is designed to signal, carrying out, if necessary, reconstruction of block elements 42 - synths and factors (multipliers) frequency. The input control signal is connected, for example, to the computer 4 through the bus interchange (not shown).

The imaging unit 5 signals timestamp forming in the claimed measuring receiver gates (signals its own timestamp of the receiver), in accordance with which the internal synchronization of processes, correlation processing and navigation measurements, in the simplest case can be made, for example, well-known scheme [7, Fig. 1, blocks 5-8] in the form of a counter, the period register and shaper signal loading period. The first counter input which is the input clock signal Fň, connected to the first input of the shaper signal loading period, the output of the meter, which is the output measurement gates f and the (output its own timestamp receiver) is connected to the second input of the shaper signal loading period, the output of the signal shaper boot period connected with a second input of the counter, the third counter input coupled to the output period register, I is facilitale 4, record the number that determines the value of the repetition period of the generated signals timestamp measuring gates f and. This number at the time set by the overflow signal of the counter, using the shaper signal loading period is loaded into the counter. Boot time is synchronized clock signal Fň received at the first input of the shaper 5 with a clock output of the radio-frequency Converter 1. After loading the counter is filled with the pulses of the clock signal until, until you overflow. When the overflow output of the counter is a new signal timestamp - new measuring f and the gate, after which the process repeats.

Components of the radio-frequency Converter 1 elements, nodes, and blocks are known elements, nodes, and blocks used in the technique of reception and correlation signal processing GPSr. So, the input unit 38 of the radio-frequency Converter 1 can be implemented as a bandpass ceramic filter; block 39 of the first frequency conversion signal can be implemented on the basis of a standard mixer, such as a chip type MS MOTOROLA; filters 43, 46 can be implemented as a bandpass subject to the gain can be realized, for example, using chip type UPC2753 companies NEC; blocks 45, 48 analog-to-digital conversion can be implemented using dual Comparators, for example chipset type MAX 962 company MAXIM. Block 42 generating signals of clock and heterodyne frequencies can be implemented using standard elements, such as chip type TEMPUS-LVA MOTOROLA (reference oscillator), chip type MS MOTOROLA (VCO) and chip type LMX2330 company NATIONAL SEMICONDUCTOR (block PLL) to implement managed frequency synthesizers, chip type MS, MS MOTOROLA for the implementation of frequency dividers.

The transmitter 4 is implemented as a microcomputer standard configuration contains the standard elements of a processor, controller, online, permanent, programmable permanent storage devices, interfaces, ports, I / o data. The function calculator 4 is carried out according to standard algorithms navigation transmitter multi-channel receiver signals SRNS.

Digital correlator 2 with the considered structure of the channels 3, i.e., modules 6 correlation processing, digital carrier generators 7 and code 8, and the imaging unit 5 rings is ideal VLSI (large specialized integrated circuits using libraries of standard elements, for example, SAMSUNG ELECTRONICS firms or SGS TOMSON.

The work of the proposed receiver GPSr consider the example of receiving and processing GPS signals and GLONASS modulated codes standard precision (C/a codes) in the frequency range L1, for the case when the signals of GLONASS signals with lettered frequencies of "0" to "12" or "-7" - "4", established in accordance with [1] .

The inventive receiver GPSr works as follows.

Received antenna signals of GPS and GLONASS frequency band L1 arrive at the signal input of the radio-frequency Converter 1, i.e., to the input of the input unit 38 (Fig. 1 and 4). The signals of the GPS L1 band occupied by the frequency band (1571, 328 - 1579, 512) MHz width F = 8,184 MHz (four lobes in the spectrum of the signal in both directions from the carrier to implement the "narrow correlator"), and the signals of the GLONASS L1 band occupied by the frequency band (1599, 956 - 1610, 794) MHz width F = 10,838 MHz (case lettered frequencies of "0" to "12") (1596, 019 - 1606, 294) MHz width F = 10,2755 MHz (case lettered frequencies "-7" - "4"). The input unit 38 transmits on its output signals of GPS and GLONASS specified frequency, i.e. the frequency range (1571, 328 - 1610, 794) MHz. From the output of block 38 GPS and GLONASS fed to the input of block 39 of the first frequency conversion signal is homeland frequency (Fr1) formed in the block 42. When receiving signals of GLONASS with lettered frequencies of "0" to "12" is the first heterodyne frequency Fr1(l)= 1412 MHz, the reception signals of GLONASS with lettered frequencies "-7" - "4" is the first heterodyne frequency Fr1(2)= 1408 MHz. Change the values of heterodyne frequencies generated in block 42, is carried out on the control signal ("Uy"), coming for example from the computer 4. In the result of the first conversion frequency GPS signals occupy the frequency band (159, 328 - 167, 512) MHz in the case lettered frequencies of "0" to "12" and the band (163, 328 - 171, 512) MHz in the case lettered frequencies "-7" - "4". The GLONASS signals occupy and consequently bandwidth (187, 956 - 198, 794) MHz for the first time and the bandwidth (188, 019 - 198, 294) MHz for the second case. Converted to the first intermediate frequency signals of GPS and GLONASS are received at the inputs of the first 40 and second 41 channels of the second frequency conversion of signals, i.e., to the inputs of filters 43 and 46 (Fig. 4). Each of these filters provides bandpass filtering signals corresponding system, namely the filter 43 - filtering of GPS signals in the frequency range (159, 328 - 171, 512) MHz, and the filter 46 - filtering GLONASS signals in the frequency range (187,956 - 198,794) MHz. Output filter adowanie frequency. For the second frequency conversion of GPS signals is used, the signal of the second heterodyne frequency (Fr2) formed in the block 42. In the first case - if you receive a lettered frequencies of "0" - "12" - this frequency is equal to Fr2(l)= 179 MHz, and in the second case - if you receive a lettered frequencies "-7" - "4" - this frequency is equal to Fr2(2)= 183 MHz. For the second frequency conversion of the signals of the GLONASS signal is provided to a third heterodyne frequency (Fr3) formed in the block 42, for example, by dividing into eight frequency signal of the first heterodyne frequency. Thus, in the first case, Fr3(1)= 1/8Fr1(l)= 176,5 MHz, and in the second case, Fr3(2)= 1/8Fr1(2)= 176 MHz. In the result of the second frequency conversion GPS signals occupy the frequency band (13,99 - 22,17) MHz for the first time and the bandwidth (10,99 - 19,17) MHz for the second case, and the GLONASS signals occupy the frequency band (11,46 - 22,29) MHz for the first time and the bandwidth (12,02 - 22,29) MHz for the second case. Then the GPS signals and GLONASS amplified using amplifiers with adjustable gain, included in the mixers 44 and 47, and then subjected to analog-to-digital conversion in blocks 45 and 48. Analog-to-digital conversion can be in dvukhbitovogo MAX 962 company MAXIM. In this analog-to-digital conversion signals generated by the blocks 45 and 48, the characteristic is the presence of a carrier, which is removed later in the channels 3 (31, 32, . . . , 3Ndigital correlator 2, namely in the digital mixers 32 and 33 module 6 correlation processing (Fig. 3).

From the outputs of the channels 40 and 41 GPS and GLONASS are received on the first ("GPS") and second (GLONASS) signal inputs of each of the channels 3 (31, 32, . . . , 3Ndigital correlator 2 (Fig. 1 and 3), i.e. on the respective signal inputs of the modules 6 correlation processing. At clock inputs of channels 3 (clock inputs of the modules 6, digital generator bearing 7 and code 8) receives the signal of the main clock frequency Fň. This clock frequency determines the frequency temporal sampling rate for operations of the digital correlation signal processing.

The signal processing clock frequency Fň performed in block 42 of the radio-frequency Converter 1, for example from the signal of the third heterodyne frequency by dividing this frequency by eight (Fň= Fr3/822 MHz) with the subsequent formation of signal type "meander". The value of the clock frequency Fň and the value of frequency bands converted to the relational processing of signals without loss of navigation information.

Channels 3 (31, 32, . . . , 3Ndigital correlator 2 is a digital correlation processing of signals N visible satellites of the GPS and GLONASS in combination determined by commands received from the computer 4. During correlation processing is determined by the temporal position of the peaks of the correlation functions of the signals corresponding to N satellites are determined by the radio navigation parameters used in the calculations of the location. This counts quasiballistic, the phase of the carrier and the number of cycles of the carrier produced in accordance with the measurement gates (f and) coming from the output of the shaper 5 signals timestamp. Frequency measurement gates (1 - 10 Hz) is set by the signal on control input shaper 5 from the transmitter 4. Correlation processing of signals in the channel 3 digital correlator 2 is module 6 correlation processing under the influence of the reference signals generated by the digital generator bearing 7 and code 8. Correlation processing of signals is controlled by the computer 4. It performs the following operations.

The switch 24 is in the command generated by the register 29 control n ONES) will be handled in this module 6. The digital carrier generator 7 produces a digital value of the phase of the carrier frequency of the reference signal used in the implementation processes quadrature "multiply" with an input signal into a digital mixers 32 and 33. Digital mixers 32 and 33 provide the selection signal of this character (GLONASS) signal or a given satellite (GPS) and the transfer of the spectrum of this signal on the main band (at zero frequency). Thus the result of multiplication of the signals in digital mixers 32 and 33 are "removing" carrier-phase and quadrature components of the signal and the transfer signal spectrum at zero frequency.

The digital carrier generator 7 is controlled by the signal transmitter 4, in particular from the computer 4 receives the data code of the carrier frequency signal. On the basis of these data accumulating adder 12 (Fig. 2) create an output signal of the digital carrier generator 7 as the current values of the phases of the frequency of the reference signal. In addition, with the help of block 13 of formation samples in the carrier generator 7 to derive the reference phase of the carrier and the data counting the number of cycles (periods) of the carrier used by the transmitter 4 in the implementation process of tracking the frequency and phase of the carrier input is Accreditatie, the primary clock frequency Fň and the first clock frequency F1, and the formation of the samples in the block 13 forming timing - frequency measurement gates f and. Formed by the digital carrier generator 7 reference signals (current phase) are fed to the reference input of the digital mixers 32 and 33. Digital mixers 32 and 33 using converters codes that implement the "table of sine - cosine functions, the values of the phase reference signal is converted into the corresponding amplitude value used in digital mixers 32, 33 when the digital quadrature "multiplication" of the processed and reference signals.

After "removing" the carrier-phase and quadrature components of the processed signal and the transfer signal spectrum at zero frequency digital demodulators 34-37 perform correlation comparing the processed signal with the reference C/a codes generated by the programmable delay line 31 and the generator 30 of the reference C/a code.

Reference clock frequency for the generator 30 of the reference C/a code (1.023 MHz for GPS and 0,511 MHz for GLONASS) is determined by a reference signal generated by the digital code generator 8. The digital code generator 8, the formation of the output is carried out, for example, with the senior level of the output register phase 17. In addition, the digital code generator 8 connected with the adder 12 unit 13 forming samples generates data of the reference shares of the character code, which as a feedback signal received at the transmitter 4. The values generated in the generator 8 reference clock frequency C/a code received in the accumulating adder 12 with the transmitter 4. Work is accumulating adder 12 digital code generator 8 is carried out with the sampling frequency of the primary clock frequency Fň and the second clock frequency F2, and the formation times of the shares of the character in the block 13 forming timing - frequency measurement gates f and.

Based on the output signal of the digital code generator 8, which clock frequency C/a code generator 30 of the reference C/a code generates the reference C/a code for the signal processing corresponding to the respective satellite system. Generated by the generator 30 of the reference C/a code unique to each of the GPS satellites that use code division signals, and the same for all satellites GLONASS uses frequency division signals. The formation of certain kinds of code, i.e. a certain kind of pseudocore pseudo-random code, managed by the evaluator 4 (not shown). The feedback signals for the transmitter 4 (counts the number of code symbols and the number of millisecond epochs) are formed with the help included with the generator 30 count of the number of code symbols and register the number of code symbols, and count millisecond epochs and register the number of millisecond epochs (not shown). Reading of data from the registers to the number of code symbols and the number of millisecond epochs is carried out with a frequency measurement gates f and.

Generated by the generator 30 of the reference C/a code is supplied to the programmable delay line 31, which generates at its outputs accurate "R" (punctual) and differential "E-L" (early-minus-late) a copy of the reference C/a code. The exact "P" copy of the reference C/a code is fed to the second inputs of the digital demodulators 34 and 37, and the difference "E-L" - at the second input of the digital demodulator 35 and 36. The programmable delay line 31 is carried out under the action of control signals generated by the register 29 management of a managed computer 4. When this is carried out varying the spacing between the early and late copies of the C/a code from 0.1 to 1 duration symbol C/a code, thereby narrow discriminator" ("narrow to the CSOs in digital demodulators 34-37, accumulate in blocks 25-28 accumulation time interval equal to the duration of the epoch code (1 MS), and then read by the computer 4 and is used for loopback loops the tracking code and the carrier of the processed signal.

In the General operation of the proposed receiver signal SNS is similar to the operation of the receiver prototype. The difference lies in the peculiarities of formation of the reference signal digital generator bearing 7 and code 8. These features are as follows.

Unlike receiver-prototype accumulating adder 12 of each of the generators 7 and 8 contains high-frequency and low-frequency parts, respectively

high-frequency 14 and the low-frequency 15 cumulative modules, thus forming accumulating the adder 12, the current values of the phase of the output signal represents the sum of the phase values generated by the modules 14 and 15. High frequency cumulative units 14 both generators 7 and 8 operate with a sampling frequency of the primary clock frequency Fň, low frequency cumulative module 15 of the digital carrier generator 7 operates with a sampling rate defined by the first clock frequency F1, and nishchal the swarm additional clock frequency F2.

Work accumulative adders 12 digital carrier generators 7 and code 8 is carried out by the same algorithm, the difference is in razrednoj cumulative units 14 and 15, the sampling rates, which are low frequency cumulative module 15, and the frequencies of the generated output signals.

As an example, consider the accumulating adder 12 of the digital carrier generator 7.

At the first control input is accumulating adder 12 of the digital carrier generator 7, i.e., to the information input of the first register code frequency 18 cumulative frequency module 14 enters K1bit number N1proportional to a given incrementRFthe current phase formed in each step of signal sampling frequency Fň. The number of N1is set by the computer 4, for example, based on operating conditions of the scheme tracking the carrier". Number1recorded in the register 18 to the corresponding recording signal generated by the transmitter 4. From the output of the register 18, the number of N1arrives at the first input of the first combinational adder 19. To the second input of the combinational adder 19 with the frequency Fň comes K1RFthat geometrically interpreted (in the coordinate system of the phase-time) step function shown in Fig. 5 the curve "I". The slope of the curve "I" determines the rate of the increment of the phase and thus the frequency f, RF signal, the synthesized high frequency cumulative module 14. This slope, and hence the frequency f, RF synthesized signal, can quickly be changed by changing the number of N1. The phaseRFretiring frequency Fň output register phase 20 (Fig. 5, curve "I"), arrives at the first input of the output combinational adder 16.

At the second control input is accumulating adder 12 of the digital carrier generator 7, i.e., to the information input of the second register code frequency 21 low frequency cumulative module 15, is supplied K2bit number N2proportional to a given incrementLFthe current phase formed in each step of signal sampling frequency F1. The number of N2recorded in the register 21 to the corresponding recording signal generated by the transmitter 4. From the output of the register 21, the number of N2Postup is depends F1 comes K2-bit number that specifies the value of the current phase accumulated in the second register phase 23 to this measure. The result of the sum of these numbers is sent back to the register phase 23. Thus, at the output of low frequency cumulative module 15 with the frequency F1 generated current values of phaseLFthat geometrically interpreted (in the coordinate system of the phase-time) step function shown in Fig. 5 curve "II". The slope of the curve "II" defines the speed increment phase and, consequently, the frequency f, the LF signal, the synthesized low frequency cumulative module 15. This slope, and hence the frequency f, LF synthesized signal can be changed by changing the number of N2.

The phaseLF(up to K1senior level) removed from output K1high-order bits of the register phase 23 low frequency cumulative module 15 (Fig. 5, curve "II"), comes from the frequency F1 to the second input of the output combinational adder 16, which is formed with a value of phaseRFcoming with a frequency Fň output register phase 26 cumulative frequency module 14 (Fig. 5, a stepped curve "I").

The sum of the phasesRF+LFSINT.and, therefore, the frequency f output signal, storing synthesized by the adder 12. The slope of this curve, and thus the synthesized frequency f, in the General case can be established by any of its components - curves "I" and/or "II" (frequency f, HF and/or f. LF). Practically, the difference in the synthesized frequencies of the considered digital generators of different channels 3 digital correlator 2, due to the different letters of the signals of GLONASS and different clock frequency C/a code GLONASS and GPS, is provided by the difference in low-frequency components f, LF.

Since the formation of the output values of the phaseSYNTH,bassin nakaplivaya the adder 12 is carried out by summing the two components (high-frequencyRFand low-frequency LF) it is an objective limitation on the magnitude of each of these components. The essence of this limitation is that in order to ensure uniqueness within the phase cycles of the formed phase valuesSINT.increment the total phase are specific correlation between razryadnitsy 14 and the high-frequency low-frequency 15 cumulative modules and the values written to them numbers and also installed a certain periodicity (periods overflow) modules 14, 15.

Analyzing the characteristics of the accumulation phase in nakaplivaya the adder 12 (Fig. 5, a stepped curve III) and comparing it with a reference characteristic (Fig. 5, a direct IV) shows that the generated accumulating the adder 12 values of total phaseSINT.taken from the output register phase 17 coincide with the reference values at the moments corresponding to the cycles of the signal sampling frequency Fň. In other aspects the total phase different from the reference, and this difference is systematic and time is determined by the phase clock frequency F1 y digital carrier generator 7 and F2 digital code generator 8. This bias, if necessary, is calculated by the computer 4 and is recorded in the form of corrections when digital tracking systems correlation signal processing. In particular, the account of the systematic error for the digital carrier generator 7 is made in the exercise of absolute phase measurements, for example in times of measurement of pseudorange and Doppler frequency shift in the carrier phase. In cases where the absolute is imeyutsa without correction of systematic errors.

In the present receiver to enable accounting for this bias is used, the register 11 of the reference phase, which is part of the shaper 9 additional low-frequency clock signals (see Fig. 1). Register 11 captures the moments of the income measurement gates f and the counter values included in the frequency divider 10. These values determine the phase1and2generated by the divider 10 additional clock frequencies F1 and F2. These values are read by the computer 4 and are used to calculate corrections to the timing of the phases of low-frequency components of the signals synthesized by the digital generator bearing 7 or code 8, the shift of the measurement since the last correction according to the formula

< / BR>
where is the adjustment value (fractional phase of the cycle);

fc. LF frequency synthesized low frequency cumulative module 15 of the corresponding digital generator 7 (8) of the corresponding channel 3 digital correlator 2;

Fň - clock frequency (sampling frequency);

k1(2)- the ratio of the frequency Fň to the frequency F1(F2);

1(2)the phase of the reference frequency F1(F2) at the time of measurement (count value of the frequency divider 10, forming sootvetstvuyushchaya bias, associated with features of the dual-frequency accumulative adders 12 digital generators 7 and 8, gives the possibility to declare the receiver to perform the navigation measurements with the required accuracy. In contrast receiver prototype, reduces power consumption.

The reduction in power consumption achieved by the new (dual) digital generator bearing 7 and code 8, due to the fact that high frequency cumulative module 14 is accumulating adder 12 is low-rank and high RES cumulative module 15 - bass. This combination of high-frequency low-rank and low-frequency high RES accumulative modules provides a reduction in energy consumption compared to a traditional solution based on the use of digital generators carrier and code high-frequency and simultaneously high RES accumulative adders.

Evaluation of winning power clearly can be illustrated on the example of the digital code generator 8.

For evaluation purposes, we assume that the digital code generator 8 to generate a frequency five times greater than the frequency of the C/Z frequency setting - f = 1 Hz.

For these conditions, the bit depth of the digital code generator traditional patterns determined from the formula f = Fň/2tois the value of K= 25, and the digital code generator 8 of the proposed receiver has the following parameters: cumulative frequency module 14 is digit (K3= 2), operates with a sampling frequency F20 MHz and synthesizes the frequency f. RF= 5 MHz; low frequency cumulative module 15 is 23-bit (K4= 23), works with frequent sampling F2= Fň/201 MHz and synthesizes the frequency f. LF= 0,115 MHz.

An approximate estimation of the power consumption P of the digital generator with accumulating a full adder can be realized, for example, using the empirical formula

P= FPgKg,

where F is the sampling frequency, MHz;

Pg - the power of one element depends on the element base);

Kg - number of digits.

In terms of the same element base, for example when using the same D-triggers, power Pg on one element in a digital generator of traditional patterns and dual-frequency digital oscillator of the proposed receiver can be considered equal and will not be taken into account when conducted comparative evaluation.

Camping as

P0= FKg= Fň(Ks0+Kr0)

where Ks0- bit combinational adder (K= 25);

Kg0the bit width of the register phase (K= 25).

Consumption of P1dual-frequency code generator can be estimated as

p1= Fň(Ks1+Kr1)2+F2(Ks2+Kr2)

where Ks1- bit width high-frequency Raman adders 16, 19 (K3);

Kg1- bit width high-frequency phase registers 17, 20 (K3);

Ks2- width of the low-frequency Raman adder 22 (K4);

Kr2- width low register phase 23 (K4).

Given that consumption per discharge combinational adder and one digit of the register phase is approximately the same [12] , the consumption of P0the digital code generator traditional patterns and consumption of P1dual frequency digital code generator of the proposed receiver can be written as

P0= F2202521000;

P1= (F34) + (F242)(2024) + (1232)206.

Comparing the values of R0and P1shows that the gain in power only in relation to one of the digital code generator 8 in this example is tructure high-frequency high RES combinational adder must contain additional circuit transfers in parallel, not considered in the above example, which leads to an increase in the volume of this adder and, accordingly, its power several times. In combinational adders of the proposed receiver of such circuits not because combinational adders 19, 16 are low-rank, and combinational adder 22 operates at a sufficiently low frequency, which allows the use of adders with a serial transfer.

Win power in relation to the carrier generator 7, estimated by the above method, is not less than 2.4 times.

Given that digital generator carrier and code can be found in all channels of N-channel digital correlator 2, and the number of channels can reach 12 to 24, the total gain in energy consumption in the inventive receiver is essential.

Thus, of the above it is seen that the inventive receiver GPSr technically feasible, implement industrial and solves the technical problem of reducing energy consumption. When implemented positive features of the proposed receiver GPSr determine the prospects for its wide use, especially in the portable radiation Satellite System - GLONASS. The interface control document. KNITS videoconferencing Russia, 1995.

2. Global Position System. Standard Positioning Service. Signal Specification. " USA, 1993.

3. Network satellite navigation system / C. S. Shebshaevich, p.p. Dmitriev, N. Century Ivancevich etc. // M , Radio and communications, 1993.

4. Riley , S., Howard N. , Aardoom E. , Daly P. , P. Silvestrin "A Combined GPS/GLONASS High Precision Receiver for Spase Applications", Proc. jf ION GPS-95, Palm Springs, CA, US, Sept. 12-15, 1995, p. 835-844.

5. Digital radio receiving system: Reference / M And. Azishski, R. B. Mazepa, E. P. Ovsyannikov, and others / edited by M. I. of Adissage, M. , Radio and communications, 1990.

6. On-Board satellite navigation device / I. C. Kudryavtsev, I. N. Mishchenko, A. I. the air and others ; Ed. by B. C. Shebshaevich, M. , Transport, 1988.

7. RF patent 2146378 (C1), CL G 01 S 5/14, publ. 10.04.2000.

8. A. J. Van Dierendonck. , Pat. Fenton and Tom Ford. Theory and Performance of Narrow Correlator Spacing in a GPS Reciever. Navigation: Jornal of The Institute of Navigation, Vol. 39, N 3, 1982.

9. U.S. patent 5390207, CL G 01 S 5/02, H 04 7/185, publ. 14.02.95. (Fenton, A. J. Van Dierendonck, "Pseudorandom noise ranging receiver which compensates for multipath distortion by dynamically adjusting the time delay spacing between early and late correlators").

10. U.S. patent 5495499, CL H 04 L 9/00, publ. 27.02.96. (Fenton, A. J. Van Dierendonck, "Pseudorandom noise ranging receiver which compensates for multipath distortion by dynamically adjusting the time delay spacing between early and late correlatorLASS="ptx2">

12. Catalogue of the elements of the company "Samsung" - "STD 80/STDM80 0.5 m 5V/3/3V Standard Cell Library Data Book, 1996, Samsung Electronics Co. Co., Ltd. ".

The receiver of signals of satellite radio navigation systems containing radio frequency Converter, the input of which forms the signal input of the receiver, the N-channel digital correlator, the signal and clock inputs of each of the channels of which are connected with the corresponding outputs of the radio frequency Converter, calculator, and the driver signals a time stamp, the control input of which is connected by a bus interchange with the transmitter clock input to clock output of the radio frequency Converter, and the output of the measurement gates with inputs measurement gates each channel N-channel digital correlator, each channel N-channel digital correlator contains associated with computer bus communication module correlation processing, digital carrier generator and the digital code generator, and each of these digital generators contains associated with computer bus interchange accumulating adder and the forming unit counts, information whose input is connected to the output data accumulating adder, and the output is their adders, connected with the control inputs of the correlation processing module, the clock inputs of these digital generators, educated clock inputs of their accumulative adders, and the measuring inputs of the gates formed by the measuring inputs of the gates blocks the formation of counts, are connected, respectively, with a clock input and the input of the measuring gates correlation processing module, a clock input, measurement gates and signal inputs which form the corresponding inputs of the channel N-channel digital correlator, characterized in that the receiver entered shaper additional low-frequency clock signals for the digital carrier generator and the digital code generator, made in the form of the frequency divider and its associated register reference phase, and the clock input of the frequency divider is connected to a clock output of the radio frequency Converter, the input of the measuring gates register reference phase is connected to the output of the measuring gate driver signals timestamp output register reference phase is connected by bus to exchange data with the evaluator and the first and second outputs of the low-frequency clock signals of the frequency divider are connected respectively with more is arrestor, in each of these digital generators accumulating adder made in the form of high frequency and low frequency cumulative modules, and includes series-connected output combinational adder and the output register phase, and frequency cumulative module contains serially connected first register code frequency, the first combinational adder and the first register phase, the output of which is connected to the second input of the first combinational adder and to the first input of the output combinational adder, low frequency cumulative module contains serially connected second register code frequency, the second combinational adder and the second register phase, the output of which is connected to the second input of the second combinational adder, and the output of the corresponding high-order bits to the second input of the output combinational adder, a clock input of the output register phase and coupled with it the clock input of the first register phase high frequency cumulative module form a clock input is accumulating adder - clock input digital generator, the clock input of the second register phase low frequency cumulative module obrazovatelnogo and low frequency cumulative modules form respectively first and second control inputs accumulating adder, associated bus communication with the transmitter, the output bits of the output register phase and outputs the corresponding least significant bits of the second register phase low frequency cumulative module form the output data accumulating adder, which is connected through the forming unit counts with the evaluator, and the outputs of the respective bits of the output register phase form the output of the reference signal digital generator connected with the corresponding reference input of the correlation processing module channel N-channel digital correlator.

 

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EFFECT: improved safety of track maintenance and repair teams in wide zone of operation.

6 dwg

FIELD: the invention refers to navigational technique and may be used at designing complex navigational systems.

SUBSTANCE: an integrated satellite inertial-navigational system has a radioset connected through an amplifier with an antenna whose outputs are connected to a computer of the position of navigational satellites and whose inputs are connected with the block of initial installation of the almanac of data about satellites' orbits. The outputs of this computer are connected with the inputs of the block of separation of radio transmitting satellites. The outputs of this block are connected with the first group of inputs of the block of separation of a working constellation of satellites whose outputs are connected with inputs of the block of computation of a user's position. The system has also a meter of projections of absolute angle speed and a meter of projections of the vector of seeming acceleration which are correspondingly connected through a corrector of an angle speed and a corrector of seeming acceleration with the first group of inputs of the computer of navigational parameters whose outputs are connected with the first group of the outputs of the system. The system also includes a computer of initial data which is connected with three groups of inputs correspondingly to the outputs of the meter of projections of absolute angle speed and the meter of projections of a vector of seeming acceleration and to the outputs of a block of integration of information and also to the outputs of the block of computation of a user's position. At that part of the outputs of the computer of initial data are connected to the inputs of the computer of navigational parameters and all outputs are connected to the first group of the inputs of the block of integration of information whose second group of inputs is connected with the outputs of the corrector of an angle speed and the corrector of seeming acceleration, and the third group of inputs is connected to the outputs of the block of computation of a user's position. One group of the outputs of the block of integration of information is connected to the second group of the inputs of the block of selection of a working constellation of satellites, the other group of the outputs are directly connected to the second group of the outputs of the system, the third group of the outputs are connected to the inputs of the corrector of seeming acceleration and the fourth group of the outputs are connected with the inputs of the corrector of an angle speed and the second group of the inputs of the computer of initial data.

EFFECT: increases autonomous of the system, expands composition of forming signals, increases accuracy.

4 dwg

FIELD: satellite radio navigation, geodesy, communication, applicable for independent instantaneous determination by users of the values of location co-ordinates, velocity vector components of the antenna phase centers of the user equipment, angular orientation in space and bearing.

SUBSTANCE: the method differs from the known one by the fact that the navigational information on the position of the antenna phase centers of ground radio beacons, information for introduction of frequency and time corrections are recorded in storages of the user navigational equipment at its manufacture, that the navigational equipment installed on satellites receives navigational radio signals from two and more ground radio beacons, and the user navigational equipment receives retransmitted signals from two satellites.

EFFECT: high precision of navigational determinations is determined by the use of phase measurements of the range increments according to the carrier frequencies of radio signals retransmitted by satellites.

3 dwg, 1 tbl

FIELD: radio communication.

SUBSTANCE: in accordance with the invention, the device for radio communication provides for getting of first time base (for example, getting of the code time shift) from the signal received from the transmitter on the ground. The predetermined shift based at least on the delay of propagation of received signal is applied to the first time base for obtaining of the second time base. For example, the second time base may be equalized with the time base of the satellite system of position finding (for example, GPS NAVSTAR).

EFFECT: synchronizing signal is generated, with has a time code shift based on the second time base.

6 cl, 12 dwg

FIELD: aviation engineering.

SUBSTANCE: device has on-ground automated system for controlling air traffic made in a special way, interrogation unit and re-translator mounted on air vehicles and made in a special manner as well. Autonomous duplication is used for measuring distance between flying vehicles.

EFFECT: widened functional abilities.

6 dwg

FIELD: radio navigation aids, applicable in digital correlators of receivers of satellite radio navigation system (SPNS) signals, in particular, in digital correlators of receivers of the SPNS GLONASS (Russia) and GPS (USA) signals.

SUBSTANCE: the legitimate signal in the digital correlator is detected by the hardware, which makes it possible to relieve the load of the processor and use its released resources for solution of additional problems. The digital correlator has a commutator of the SPNS signals, processor, digital mixers, digital controllable carrier-frequency oscillator, units of digital demodulators, accumulating units, programmed delay line, control register, digital controllable code generator, reference code generator and a signal detector. The signal detector is made in the form of a square-law detector realizing the algorithm of computation of five points of the Fourier sixteen point discrete transformation with additional zeroes in the interval of one period of the, c/a code with a subsequent computation of the modules of the transformation results and their incoherent summation and comparison with a variable threshold, whose value is set up depending on the noise power and the number of the incoherent readout. The signal detector has a controller, multiplexer, complex mixer, coherent summation unit, module computation unit, incoherent summation unit, noise power estimation unit, signal presence estimation unit and a unit for determination of the frequency-time coordinates of the global maximum.

EFFECT: provided acceleration of the search and detection of signals.

2 cl, 6 dwg

FIELD: submarine, marine terrestrial and close-to-ground navigation, in particular type GPS and GLONASS systems.

SUBSTANCE: at a time instant, that is unknown for the receiver, a signal is synchronously radiated by several radiators with known co-ordinates. The radiated signals are received by the receiver, the signal speed square is measured in the current navigation session, the Cartesian co-ordinates of the receiver are computed according to the moments of reception of the radiated signal and the measured signal speed square.

EFFECT: enhanced precision of location of the signal receiver.

2 dwg

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