Universal digital driver signals with continuous phase modulation

 

(57) Abstract:

Usage: in electronics in transmission systems discrete data to form a signal with continuous phase modulation. The device includes a shift register (1), the decoder (2) the current phase, performed on the ROM (9) the current phase and the adder (C) (10), RAM (3) the current phase, with the generator (4), the decoder (5) the initial phase, performed on a read-only memory (11) the initial phase and (12), RAM (6) the initial phase, the counter (7) clock intervals and synthesizer (8) frequencies. Technical result: improving the accuracy of the generated signal with continuous phase modulation due to synchronization in time of the successive transformations of samples generated signal with boundary clock and symbol intervals. 2 C.p. f-crystals, 4 Il.

The invention relates to electrical engineering and can be advantageously used to generate a signal with continuous phase modulation in communication systems discrete information.

Known shapers signal with continuous phase modulation (CPM [1 - 5], which allows to receive radio signals with different types of continuous phase modulation CPFCK, MSK, GMSK, TFM, GTFM.

In these ustroystv, the next i-th order of the symbol which

< / BR>
< / BR>
iTct(i+1)Tc; 0t*Tc;

wherei= 1; 3; ...(M-1)- values that can be used with the i-th information symboli;

g(t) is the symbol of the modulating signal (frequency pulse) duration LTcL is an integer;

Tc- the length of the information symboli;

fnthe carrier frequency;

h=p/q is the modulation index (p and q integers);

O- the initial phase of the signal (the first character signal);

q(t) - law-of-phase (phase pulse) generated signal.

Duration LTcsymbol g(t) of the modulating signal and the corresponding phase response q(t) is called the length of the partial response.

In practice, the most often chosen modulation index h = 1/2, in which conditions are

q(t) = 0; q(LTc)=1/2 (2)

These conditions satisfy all of the above signals with continuous phase modulation.

When the digital formation of character (1) signal with continuous phase modulation in known devices initially form a set of N samples of the phase of the symbol. Any n-th sample (n = 0,1,...N -1) phase formed of the i-th symbol (1), with an account of the tion.

The sampling phase is then converted into sample values generated symbol, and then use the d / a conversion in continuous time signal.

As a result of multiple sequential transformations of samples of signals in known devices on the borders of clock intervals occur transients, which reduces the accuracy of the generated signal.

Closest to the proposed set of features is a universal digital driver signals with continuous phase modulation [1], containing the shift register, the information input by the information input device and the output is connected to the information input of the decoder for the current phase, the clock input connected to the output of the counter clock intervals, and the output with the input of the analog generator whose output is the output device.

A disadvantage of the known device is the presence of transient processes on the borders of clock intervals defined by the clock pulses fed to the counter input clock intervals.

To eliminate this drawback must be strictly SS="ptx2">

Achieved the solution of the problem the fact that universal digital driver signals with continuous phase modulation, containing the shift register, the information input by the information input device and the output is connected to the information input of the decoder for the current phase, the clock input connected to the output of the counter clock intervals, as well as analog generator whose output is the output of the device, put the RAM at the current phase, RAM initial phase, the decoder initial phase and the frequency synthesizer, the first character of the output of which is connected to the clock input of the shift register, the second character output to the input of the control RAM write initial phase and the installation of the counter input clock intervals, the clock input of which is connected to the first clock output of the frequency synthesizer, the second clock output of which is connected to the control input of the entry RAM of the current phase, the output of which is connected to the analog input of the generator, and the input - output of the decoder, the current phase, the character input connected directly to the character input decoder initial phase and RAM through the initial phase with the output of the decoder, the initial phase, estructura scheme proposed universal digital driver signals with continuous phase modulation, a in Fig. 2 is a timing diagram explaining his work. In Fig. 3 shows the electrical structural diagram of the proposed universal digital driver signals with continuous phase modulation in the particular case of the device run on the discrete elements of technique. In Fig. 4 shows an electrical block diagram prototype [1].

Universal digital driver signals with continuous phase modulation (see Fig. 1) contains a register 1 shift decoder 2 current phase, RAM 3 of the current phase with the generator 4, the decoder 5 initial phase, RAM 6 initial phase, the counter 7 clock intervals and synthesizer 8 frequencies. The output of register 1 shift through the decoder 2 current phase and RAM 3 current phase is connected to the input analog generator 4. The output of the RAM 6 initial phase connected to the character inputs of the decoder 2 current phase and decoder 5 initial phase. The output of the counter 7 clock intervals connected with a clock input of the decoder 2 current phase. The output of register 1 shift also connected to the information input and decoder 5 initial phase, the output of which is connected to the input of the RAM 6 initial phase. The first character of the output of the synthesizer 8 frequency connected to clock input is the input of the counter 7 clock intervals, the clock input of which is connected to the first clock output of the synthesizer 8 frequency, the second clock output of which is connected to the control input of the write RAM 3 current phase.

Works universal digital driver signals with continuous phase modulation as follows.

In the proposed device is (3) the n-th sample (n=0,1,...N-1) phase i-th character (1) form using decoder 2 current phase based on its view of the initial phase and Delta phase:

< / BR>
where(i)o(o, ...i-1- the initial phase of the i-th symbol;

(i)(nTin,i-L+1, ...i- the current increment the phase of the i-th symbol for the n-th sample.

The initial phase of the current i-th symbol is given (2) and (3)

< / BR>
in the proposed device is defined recurrently by using the RAM 6 initial phase and decoder 5 initial phase in the initial phase of the previous (i-1)-th symbol

< / BR>
and increment phase for the duration of the previous (i-1)-th symbol

< / BR>
< / BR>
according to the rule

< / BR>
Therefore, to determine the initial phase of the current i-th symbol at a known initial phase of the previous (i-1)-th symbol is sufficient to know only L penultimate

is uniquely determined in the decoder 2 current phase generated by the counter 7 clock intervals, the number n of the current sample and the values of L the latest information symbolsi-L+1, ...i.

The operation of the proposed device provides the synthesizer 8 frequencies, generating the following sequence of pulses, the relative positions of which in time are shown in Fig. 2:

sequence of clock pulses with a repetition frequency fTon the first clock output (Fig. 2,a);

sequence detainees clock pulses in the second clock output (Fig. 2,b);

- character sequence of pulses with a repetition frequency fc= ft/N(N is integer), the first character of the output (Fig. 2,in);

sequence detainees character of the pulses at the second character output (Fig. 2,g).

Character pulses (see Fig. 2) with the first character of the output of the synthesizer 8 frequencies arrive at the clock input of the register 1 shift and ensure the consistent input into it information symbolsifrom the information input device.

Register 1 shift has (L+1) bits. Recorded in the register 1 shift penultimate (otuput information on the input of the decoder 5 initial phase, and the last (in the order of receipt) L information symbols i-L+1, ...i) corresponding to its (L, ...1) discharge, proceed to the information input of the decoder 2 current phase.

In the decoder 5 initial phase recorded all possible values increment phase f(i-1)(i-L, ...i-1) during the previous character generated signal, which are determined by the aggregate of previous values of L information symbols (i-L, ...i-1). Depending on the combination of values of these characters coming from the output of the register 1 shift to the information input of the decoder 5 initial phase, the corresponding value of the phase increment f(i-1)(i-L, ...i-1with the release of the latest fed to the input of the RAM 6 initial phase.

At the beginning of the work RAM 6 initial phase enter the value ofo0the initial phase of the generated signal. For this RAM 6 initial phase may have the appropriate information and control inputs.

During operation after recording in the register 1 shift valuesithe next information symbol in the RAM 6, the initial phase is to update the value of the initial phase(i)o(o, ...i-1the current i-th symbol of the grouped pulses, input control entry RAM 6 initial phase from the second character of the output of the synthesizer 8 frequencies.

Then for any symbol interval of duration TC= 1/fCon the character input decoder 2 current phase output RAM 6 initial phase enters the value of f(i)o(o, ...i-1) the initial phase of the current i-th symbol of the generated signal.

At the clock input of the decoder 2 current phase from the output of the counter 7 clock intervals receives a binary signal, which determines the number n of the current selection within the duration of TCcharacter. The number n can take values from 0 to N-1 and changes when it arrives at the clock input of the counter 7 a clock interval of the clock pulses from the first clock output of the synthesizer 8 frequencies. While detained character pulses from the second character of the output of the synthesizer 8 frequency supplied on the installation meter inlet 7 of the clock intervals, confirm its zero state at the boundaries of the symbols generated signal.

Using decoder 2 current phase determines the phase values of f(i)(nTin,o, ...i) generated signal for N times, conformational character. The value of (3) every n-th sample (n= 0,1, . ..N-1) phase i-th symbol (1) is uniquely determined by the set of values of L the latest information symbols (i-L+1, ...i), the value of f(i)o(o, ...i-1) the initial phase and the number n of the given reference.

Record the values of f(i)(nTin,o, ...ithe current phase in the RAM 3 current phase is carried out using detainees clock pulses received at its control input record from the second clock output of the synthesizer 8 frequencies.

Then the set of N samples (n = 0,1,...N-1) phase f(i)(nTin,o, ...i) the i-th symbol using the analog generator 4 is converted into a continuous time symbol S(i)(to, ...i) generated signal (1) with continuous phase modulation.

Universal digital driver signals with continuous phase modulation can be implemented on known functional elements.

Decoder 2 current phase and the decoder 5, the initial phase can be in the form of a ROM, a set of values of all input signals which is the address of the corresponding cell, from which the value of the current or initial phase enters the e the electrical structural diagram of the prototype [1]. Analog generator 4 includes (see Fig. 4) drive 6, the ROM 7 samples (samples) of the harmonic signal, d / a Converter 8 and the filter 9 of the lower frequencies. Recommendations on the choice of parameters and operation modes of the analog generator 4 is given in [6].

In the particular case of implementing the universal digital driver signals with continuous phase modulation on the discrete elements of technique, as shown in Fig. 3, the decoder 2 current phase contains consistently enabled ROM 9 current phase and the adder 10, additional input and output which are, respectively, the character input and output of the decoder, the initial phase information and the clock inputs of which are respectively the first and second inputs of the ROM of the current phase.

The decoder 5 initial phase contains consistently enabled ROM 11 initial phase and the adder 12, additional input and output which are, respectively, the character input and output of the decoder, the initial phase, the information input of which is the entrance ROM initial phase.

The device allows you to generate a signal with continuous phase modulation with tight synchronization in time after the with boundary clock and symbol intervals, that allows to improve the accuracy of the generated signal and to prevent the loss of information during data transfer.

Sources of information:

1. A. Kopta, S. Budisin, V. Jovanovic. New Universal All-Digital CPM Modulator. IEEE Trans. on comm., vol. com-35, N 4, April 1987, pp. 458 -462.

2. T. Aulin, N. Rydbech, C. E. Sundberg. Transmitter and receiver structures for M-ary partial response FM. IEEE Trans. on comm., vol. com-26, No. 5, May 1978, pp. 534-538.

3. S. Ray. Generation of serial CPMFSK signal. Proc. IEEE, vol. 72, No. 1, Jan. 1984, pp. 128-129.

4. C. B. Decker. On the application of tamed frequency modulation to various field of digital transmission. Proc. 1980 Int. Zurich Seminar on Digital Commun., Zurich, Mar. 1980, pp. A1.1-A1.10.

5. H. Suzuki, Y. Yamas, K. Momma. Single chip baseband waveform generation CMOS LSI for a quadrature-type CPM modulator. Electron. Lett., vol. 20, No. 21, Oct. 1984, pp. 875 - 876.

6. J. Tierney, C. Rader, B. Gold. A digital frequency synthesizer, IEEE Trans. on Audio Electroaconst., vol. AU-19, N 3, Mar. 1971, pp. 48-56.

1. Universal digital driver signals with continuous phase modulation, containing the shift register, the information input by the information input device and the output is connected to the information input of the decoder for the current phase, the clock input connected to the output of the counter clock intervals, as well as analog generator whose output is the output of the device, characterized in that the input RAM of the current phase, initial RAM faadu of the shift register, the second character output to the input of the control RAM write initial phase and the installation of the counter input clock intervals, the clock input of which is connected to the first clock output of the frequency synthesizer, the second clock output of which is connected to the control input of the entry RAM of the current phase, the output of which is connected to the analog input of the generator, and the input - output of the decoder, the current phase, the character input connected directly to the character input decoder initial phase and RAM through the initial phase with the output of the decoder, the initial phase, information whose input is connected to the output of the shift register.

2. Universal digital shaper under item 1, characterized in that the decoder current phase contains consistently enabled ROM the current phase and the adder, additional input and output which are, respectively, the character input and output of the decoder, the initial phase information and the clock inputs of which are respectively the first and second inputs of the ROM of the current phase.

3. Universal digital shaper under item 1, characterized in that the decoder initial phase contains consistently enabled ROM initial phase and somnitelnoi phase, information input which is the input of the ROM initial phase.

 

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