Apparatus for forming an interval of time

 

(57) Abstract:

Apparatus for forming controlled by the digital code of the time interval used to generate pulses and delays. The principle of the device is based on the conversion of pulses of the reference oscillator counter (7) pulses, which is loaded on the output trigger. The period of the reference pulses is additionally broken into multiple parts - quanta of time due to the implementation of the reference oscillator in the form of a multiphase pulse generator (IGI) (1). Many of the outputs of MHI (1) form the subscale countdown at the beginning and end of the generated frame. The process of counting time interval and digital control its duration exercise added blocks: case (2), the encoder (4), the adder (3), the multiplexer (3), the EXCLUSIVE OR element (10) and node comparison (11). Technical result: improving the accuracy of the generated time interval. 1 C.p. f-crystals, 1 Il.

The present invention relates to techniques for forming pulses of variable duration.

Art

To generate time intervals with adjustable duration, for example, when the delay pulse signals, the widely opastnosti, in the well-known time relay, consisting of a trigger, covered by the feedback through bit key, gronroos RC-circuit and comparator [1, 2] . These devices are easy to implement, but do not provide a stable duration of the time interval due to the analog principle of its formation, are sensitive to changes in temperature and supply voltage.

There is also known a method of forming a pulse of a given duration [3], based on the development of stable periodic sawtooth signal, whereby upon receipt of a triggering signal stores instantaneous value of the sawtooth signal as a threshold voltage, and completed the formation of the interval at the time of reaching the threshold voltage of the sawtooth signal in the next period. Implementing this method, the device includes a trigger feedback through gronroos circuit in the form of a reference oscillator, which is loaded on dual shaper sawtooth voltage, each channel is equipped with an analog storage device and the comparator. However, this analogue does not provide the ability to electronically adjust the duration of the generated pulse is allow device, based on the calculation of the specified number of pulses of stable frequency. Such devices include, in particular, the processing unit interval delay (4], including principal and managing counters pulse outputs connected to the unit equivalence, as well as the element And connected the inputs to the Opera generator and the input terminal of the triggering signal, and output to the input of the main counter pulses. Digital regulation of the duration of the generated interval is managing pulse counter whose contents can be changed. However, the accuracy of the analog low, since the quantization step time is limited to the period of the reference oscillator.

Among the known analogues of the closest in technical essence to the present invention is a pulse shaper [5], which contains reference generator and a pulse counter, and the output trigger, one input connected to the inlet clamp trigger signal, and the other with the output of the pulse counter. Digital modulation pulse duration in this device you can make an obvious way, providing the pulse counter inputs parallel downloads original saastliku quantization interval of time in the process of formation equal to the period of pulses of the reference oscillator and cannot be arbitrarily reduced.

The invention

The aim of the present invention is to improve the accuracy of the generated time interval by reducing the quantum of time.

To achieve this goal period of the reference pulses are additionally broken down into many parts, equal quantization step time, due to the implementation of the reference oscillator in the form of a multiphase pulse generator. Multiple outputs multiphase pulse generator form the subscale countdown at the beginning and end of the generated frame. The process of counting time interval and digital control its duration exercise added blocks: register encoder, adder, multiplexer, the EXCLUSIVE OR element and node comparison.

In accordance with the invention, the pulse counter that can operate in parallel mode load original number, is connected to the information input to the input terminals of the digital code time interval, and the entrance boot - with input clamp trigger signal and the reset input of trigger, the output of which serves as an output device and an information input connected to the output node of the comparison. The outputs of the multiphase generator EMI input is connected to the input terminal of the triggering signal, all outputs attached to the group of least significant bits of the first addend adder through the encoder, and the first output register, in addition, is connected to the input of the high-order bit of the first addend adder. The inputs of the second addend adder connected to additional input terminals of the digital code time interval, the group of outputs of all least significant bits of the sum are connected to corresponding address inputs of the multiplexer, the output of the high-order bit of the sum to one input of the EXCLUSIVE OR element, and the output of the transfer from the first input node of the comparison. The other input node of the comparison device is connected to the respective outputs of the pulse counter. The EXCLUSIVE OR element to its other input connected to the output of the multiplexer, and output to the clock inputs of the pulse counter and the trigger.

In a preferred embodiment, the node is from the output element OR connected with its inputs to the outputs, respectively, of the elements of And and OR NOT. United first input element And the element OR NOT serve as the first input node of the comparison, and the remaining United inputs and the other input node of the comparison.

The drawing shows electr.

Information confirming the possibility of carrying out the invention

Shown on the drawing a diagram of the device for forming the interval of time includes a multi-phase generator 1 pulse, the outputs of which are connected simultaneously to the corresponding inputs of the register 2 and the multiplexer 3. The outputs of the register 2 via the encoder 4 is connected with the younger group of inputs of the first addend adder 5, his first appearance, in addition, is connected to the input of the high-order bit of the first addend adder 5, and the clock input from the input clip 6 trigger signal.

Included in the counter circuit 7 pulses connected input load to the input terminal 6 of the triggering signal, the information input to the input terminals 8 high-order bits of the digital code time interval and a clock input simultaneously with a clock input of the trigger 9 to the output of the EXCLUSIVE OR element 10. Node 11 comparison first input connected to the output of the transfer of the adder 5, the other inputs to the corresponding outputs of the counter 7 pulses, and output to the information input of the trigger 9. The inputs of the second term of the adder 5 is connected to the additional input terminals 12 least significant bits of the digital code time interval, the output e of the multiplexer 3. The output of the multiplexer 3 is connected to the remaining input of EXCLUSIVE OR element 10, and the output of the trigger 9 to the output terminal 13 of the synthesizer time intervals.

Node 11 comparison can be made in the form of the output element 14 OR the inputs of which are connected to the outputs of item 15 And item 16 OR NOT. United first inputs of item 15 And item 16 OR does NOT serve the first input node 11 comparison, the other inputs of which are respectively combined inputs of both elements 15 And 16 OR NOT.

If multiphase generator 1 pulse is 2noutput, the same number of digits must contain the parallel register 2, the same number of information inputs must have the multiplexer 3. The number n is the number of outputs of the encoder 4 and the number of address inputs of the multiplexer 3. Parallel adder 5 is (n+1)-bit, and the pulse counter is an m-bit. The value of the time slice at synthesis time interval is Tabout/2n+1where Tabout- the period of the pulses on each output of the multi-phase generator 1 pulse.

In a preferred embodiment, the multi-phase generator 1 pulse occurs in the inverter, ogolna circuit of the 2nelectronic delay elements. The outputs of these delay elements form a set of 2noutputs multiphase generator 1 pulse with a phase shift from 0 to . In the process of generating pulses in sections such delay lines extends first "wave zeros", and then "wave units." The output pulses have the shape of a "meander", which allows the outputs of the multi-phase generator 1 pulse in the range 2 ...to use the inversion of the main outputs from the range 0... . Inversion is selected by the multiplexer 3 main output of the multi-phase generator 1 pulse performs the EXCLUSIVE OR element 10. The use of a controlled inverter in the form of element 10 ELIMINATES OR reduces to two times the required number of working phases of the multiphase generator 1 pulse, and also to reduce twice the bit width of the register 2, the multiplexer 3 and the encoder 4.

The encoder 4 converts the outputs of register 2 digital combination of the form where aiis either 0 or 1 in a binary number indicating the number of the combination, where there is a change in the value of the bit from 0 to 1 or Vice versa.

The duration of the synthesized time interval is set to binary (m+n+1)interval is the quanta of time Tabout/2n+1.

Apparatus for forming an interval of time working in the following order.

Multiphase generator 1 generates pulses continuously, periodically recurring pulses at their 2nthe outputs. The pulse at each of the next output delayed relative to the pulse at the previous output value of the time slot Tabout/2n+1. The input terminals 8 and 12 receives a digital code time interval. The trigger 9 in the initial state cocked, and the output terminal 13 is held to the voltage level of logic "1".

Upon receipt of a triggering signal on input clamp 6 case 2 captures the current state of the multiphase outputs of the generator 1 pulse, the pulse counter 7 is written to its original state, is equal to the binary number present at the input terminals 8 senior m bits of the digital code of the time interval and the trigger 9 is reset. On the output terminal 13 begins the formation time interval in the form of a pulse with zero working level.

The formation time interval is carried out by successive subtraction of the pulses of the pulse counter 7 from the original recorded when Zap is a sequence number which is determined by the adder 5 via the multiplexer 3 and the EXCLUSIVE OR element 10. The duration of the generated time interval is the sum of the total number of periods Taboutmultiphase generator 1 pulse set by the code at the input terminals 8, and the number of quanta of time Tabout/2n+1specified source at the input terminals 12 and determining the phase of the subtrahend counter 7 pulses.

Fixing the date of receipt of the triggering signal is produced by the register 2 by a subscale of the multi-phase generator 1 pulse by determining the sequence number of the output multiphase generator 1 pulse, pulse which coincides in time with the launch. The output code register is a likeness of thermometric code in two parts, one of which consists of one "zeros", and the second one "units". The length of one side is k bits, and the length of another side is equal to (2n-k) bits, and k can take values from 0 to 2n.

If the low order digit of the register 2 is fixed to "0", the code register looks like 0...01...1, and therefore, the trigger signal coincides in time with the time of occurrence of the pulse at the output of the multi-phase generator 1 pulse, where case 2 is fixed to the first "1". Shirato what this number is transmitted simultaneously with the zero LSB register 2, which is interpreted as big-endian fixed numbers of the output multiphase generator 1 pulse. Fixed (n+1)-bit number is in the range 0...(2n1) and corresponds to the range 0... phase shift on the subscale of multiphase generator 1 pulse.

If the low order digit of the register 2 is fixed to "1", the code register is 1...10...0, and, consequently, the trigger signal coincided in time with the advent of recession pulse at the output of the multi-phase generator 1 pulse, where case 2 is fixed to the first "0". The encoder 4 produces the output in the form of binary numbers on their outputs. To input the first addend adder 5 is the number of transmitted simultaneously with the unit at the LSB of the register 2, which is interpreted as big-endian fixed numbers of the output multiphase generator 1 pulse. In this case, fixed (n+1)-bit number is in the range 2n... (2n+11) and corresponds to the range ...2 phase shift on the subscale of multiphase generator 1 pulse.

Younger (n+1) bits of the digital code time interval received at input terminals 12, formed in amatoriale ordinal phase multiphase generator 1 pulse, which will match the end of the generated time interval. The sum of the numbers in the adder 5 is either not formed, or formed signal transfer. In the first case, the node 11 is configured to compare the state of 00... 00 counter 7 pulses, as it is with this combination, you receive a "1" at the output of the element 16 OR NOT. In the second case, the node 11 comparison configured to condition 11...11, as this combination will work element 15 I. Thus, in the second case, the node 11 comparison adjusts the number counted by the pulse counter 7 full periods Toby adding one period To.

When in the process of subtracting the pulse count 7 pulse reaches the end state 00 00...in the absence of the signal transfer adder 5 or 11.. . 11 during the formation of the adder 5 of the signal transfer node 11 comparison produces at its output a logic level "1" so that when the front of the next pulse at the output of the EXCLUSIVE OR element 10, the trigger 9 is cocked, thus completing the formation of a time interval on the output terminal 13.

In that case, if the total propagation delay of the pulse through the multiplexer 3 and the element 10 EXCLUSIVE OR more floor the IAOD downward corresponding to the number of time quanta by known means, for example, during automatic alignment device running microprocesser.

Literature

1. The one-shot. - Ed. mon. USSR N 1221712, CL H 03 To 3/033.

2. Titze U. , Schenk, K. Semiconductor circuitry: a reference guide. - M.: Mir, 1982, page 313, Fig. 18.36.

3. Method of forming a pulse of a given duration. - Ed. mon. USSR N 1287274, CL H 03 To 5/135.

4. Goldenberg L. M. Pulse and digital devices. - M.: Communication, 1973, S. 479, Fig. 10.29.

5. Horowitz P., hill U. Art circuitry: 2 I. I. I. - M.: Mir, 1986, page 563, Fig. 8.61.

1. Apparatus for forming pulses of variable duration, contains a reference generator, a pulse counter, information inputs are connected to input terminals of the digital code time interval, and the entrance boot - with input clamp trigger signal and the reset input of trigger, the output of which is connected to the output terminal of the device, characterized in that the input register, the encoder, adder, multiplexer, the EXCLUSIVE OR element and node comparison and the reference generator is designed as multi-phase pulse generator, the outputs of which are connected to the appropriate information inputs multy output register connected to the input of the high-order bit of the first addend adder, and the rest of the output register via the encoder connected to respective bits of the first addend adder, the inputs of the second term of the adder is connected to the additional input terminals of the digital code time interval, the group of outputs of the least significant bits of the adder are connected to corresponding address inputs of the multiplexer, the output of the high-order bit of the adder is connected to one input of the EXCLUSIVE OR element, and the output of the transfer of the adder with a first input node of the comparison, the other input of which is connected to the respective outputs of the pulse counter, the other input of the EXCLUSIVE OR element is connected to the output of the multiplexer, and the output from a clock input of the pulse counter and the trigger the output node of the comparison is connected to the information input of the trigger.

2. Apparatus for forming pulses of variable duration under item 1, characterized in that the node is from the output element OR the inputs of which are connected to the outputs respectively of elements And OR NOT combined first inputs of which are the first input node of the comparison, and thus United the remaining inputs and the other input node of the comparison.

 

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