The frame synchronization device

 

(57) Abstract:

The invention relates to techniques for digital communication, namely, devices frame synchronization in digital transmission systems with a temporary seal. The technical result - increased robustness of synchronization. The device frame synchronization includes the shift register 1, a decoder 2, the divider 5, the first analyzer 3, the first deciding unit 4, the dispenser gate stands 6, second and third analyzers 7 and 8, the second and third computing nodes 9 and 10, the divider by two 1, first and second, third and fourth memory blocks 12, 13, 14, and 15, the multiplexer 16, the correction device 17. The device frame synchronization can improve the noise immunity of digital transmission systems with a temporary seal, since the distortion control commands to be cleared is not the loss of a cyclical synchronism in the instrument receiving component group of signals. 1 Il.

The invention relates to techniques for digital communication, namely, devices frame synchronization in digital transmission systems with a temporary seal.

A device frame synchronization [1], containing the detector clock cycle, the input device, the elements, And, element OR register.

This device reduces the time of occurrence in cyclic synchronism due to the additional register. But the reduction of the time of occurrence in cyclic synchronism is not enough when the cycle length is several times greater than the length of the register and at high noise levels.

The closest to the technical nature of the claimed invention is selected as a prototype device frame synchronization [2] , containing the Recognizer singlegroup consisting of a shift register and decoder analyzer, a crucial node, a frequency divider connected in a certain way.

The disadvantage of this device is low immunity.

An object of the invention is to increase the noise immunity synchronization.

This task is solved in that in the device frame synchronization, containing the shift register, a decoder, the first analyzer, the first critical node, the frequency divider and clock TI and information HS inputs of the device frame synchronization is connected to the corresponding inputs of the shift register, the information outputs m0 - mn which are connected with inputs of the decoder, the output of which is dtweedie inputs of the first critical node, the output of the search SP which is connected with the corresponding input of the frequency divider, the other clock th input connected to the respective input device frame synchronization entered the dispenser gate stands, second and third analyzers, second and third computing node, a divide-by-two, the first, second, third and fourth memory blocks, the multiplexer, the correction device, and the address outputs A0 - An of the frequency divider is connected to the corresponding inputs of the first, second, third and fourth memory blocks and the inputs of the distributor gate stands the output of the gate stands the UCS position under synchronously D2 which is connected to another input of the first analyzer and the input of the correction, the output of the gate stand UCS(-1) under position prior synchronously one clock interval D1 is connected to the input of the second analyzer and the other input of the correction, the output of the gate stand PSK(+1) position following synchronously one clock interval D3 is connected to the third input of the analyzer and the other input of the correction, the output of the gate stand TFP under item staffing D4 is connected with the corresponding whodo and inputs the correction device and the divider by two, the output of which is connected to the inputs of the write-read C/S first, second, third and fourth memory blocks, other inputs data I of the first and second memory blocks are connected with information HS input device frame synchronization, outputs data D which are connected respectively to the inputs of data I of the third and fourth memory blocks, outputs data D which are connected respectively with the information inputs D1 and D2 of the multiplexer, the other address input a which is connected to the output of the divider by two.

Information output Y of the multiplexer is connected to the information input of the HS device correction, clock th input connected to a corresponding input of the frame synchronization, the output of the RESET which is connected with the corresponding input of the frequency divider, the input to the existence of a synchronization PHASE is connected with the corresponding output of the first critical node, the input correction GFR(-1) and GFR(+1) connected to respective outputs of the second and third computing node, the inputs to the availability of the synchronization PHASE, which are connected with the corresponding output of the first critical node, the other inputs of the response Ufromand errors UOshconnected respectively to the outputs of the second and third anad pulse frame synchronization AIC device correction are the outputs of the device frame synchronization.

When considering procedures grupoaranea.net higher orders, we can conclude that the duration of the cycle is a certain number of clock intervals. Some of them are intended for information on each component signal, for transmission of a cyclical (multiframe) clock, to transmit control commands speed agree and for the organization of clock intervals of X. Since X can be either an insertion or information, each component signal corresponds to N or N - 1 bits. When a similar procedure grupoaranea.net shows that if the distortion can cause the perception of inserting information bits (or Vice versa), the purpose of the operation of the leveling speed is not achieved, in addition, an erroneous interpretation of the management team alignment leads to loss of reception component group signals, which in turn leads to the deterioration of the noise immunity of the device frame synchronization.

In connection with the foregoing, the actual problem is the creation of a device frame synchronization with increased immunity, when the distortion control commands alignment. The known device [2] in this situation will go from a state of sin is the s phase and clock interval, designed in a loop under insert bits, the result will not be a loss of reception of the component group of signals downstream digital hierarchy levels.

The novelty of technical solutions is available in the claimed device new circuit elements: allocator gate stands, second and third analyzers, second and third computing node, the divide-by-two blocks of memory, multiplexer, device correction.

Thus, the invention meets the criterion of "Novelty."

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional units known. However, their introduction into the device frame synchronization with the above links gives it new properties. Introduced functional units interact in such a way that allow for the retention of synchronism of the component group of signals with distortion-control commands alignment.

Thus, the invention meets the criterion of "Inventive step", as it is for the expert is not obvious from the prior art.

The invention can be used in ciprofibrate, the invention meets the criterion of "Industrial applicability".

The drawing shows a structural electrical diagram of the device.

The device frame synchronization includes the shift register 1, a decoder 2, the first analyzer 3, the first deciding unit 4, the frequency divider 5, the dispenser gate stands 6, second and third analyzers 7 and 8, the second and third computing nodes 9 and 10, the divider into two 11, the first, second, third and fourth memory blocks 12, 13, 14 and 15, the multiplexer 16, the correction device 17, and a clock TI and information HS inputs of the device frame synchronization is connected to the corresponding inputs of the shift register 1, information outputs m0 - mn which are connected with inputs of the decoder 2, the output of which is connected to the input of the first analyzer 3, the outputs of the response Ufromand errors UOshwhich is connected to the corresponding inputs of the first critical node 4, the output of the search SP which is connected with the corresponding input of the frequency divider 5, the other clock, the input of which is connected with the corresponding input of the frame synchronization, the address outputs A0 - An is connected to the corresponding inputs of the first, second, third and chetki UCS position under synchronously D2 which is connected to another input of the first analyzer 3 and the input of the correction device 17, the output of the gate stand UCS(-1) at the position preceding synchronously one clock interval D1 is connected to the input of the second analyzer 7 and the other input of the correction device 17, the output of the gate stand PSK(+1) position following synchronously one clock interval D3 is connected to the third input of the analyzer 8 and the other input of the correction device 17, the output of the gate stand TFP under item staffing D4 is connected with the corresponding input of the correction device 17.

The output of the gate stand under CC position of the end of the cycle D0 is connected to the corresponding inputs of the correction device 17 and the divider into two 11, the output of which is connected to the inputs of the write-read C/S first, second, third and fourth memory blocks 12, 13, 14 and 15, other data inputs I of the first and second memory blocks 12 and 13 are connected with the information of the HS input device frame synchronization, outputs data D which are connected respectively to the inputs of data I of the third and fourth memory blocks 14 and 15, outputs data D which are connected respectively with the information inputs D1 and D2 of the multiplexer 16, the other address input of which is connected to the output of the divider into two 11, information visudyne with the respective input device frame synchronization, output RESET which is connected with the corresponding input of the frequency divider 5.

The entrance to the availability of the synchronization PHASE is connected with the corresponding output of the first decision making unit 4, the input correction GFR(-1) and GFR(+1) connected to respective outputs of the second and third computing nodes 9 and 10, the inputs to the availability of the synchronization PHASE, which are connected with the corresponding output of the first decision making unit 4, other inputs response Ufromand errors UOshconnected respectively to the outputs of the second and third analyzers 7 and 8, the other input of which is connected to the output of the decoder 2, the clock MINUTE information of the HS outputs and pulse output frame synchronization AIC device correction 17 are the outputs of the device frame synchronization.

The device operates as follows.

The divider 5 divides the frequency sequence of clock pulses on a clock th input unit to the repetition rate of the cycles. His address outputs A0 - an account receives signals to corresponding inputs of the distributor gate stands 6 and the address inputs A0 - An of the first, second, third and fourth memory blocks 12, 13, 14 and 15.

The dispenser gate stands 6 foretime:

output D0 - gate stand under CC position end loop;

output D1 - gate stand (PSK-1) at the position preceding synchronously one clock interval;

output D2 - gate stand UCS position under synchronously;

output D3 - gate stand (PSC+1) positions, following synchronously one clock interval;

output D4 - gate stand TFP under the position of staffing.

Group signal on the information of the HS device input frame synchronization, is fed to the data inputs I of the first and second memory blocks 12 and 13. Output data D of the first memory block 12 group signal at the data input 1 of the third memory block 14, and the output data D of the second memory unit 13 to the input I of the fourth memory block 15. In addition, the output D0 of the dispenser gate stands 6 to the inputs of the write - read C/S first, second, third and fourth memory blocks 12, 13, 14 and 15 through the divider into two 11 enters the gate stand under CC position of the end of the cycle. The first, second, third and fourth memory blocks 12, 13, 14 and 15 have two modes of operation.

In the 1st mode: - in the first and fourth memory blocks 12 and 15 PR - the C first and fourth memory blocks 12 and 15 reads data, and the second and third memory blocks 13 and 14 to their record.

With the output data D of the third and fourth memory blocks 14 and 15 group signal is sent to the information inputs D1 and D2 of the multiplexer 16, which is controlled by the output signal from the divide-by-two 11. On its informational output Y is skipped first information stream received by the information input D1 of the multiplexer 16, and through the period of the cycle stream received by the information input D2. The site, consisting of the listed devices, carries out the group delay of the signal by a period equal to two cycles, if necessary, adding additional blocks of memory latency can be increased by the time required for the subsequent signal processing. From the information output Y of the multiplexer 16 group signal is supplied to the information input of the HS device correction 17.

Not delayed group signal with the information of the HS input device frame synchronization is supplied to the corresponding input of the shift register 1, in which the record information on the positions of synchronously in the loop. The bit width m of the shift register 1 is determined by the number of elements of a message in a parallel code, enter the corresponding input of the decoder 2. When entering the shift register 1 clock, the first analyzer 3 from the output of the decoder 2 receives a signal of compliance synchronously. Proposed first analyzer 3 and the first decisive node 4 has two operating modes: mode 1 - finding, fixing and retention of synchronism; mode 2 - phase correction the clock and interval insertion.

Initially, the device frame synchronization is in the first mode. If not strobila stand UCS position under synchronously output D2 of the valve gate 6 coasters with signal matching synchronously from the decoder 2, the first analyzer 3 generates the error signal UOshthe first critical node 4 generates a detection signal SP, which phase frequency divider 5 so that the next stand UCS is formed by the valve gate stands 6 exactly one cycle plus one clock interval. Thus, an analysis of the following group of signal.

When matching stand UCS output D2 of the valve gate stands 6 with signal matching synchronously from the decoder 2, the first analyzer 3 generates a signal response Ufromthe first deciding unit 4 decides on what narushenie true singlegroup, however, to hold the device frame synchronization means, usually after repeated detection of the synchronization signal at the same positions in the adjacent cycles of the received signal.

When switching device frame synchronization on hold the first decisive node 4 generates a signal having a synchronization PHASE, which prohibits the operation of the second and third computing nodes 9 and 10, and the correction device 17. The device frame synchronization enter the second mode of operation only during the control positions of the clock.

In the case of distortion of the management team alignment is removing or adding a single clock interval. In the first case, the first deciding unit 4 receives from the first analyzer 3, the error signal UOshand ceases to generate the signal having the synchronization PHASE. Is the coincidence gate stands UCS(-1) at the position preceding synchronously one clock interval from the output D1 of the valve gate stands 6 compliance status of synchronously from the output of the decoder 2, the second analyzer 7 generates a signal responsefromreceived at the corresponding input of the second VBOs correction 17. On the information input of the HS device correction 17 receives the delayed group signal to clock the input clock pulses, the gate pad TFP under the position of staffing and the correction signal SCF(-1). The correction device 17 on the false drop generates a clock interval, the frame synchronization pulse AIC and the signal RESET phase frequency divider 5. When analyzing the positions of group signal of the next cycle, the signal response Ufromwith the release of the first analyzer 3 is supplied to the corresponding input of the first critical node 4, which confirms the presence of the device frame synchronization mode matching, generates a signal having a synchronization PHASE, preventing the second and third computing nodes 9 and 10, and the correction device 17.

In the case of a reverse interpretation of the management team alignment signal response Ufromis formed by a third analyzer 8, and the third crucial node 10 generates the correction signal SCF(+1). In this case, the correction device 17 on the false insertion removes one clock interval, generates the frame synchronization pulse AIC and phase frequency divider 5. When analyzing the positions of the next cycle, the signal response Ufrom

If the true loss of synchronism on the outputs of all analyzers are formed error signal UOshthe second and third computing nodes 9 and 10 do not produce correction signals GFR(+1), SCF(-1), which prohibits the operation of the correction device 17. The detector of the lack of synchronism of the first critical node 4 will fulfill a specified criterion output and puts the device frame synchronization search mode.

The present invention can improve the noise immunity of the device frame synchronization, since the distortion of the management team alignment does not occur, the loss of a cyclical synchronism in the instrument receiving component group of signals.

The device frame synchronization, containing the shift register, a decoder, the first analyzer, the first critical node, the frequency divider and clock TI and information HS inputs of the device frame synchronization is connected to the corresponding inputs of the shift register, the information outputs of mO - mn which are connected with the inputs of the decoder, the output of which is connected to the input of the PE the first and final node, the output of the search SP which is connected with the corresponding input of the frequency divider, the other clock th input connected to the respective input device frame synchronization, characterized in that the valve gate stands, second and third analyzers, second and third computing node, a divide-by-two, the first, second, third and fourth memory blocks, the multiplexer, the correction device, and the address outputs AO AP frequency divider connected to respective inputs of the first, second, third and fourth memory blocks and the inputs of the distributor gate stands the output of the gate stands the UCS position under synchronously D2 which is connected to another input of the first analyzer and the input of the correction, the output of the gate stand UCS(-1) at the position preceding synchronously one clock interval D1, is connected to the input of the second analyzer and the other input of the correction, the output of the gate stand PSK(+1) position, following synchronously one clock interval D3, is connected to the third input of the analyzer and the other input of the correction, the output of the gate stand TFP under item staffing D4, oedipodinae to the corresponding inputs of the correction device and the divider by two, the output of which is connected with the inputs of the write-read 3/With the first, second, third and fourth memory blocks, other input data 1 of the first and second memory blocks are connected with information HS input device frame synchronization, outputs data D which are connected respectively to the inputs of the data 1 of the third and fourth memory blocks, outputs data D which are connected respectively with the information inputs D1 and D2 of the multiplexer, the other address input of which is connected to the output of the divider by two, the information output Y of the multiplexer is connected to the information input of the HS device correction clock th input connected to a corresponding input of the frame synchronization, the output of the RESET which is connected with the corresponding input of the frequency divider, the input to the existence of a synchronization PHASE is connected with the corresponding output of the first critical node, the input correction GFR(-1) and GFR(+1) connected to respective outputs of the second and third computing node, the inputs to the availability of the synchronization PHASE, which are connected with the corresponding output of the first critical node, the other inputs of the response Ufromerrors UOshconnected respectively to the outputs of the second and third analyzers, etc is clovey synchronization AIC device correction are the outputs of the device frame synchronization.

 

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