# Three-dimensional nanostructure

(57) Abstract:

Usage: devices and structures integrated semiconductor microelectronics and silicon nanoelectronics, in particular in integrated neural structures neuro-BIS and neuro-computer. The technical result of the invention is to expand the functionality of the structure, reducing inter-element communication lines at high density three-dimensional packaging, low power consumption. The inventive three-dimensional nanostructure includes a semiconductor substrate of a certain conductivity type with a source, drain and column side surface of which is covered with the first layer by a dielectric layer, on the opposite sides of which are placed the paddles, the conductivity type of the upper layer of the substrate and of the column opposite to the base substrate, and the conductivity of the column is close to the intrinsic conductivity of the semiconductor. Offered in three-dimensional nanostructure closures on side surfaces of the column to perform in the form of floating gates, each of which bears a second dielectric layer, on which the manufactured insulated from each other n input contacts with the relevant areas and containers weighted summation by adding the charges on the floating gate of nanostructure and the corresponding threshold function. Depending on the operating conditions of the structure corresponding to the input pins on the left and right side surfaces of the column can be connected or disconnected, and the flow patterns produced as absorbing contact, made in the form of two adjacent dissimilar Schottky contacts on n - and p-type. 1 Il. The invention relates to devices and structures integrated semiconductor microelectronics and silicon nanoelectronics, in particular to integrated neural structures neuro-BIS and neuro-computer.The fundamental problem of development element-technological base UBIS is to increase the level of integration of elementary two-input logic cells (PE), bistable cells (BOJ), complex multi LAYE, their packing density by reducing the geometric dimensions in the region of hundreds of nanometers, increase intellectual capacities of the crystal at low power consumption and high system performance in the layout space of the system in the crystal.One of the most effective ways to increase the degree of integration is the transition to the design of functionally-integrated logic elements on the vertical and national opportunities more complex and flexible threshold elements, implementing a minimal three-dimensional semiconductor volume greater number of necessary universal logic functions. Known three-dimensional dvuhstvornyh MOS structure with a vertical channel [1] . This structure is similar contains a semiconductor substrate of a certain conductivity type with column side surface of which is covered by a dielectric layer, on the sides of which there are two gates, also contains a region of an opposite conductivity type, one located in the lower part of the column is the source, and the other on the top of the bar - stock. The structure refers to a purely instrumental structures, which has significant drawbacks and fundamental limitations in the organization of more complex logic elements and a significant expansion of functionality. This is because even to build a simple inverter or input LE AND does NOT require additional area on the chip and, accordingly, additional structures and elements.Known three-dimensional LAYE on the combined MOS structure with a vertical channel [2] , we use as a prototype. To extend the functionality of dvuhsotmetrovoj covered by a layer of dielectric, on opposite sides of which there are two gates, and containing the flow at the top of the column and the source, it was suggested that the conductivity type of the upper layer of substrate to use the opposite type of the base substrate, and the conductivity of the column to perform close to the intrinsic conductivity of the semiconductor, and the drain of manufacture in the form of transition metal-tunnel insulator-semiconductor.The disadvantage of this structure is limited functionality, very little flexibility is implemented in a unit volume of the crystal elementary logic functions, a sharp increase in inter-element communication lines to form a complex logical functions and functional-perfect architectures UBIS.To extend the functionality of patterns, dramatically reducing inter-element communication lines proposed in the known three-dimensional structure containing a semiconductor substrate of a certain conductivity type with a source, drain and column side surface of which is covered with the first layer by a dielectric layer, on the opposite sides of which are placed the paddles, the conductivity type of the upper layer of the substrate and of the column opposite to the basis on which nanostructure closures on side surfaces of the column, made in the form of floating gates, each of which bears a second dielectric layer, on which the manufactured insulated from each other n input contacts with the relevant areas and capacities input contact relative to the floating gate determining the weight values, and forming a weighted summation by adding the charges on the floating gate of nanostructure and the corresponding threshold function, and depending on the conditions of operation patterns corresponding to the input pins on the left and right side surfaces of the column can be connected or disconnected, and the flow patterns produced as absorbing contact, made in the form of two adjacent dissimilar Schottky contacts on n - and p-type.The proposed construction of a three-dimensional nanostructure will differ from the prototype in that depending on the voltage on the floating gate with function weighted summation by adding the charges on the floating gate when the weights will be determined by the capacitances of the respective input contacts regarding this gate in a vertical channel can be moved from the base of the column to its drain at the top of the column on slaughtery output - contact source. As a result, the runoff potential of the proposed three-dimensional nanostructure will be the threshold logic function from the weighted summation on the floating gate and the threshold value, i.e. nanostructure implements complex logic function, increases functionality and logic flexibility compared to the prototype.Thus, the proposed construction of a three-dimensional nanostructure achieve new technical result - getting a difficult threshold function of the neural element in the minimum volume of the crystal without additional inter-element communication lines required for the implementation of complex functional devices at the elementary two-input gates 2I-NOT. In the framework of nanotechnology and emerging nanoelectronic architectures using a three-dimensional nanostructure not only provides the highest density in the three-dimensional volume neuro-UBIS, but helps to eliminate and/or reduce the impact of the "tyranny of the compounds for surenthiran systems with the use of bus architectures for flexible adaptive self-organizing neural networks.Fig. 1 illustrates the proposed structure triggernometry dopant 10^{17}cm

^{-3}. In the upper part of the substrate layer formed of p-type conductivity 2 with a concentration of dopant 10

^{15}cm

^{-3}the thickness of 0.4-1 μm. To create stokovyh metal contacts 4 are formed in the p-region of the substrate signalground, with a concentration of 10

^{18}cm

^{-3}p

^{+}- region 3. In the upper part of the substrate over the p-region formed column 5 width of 50-200 nm and a height of 0.2 to 0.9 μm, filled with silicon of n-type conductivity 6, and the conductivity of the column is close to the intrinsic conductivity of a semiconductor, such as 10

^{11}- 10

^{14}cm

^{-3}. The side surface of the column is covered with the first layer by a dielectric layer 7, the silicon oxide with a thickness of 5-10 nm. On opposite sides of the column are placed the floating gates 8 and 9, for example of polycrystalline silicon n

^{+}- type conductivity. On each of the valves 8 and 9 deposited second dielectric layer 10, the silicon oxide of a thickness of 10 to 50 nm, which produced isolated from each other n input pins 11 with the numbers 1...i...n the right side and left 12, with appropriate spaces and reservoirs, determining the weights and forming a weighted summation. The corresponding input contacts on the right is absorbing contact, made in the form of two adjacent dissimilar Schottky contacts on n - and p-type 13 and 14. To create effective Schottky contacts used signalground n 15 and p-16 with a dopant concentration of about 10

^{18}cm

^{-3}.The proposed nanostructure works as follows: when applying to at least one shutter impoverishing voltage due to low alloy or unalloyed column with low conductivity is the impoverishment of the entire column, and under the appropriate shutter is formed a channel for minority carriers. If both shutter enriching voltage, a gate formed the main media. Moreover, the source of minority carriers is n layer 1, and the source of majority carriers is p layer 2. Under forward bias the corresponding p-n junction minority carriers moving to the base of the column 5 and form the induced channel. Absorbing a drain contact in the form of Schottky contacts 13 and 14 provides a flow of current of majority carriers when the potential of the drain electrode corresponding to the enrichment column, similarly provides a current flow of minority carriers at a potential corresponding to obedneny the upper electrode is enriching, if at least one shutter will be served impoverish voltage, and will impoverish, if both of the shutter will be served enriching voltage.The specifics of nanostructure floating gates such that influences all channels low-alloy column voltage signals applied to terminals 11, 12. By combining the required number of inputs 1...n to the right and to the left with the corresponding voltage U

_{1}U

_{2}U

_{n}ensures proper management of the gates 8 and 9 through capacitive coupling to the floating gate C

_{i}C

_{n}. Accumulated fixed weight determined by the capacitances of the input pins will control the currents of the main and minority carriers from the source to the drain.Isolated from each other n input contacts with the relevant areas and their barrier capacitances of the input pins relative to the floating gate will determine the weight values and shape of the target function weighted summation by adding the charges on the floating gate of nanostructure and ultimately threshold function nanoelement, Y = 1 if the sum of X

_{i}W

_{i}> h

_{i}and Y = 0 at different values of the amount according to the formula for the threshold fu is that the potential f is determined by the value of

f = (C

_{1}V

_{1}... + C

_{i}V

_{i}+ ... + C

_{n}V

_{n})/(C

_{1}... + C

_{i}.... + C

_{n}+ C

_{c})

where the full capacity of the structure C

_{t}= (C

_{1}... + C

_{i}... + C

_{n}+ C

_{c}) C

_{c}- the capacity of the actual channel, and the components of containers floating gate C

_{i}formed containers of contacts 11 and 12, V

_{i}= X

_{i}V

_{dd}V

_{dd}the voltage at the drain. In other words, the voltage on the floating electrode is the weighted sum of the charges on the gate (the weighted sum of the input voltage with a factor C

_{i}/C

_{t}).As soon as the potential f exceeds the threshold voltage V

_{t}symmetrical for "virtual" MOS transistors in the structure, the channel becomes conductive. Moreover, the threshold voltage V

_{t}largely controlled by the potential f.Thus, in a three-dimensional nanostructure implemented higher functionality, higher logical flexibility in high-density packaging, with a corresponding reduction in inter-element communication lines. Technical and economic effect of the present invention is to increase the logical flexibility in the minimum volume of the crystal, which allows decides the BIS, b) low reliability of systems with a large number of communication lines; "the tyranny of interconnection" with the increase of the power consumption and loss of system performance in subsystems UBIS increasing their degree of integration.Sources of information

1. Application EP 0149390.2. Microelectronics, 1996, vol 25, N 2, 112-115 C.; Rakitin centuries Application N 95111511. Three-dimensional nanostructure containing semiconductor substrate of a certain conductivity type with a source, drain and column side surface of which is covered with the first dielectric layer, on the opposite sides of which are placed the paddles, the conductivity type of the upper layer of the substrate and of the column opposite to the base substrate, and the conductivity of the column is close to the intrinsic conductivity of a semiconductor, characterized in that the valves on the side surfaces of the column is made in the form of floating gates, each of which bears a second dielectric layer, on which the manufactured insulated from each other n input contacts with the relevant areas and capacities input contact relative to the floating gate, determining weight values, and forming a weighted summation by summing terms of the operation patterns corresponding to the input pins on the left and right side surfaces of the column can be connected or disconnected and the flow patterns produced as absorbing contact, made in the form of two adjacent dissimilar Schottky contacts to p - and R-type.