The semiconductor device memory to achieve high performance and the way it signal tyres


G11C11/407 -

 

(57) Abstract:

The invention relates to a semiconductor device memory. The technical result is high performance specified device without using a separate local bus I / o connection bit bus and the host bus I / o. The device includes memory banks, the set of bit tyres, tyre I / o data (signal tyres, tyre column selection signal tyres), word of tyres, main bus data I / o, the read transistors, the transistors for the record, the multiplexer. The method describes the location therein of the signal buses. 2 S. and 1 C.p. f-crystals, 13 ill.

Prior art

The invention relates to a device of a semiconductor memory and, in particular, relates to devices semiconductor memory and method of execution in it signal tyres, which can provide high performance through the creation of the architecture of the crystal, including multiline input/output (I / O).

One of the most important aspects in the design of semiconductor devices memory is the choice of the appropriate architecture of the crystal. From the architecture of the crystal depend on such indicators of quality of the measures of the crystal, and so p. in Other words, the exceptional flexibility of the architecture of the crystal contributes greatly to the satisfaction of the requirements for these parameters. Specialists are well aware that in practical development of the architecture of the crystal flexibility of the architecture of the crystal allows you to maintain unchanged the basic structure in the event of a change and the introduction of additional peripheral devices and increase the density of semiconductor devices memory. The flexible architecture of the crystal makes it easy to adapt to these variations. The purpose of developing devices semiconductor memory is to achieve high performance, commensurate with the capabilities of the device semiconductor memory of high density. In other words, the concept device, the semiconductor memory has changed from simple devices high density memory to the new memory device having high performance and synchronized with the speed of the system. For example, in the case where the memory device has 64 MB (M) or more, in particular, to a dynamic random access memory (RAM) bus direct access or synchronous dynamic RAM) when the basic version of the dynamic RAM 256 M, for operating the semiconductor memory towards higher performance the architecture of the memory device with the parent version of the 256 bits must have the internal capacity of 256 bits (for one cycle). The developers of memory devices of all manufacturers are looking for architecture, with the highest possible performance. Meanwhile, the higher the density of the memory device, the larger the size of the crystal. In the result of difficulties with reading and writing data because of the increased load of each bus. These difficulties necessitate the creation of a new architecture.

In Fig. 1 shows the architecture of the crystal at 256 M in the known device a semiconductor memory. In addition, the circuit implementation of internal columns based on the architecture of the crystal shown in Fig. 1, is disclosed, for example, in U.S. patent N 5247482, entitled "Semiconductor Memory Device With High Speed Write Operation" ("the Device is a semiconductor memory with high-speed write operation"). When choosing a known structure with collapsed bit tire to obtain dynamic RAM (DRAM) 256 M will need word bus 32 To the bus 32 To the word and bit bus 16 To bus to 16 bits). Of course, 512 cells can be connected to one of bit bus, but it is connected to one of bit bus 256 cells. Thus one word bus can be activated matrix with dimension 2 M Thinking that the update cycle corresponds to a certain time, the gate signal line addresses thereby all 256 M will be activated matrix 8 M If the matrix shown in Fig. 1, is activated and two pairs of tires I / o are located in the area of the read amplifier, the amount of data available in the matrix 2 M, is equal to 4 bits, and this number corresponds to the number of bus IO. Thus, all 256 M can be accessed 16-bit data. Because it is very different from the desired internal performance of 256 bits, the practical achievement of high performance impossible. In addition, high performance cannot be achieved with the above architecture of the crystal. Also in this architecture, the crystal load bus I / o and load transistors keys for connecting bus I / o bit to the bus is high, which can lead to difficulties in forming an adequate level of voltage at bus I / o when performing read operations. In addition, when performing write operations, because the bus I / o data shown in Fig. 1, directly connected to the bit bus through the key transistor, the load on the connection and the bit bus is unacceptable. For this reason, we can assume that the structure in Fig. 1 is unfit to give the ikovoy memory which can be achieved better performance compared with the structure in Fig. 1, and in which the loading of the tire of Fig. 1 is significantly reduced. The diagram in Fig. 2 is disclosed in "Circuit Techniques For a Wide Word I/O Path 64 Mega DRAM" on SS. 133-134 article "1991 Simposium on VLSI Circuits". The above article will be useful for understanding the details of Fig. 2. In Fig. 2 load bus I / o is reduced through the use of subsidy I / o and local bus I / o. Also, a predetermined number of read amplifiers connected to subside I / o to transfer data to the local bus I / o through a differential amplifier. This known technique gives some increase internal productivity, but has the disadvantage that the number of n-MOS (NMOS) transistors, through which data is transmitted, is high when the recording operation. In Fig. 3 presents a block diagram showing bus I / o data in Fig. 2. When the write operation, the data on the local bus I / o is transmitted to the transistor 2 of Fig. 2 through the signal SEC SELECT bearing column data of the selected block, but if to determine subsidy I / o signal YWRITE, data PE bus from a variety of bit of tyres, connected to one subshine I / o, data is transmitted on bit bus through the transistor 10. As mentioned above, when the write operation, the data transfer is performed from the bus I / o bit to the bus only three n-MOS transistor, which is a serious disadvantage when performing a write operation in the memory device with a high degree of integration, with a large load of tires.

The invention

Thus, the aim of the present invention is to provide a device of the semiconductor memory and a method for arranging therein the signal tyres, which are implemented by creating an architecture of the crystal, which can be achieved high performance.

Another objective of the present invention is to provide a device of the semiconductor memory and a method for arranging therein the signal tyres, which are implemented by creating an architecture of a crystal, in which the operations of reading and writing can be performed high-speed data access.

Another objective of the present invention is to provide a device of the semiconductor memory and method for disposition therein of the signal channels, which can solve the problem of loading bit of tire Vo semiconductor memory and a method for arranging therein the signal tyres, implemented by creating architecture of the crystal, which can be achieved with high efficiency without using a separate local bus I / o connection bit bus and the host bus I / o, and the write operation can be performed with high speed.

To achieve these and other goals of a device of the semiconductor memory implemented by creating architecture of the crystal, which can be achieved the required high performance.

According to one aspect of the present invention the device is a semiconductor memory has an architecture in which a set of bit tire, transmitting data to multiple memory cells connected to the respective busbars input-output data, each of which is connected independently of the other, thus achieving high performance.

According to another aspect of the present invention the device is a semiconductor memory includes lowercase decoders for the location of many base tire along the crystal and decors columns for the location of the bit set of tires and set tire choice column in the transverse direction with respect to the length of the crystal.

According to another aspect of the present invention the device is a semiconductor memory includes a matrix consisting of a set of reference blocks, holds many memories; many base tire along the crystal; the set of bit tire, perpendicular to the crystal, and each pair of bit tire consists of bit bus and complementary (additional code) bit bus; many buses I / o data placed in the upper part of the matrix and running in the transverse direction, moreover, each pair of tires I / o data consists of bus I / o data and complementary bus I / o data and one after the other they are connected to each pair of bit buses; and many tyre choice column, placed in the transverse direction adjacent to the bus I / o data and complementary bus I / o data, to control the connection of each pair of bit tire to tire of input-output data.

According to another aspect of the present invention the method is from a lot of thrust blocks for storing multiple memory cells, placed in a matrix form; the location of many groups of tires for selecting rows of memory cells, and word bus pass along the crystal; the location of the set bitmap tyres, passing across a crystal, for selecting columns of memory cells, and each pair of bit tire consists of bit bus and the complementary bit bus; the location of the set of tires I / o data placed in the upper part of the matrix and running in the transverse direction, and each pair of tires I / o data consists of bus I / o data and complementary bus I / o data, they are connected one after another to each pair of bit buses; and the location of many tyre choice column, placed in the transverse direction between bus I / o data and a complementary bus I / o data control connecting each pair of bit bus to the bus I / o data.

The first object of the invention is the device of a semiconductor memory comprising memory banks, each of which contains submatrices memory consisting of a single matrix, activation of memory cells along a line which is in the direction of many groups of tires, while the set of bit tyres, multiple bit tire consists of bit bus and the complementary bit bus, for selecting a column of memory cells, each pair from a set of tyres I / o consists of bus I / o data and complementary bus I / o data between a layer where the bus data I / o and bus column selection, and the substrate layer are bit of the tire and the base layer of the tire, and the tire column selection feature related to the corresponding bus I / o data and complementary bus I / o data, and to connect the base of the tire is intended line decoder to connect bitowych tire is the column decoder, and in every single matrix included scheme bit bus in which to perform the read operations is the bus select signal read by means of which selects one pair from the set bit of the tire, connected to one pair of tires I / o in accordance with the entered address column, through the respective transistors of the read, which transmit the data stored in the memory cell for write operations is the bus select signal recording, by means of which selects one pair from the set bit of the tire, connected to one pair of tires I / o, and p is i.i.d. address column, moreover, when the write operation, the data is first passed to the main bus I / o, and then through the multiplexer serves in bus I / o data.

The second object of the invention is a method for arranging signal tyres device, semiconductor memory, according to which link a matrix consisting of a set of memory cells have many word pairs of tires to select rows from a set of memory cells, and each of the word pairs of tyres fitted along the crystal, have many pairs of bit of tyres to select columns from a set of memory cells, and each pair of sets of bit tire consists of bit bus and the complementary bit bus and it is placed in a transverse relation to the length of the crystal direction, have many pairs of tires I / o data (signal wire) above the matrix in the transverse direction of the crystal, and each pair of the multiple pairs of tires I / o consists of bus I / o data and complementary bus I / o data, and each of which is capable of connecting to each pair of the multiple pairs of bit of tyre, thus have many tires column selection signal tyres) related to PA.

The invention is illustrated by reference to the accompanying drawings, in which similar positions indicate the same or similar elements:

Fig. 1 is a block diagram illustrating the configuration of the architecture of the crystal in the known device a semiconductor memory;

Fig. 2 is a diagram illustrating the configuration of tires I / o data in the known device a semiconductor memory;

Fig. 3 - scheme of the tires I / o data;

Fig. 4 is a block diagram illustrating the configuration of the architecture of the crystal with multilines I / o device of a semiconductor memory in accordance with the principles of the present invention, and Fig. 4 consists of Fig. 4A and 4B arranged in parallel;

Fig. 5 is an illustration of an example implementation of the method of the location of the tires I / o data and tires column selection Fig. 4;

Fig. 6 is a detailed circuit diagram illustrating an embodiment of the control circuit columns in the architecture of the crystal in Fig. 4;

Fig. 7A and 7B is a timing diagram illustrating read operations and write performed by the circuit of the read bit bus 24 of Fig. 6;

Fig. 8 is a block diagram illustrating the path of the I / o data in Fig. 6;

Fig. 9 is a block diagram illustrating a variant of the re is th multiplexer 60 in the multiplexer 20 of Fig. 9; and

Fig. 11 is a variant of the circuit design for generating a signal IOPP input to the multiplexer 20 of Fig. 10.

A detailed description of the preferred options for implementation.

In the following description, some specific details, such as the vertical structure of the tire input-output readout circuit bit bus multiplexer and so on , designed to provide a comprehensive understanding of the present invention. Professionals should be clear that can be offered to other embodiments of the present invention without these specific details, or with alternative private parts.

Used herein, the term "identity matrix" refers to a matrix of cells that can be activated by one word bus. The term "submarine" is used to describe the matrix of cells that can be selected by one small group of decoders and one group of column decoders, and this sublattice consists of a set of singular matrices with a common bus data input / output connected to one group of multiplexers.

Fig. 4 is a block diagram illustrating the configuration of the architecture of a crystal having Multikino I / o is composed of Fig. 4A and 4B, located in the crystal in parallel. The subsequent description of the architecture of Fig. 4A, 4B is carried out in comparison with the known architecture of the crystal shown in Fig. 1. In Fig. 4 presents the architecture of the new crystal in accordance with the principles of the present invention, which embodiments are considered DRAM 256 M In the figure has four banks, two of which are placed in the upper and lower parts of Fig. 4A, and the other two placed in the upper and lower parts of Fig. 4B. Digital reference 22 denotes one submarine, and 12 denotes one single matrix. As shown in the figure, in the Bank there are two submatrices 23, and in one submatrices 12 contains 16 single matrix 12. One is the identity matrix 12 is 2 M (M is equal to 220), one submarine 22 contains 32 M, and one Bank contains 64 Meters In the same time line decoder 18 is in the vertical direction with respect to the length of the crystal (through 64 M is divided into 32 M), and activation of memory cells, as shown in Fig. 4, is made in the direction of the base tire. Thus, activation of the unit matrix, are compared one to another on the same bus along the crystal.

In the above configuration bitoy tires. For two adjacent submetric 22 in one of the banks in Fig. 4A or 4B on the same matrix shown only bus I / o data 10, and the other shows only tires column selection CSL. This is done to facilitate understanding of the configuration of tires I / o 10 and tires column selection CSL. Each submatrices 22 has the same number of tyres I / o data 10 and tires column selection CSL, as shown in the figure. At the same time in order to avoid mutual influence of signals, it is desirable that the tires column selection, and bus I / o data 10 and the complementary bus I / o data were not located next to each other. The main feature of the architecture shown in Fig. 4, is that it can be read large amount of data per unit of time without the use of local bus I / o data shown in Fig. 2, and the write operation can be performed with high speed. This will be explained below.

Here and further discussed the way to achieve high performance in the architecture of the crystal, constructed in accordance with the present invention, the above-described configuration. Identity matrix 12, as basic building blocks form submatrices 22 to 32 M, which consists of 16 sets of 128 blocks on the in X 16) pairs of bit buses. Here, if the operation data update unit 16 K in one Bank at 64 M activates one word bus and matrix 2 M, and the number of tires I / o data in the matrix 2 M will be: If 2npairs of bit tire connected to a single bus I / o, is formed 4096/2n(equal to 2m) pairs of tires I / o. If through the multiplexer 20 is combined predetermined number of tires I / o, can be obtained from the 2khost bus I / o M10 (in pairs). In other words, at the time of activation of signal line addresses in the matrix 2M, as shown in Fig. 4, is a 4096/2n(equal to 2m) tire data I / o and 2khost bus I / o data M10. In General, 256 M can be obtained 2kx 4 bit data. For example, if connecting 8 pairs of bit of tire on the same bus I / o data number of pairs of tires I / o data in the matrix 2 M will be 512 (2n= 8), and in the case of connecting 8 pairs of tires I / o data to a single master bus I / o data M10 number of pairs of main buses I / o data M10 will be 64. Therefore, if one submatrices 22 there are 64 pairs of main buses I / o data 10 M, 256 M in General can be obtained 256 bits of data. Ago the number of bits in a device of the semiconductor memory, has the possibility of flexible adjustment of the number of pairs of bit of the tire, connected to bit bus I / o data, and the number of pairs of tires I / o data, connected to the main bus data I / o 10 M.

Fig. 5 shows an example of the method for the location of the tires I / o data and tires column selection Fig. 4 and is useful for understanding the architecture shown in Fig. 4. In Fig. 5, each of the tires column selection CSL is located between each of the tire data I / o 10 and each of the complementary tyres input / output data in the crystal. At the same time, if you compare the architecture in accordance with the present invention with a known architecture, and even if we assume, as shown in Fig. 2, the location of the signal buses, with bus I / o data and column data, because from the point of view of reducing the size of the crystal on each bit of tire you want information signal S/A SELECT bit bus, organized in a different direction from the bus I / o data, the information signal S/A SELECT will require bus I / o bus SEC SELECT, load-bearing column data, YREAD and YWRITE in the same direction relative to each other. That is, in the same direction each WRITE. To achieve high performance will inevitably need a lot of tires I / o data. For this reason, in the basic structure, you must have at least four tires with a recurring location, which leads to an increase in crystal size. However (Fig. 5), due to the fact that bus I / o data and tires column selection are repeated triples the size of the crystal thereby reduced. In addition, since the layout of the crystal is made on the upper part of the matrix, may be placed the required number of tires I / o data that is required to achieve high performance. At the same time as the tire of choice column is located between buses I / o data, the possibility of interaction, usually taking place between buses I / o data 10 and the minimum. As the tyre of choice column are not adjacent to each other, they achieved a similar effect. Of course, it should be clear that the arrangement shown in Fig. 5, showing one of the preferred variants of realization of the present invention. In addition, as shown in Fig. 5, on the substrate crystal, between the layer where the bus data I / o 10 and Shi is e tires are located in the same longitudinal direction, what bus I / o data 10 and tires column selection CSL, and parallel to each other. Word tires are perpendicular to the tires I / o 10 and the bus column selection CSL of Fig. 5 the way the tires I / o data 10 and tires column selection CSL is implemented by a base structure having a three-CSL-10 tires, but it should be noted that can be built and other recurring underlying structure, such as, for example, 10-CSL - or 10-CSL.

In Fig. 6 shows a detailed circuit implementation of the control option on the columns, that is, the read bit bus architecture of the crystal in Fig. 4. In Fig. 6 diagram of the read bit bus, a dotted block 24 is directly associated with the read operation bit bus. In the circuit configuration of the read bit bus 24, the read amplifier consists of a read amplifier p (positive)-type 32 and amplifier read n (negative)-type 34, which are mounted on the bit tire BL and for the formation level of the data transmitted through the bit buses. In addition, a transistor for write-36, is connected by its drain to the bus I / o data 10, passes a signal record selection WS, and a transistor for write-38 transmits the select signal with the second one and the same) and connects the source of the transistor for writing 36 bit bus BL. Transistor for charge 40 transmits the signal of the column selection CSL and its source connected to ground GND, and the transistor for writing 42, is connected by its drain to the bus output data passes a signal record selection WS. Transistor for write-44 transmits the signal of the column selection CSL and connects the source of the transistor to write 42 to bit bus and a transistor for reading 46 to its gate connected to bit bus BL and its source to the drain of the transistor to charge 40. Transistor for reading 48 transmits the select signal read RS and connects the drain of the transistor for writing 46 bus I / o data and a transistor for reading 50 its gate connected to bit bus and its source connected to the drain of the transistor to charge 40. Also the transistor for read 52 transmits the select signal read RS and connects the drain of the read transistor 50 bus I / o data 10.

At the same time, in addition to the items described above, a memory 26, which is selected by activation of the word tires WL, schema alignment 281 to align the signal level of the left bit of the tire BL and the selection transistor 30G to select the right bit of tire BL and These elements are, of course, known specialisterne 10 and the signal of the column selection CSL, that is, in the direction of the base tire WL. The control signals in Fig. 6, namely, EQ1, ISOI, LA, ISOJ and EQJ discussed in the patent application Korea N 92-12436, filed July 13, 1992 by the present applicant and entitled "a row redundancy circuit sharing a fuse box. It should be noted that such circuit configuration of the read bit of the tire 24, shown in Fig. 6, can be made different in accordance with the architecture of the crystal in Fig. 4 according to the present invention.

The explanation of such operations, such as read and write data in the cell is performed by the circuit of the read bit bus 24 will be in detail given with reference to Fig. 7A and 7B.

First, it is well known that when performing a read operation (Fig. 7A) row address and column address are input synchronously with the activation of the gate signal line address strobe signal, the column address and then indicated a specific memory cell. In the present invention shows a variant implementation, where considered DRAM 256 M 256 bits of data. As noted previously in connection with Fig. 4, a pair of tires I / o data of the connected 8 pairs of bit buses. Thus, one bus column selection CSL selects eight pairs of bit of the tire, connected to a particular pair of tyres in the eight pairs of bit buses. Here, the select signal read RS is formed in the form of a certain combination of decoded address DCA 0, 1 and 2. Then (Fig. 6) the data stored in the memory 26, is transmitted to the bit bus BL through activation code bus WL, and is generated by a potential difference between the bit tire BL and in accordance with the data level, thus raising the potential of using the read amplifier n-type 34. However, only one of transistors for reading 46 and 50 are included in accordance with the voltage level on bit tire BL and At the same time, the transistor for charge 40 in advance is enabled by the signal of the column selection CSL. Each of the transistors for reading 48 and 52 is enabled by the select signal read RS. Then pre-announced to the tires of the data output 10 or the voltage goes down depending on specific ways to switch mentioned above. The result is the voltage difference between the tyres output 10 and this generated voltage difference is amplified with the amplification device, such as an amplifier of the read data I / o (not shown, it is not necessary, if between buses I / o data 10 and formed a large enough voltage difference), thereby vybiraetsya one of the n pairs of bit buses (in the present invention n is equal to 8) and the selected pair of bit tire is connected to the bus I / o data through the transistor for read 48 or 52. And through previously reviewed the data path with bit bus is transmitted to the main bus I / o data 10 M.

Since the identity matrix 12 includes 16 basic blocks 128 and at the same time, the number of host bus I / o data M 10, transmitting data to one base unit, equal to 4 through 64 main bus I / o data 10 M, you can get 64 bits of data in one submatrices 22 (see Fig. 4).

On the other hand, when performing a write operation (Fig. 7B), when certain data is received through the input buffer data (not shown) from the outside of the crystal and then transmitted to the main bus I / o 10 M or transmitted data are in bus I / o data 10 or the write Operation data is transferred at high speed through the turn signal column selection CSL for a particular selected column and the recording signal WS (which selects one of the eight pairs of bit buses) through the transistors to record 36 or 42 and 44, that is, two n-MOS transistors.

Fig. 8 is a block diagram illustrating the path of the input-output data Fig. 6, which schematically shows the processes of the operations read and write.

If the architecture is built in accordance with the principle of nastojasih shown in the figure, it is not required. Therefore, the problem of load tyres can be found by using only the host bus I / o data and tires I / o data, which reduces the problem of load in comparison with the variant in Fig. 2. In addition, the architecture, constructed in accordance with the principle of the present invention has obvious advantages from the point of view of increasing the recording speed and reduce the size of the memory device of high density compared with the architecture in Fig. 2. In a known prototype in the direction of the columns are five signal tyres, for example, local bus data I / o LOCAL I/O subshine I / o data SUB 10, the signal bus on the record YWRITE, signal bus enable read YREAD and bus column selection CSL. However, in the present invention has three signal bus, for example, the main bus I / o 10 M, bus I / o 10 and bus column selection CSL. This contributes to a higher degree of integration of semiconductor memory. Also, if the architecture is built in accordance with the principle of the present invention, the word WL bus, the bus selection read RS and bus record selection WS are set in the direction along the device is anticolana word bus, allowing more effective to receive and to generate the set of data bits. As described earlier, in the case of compound 2npairs of tires I / o data with a pair of tires I / o data, you will need 2mpairs of tires I / o data and 2mpairs of tyres in the selection column, respectively. Thus, the base unit according to the present invention has an arrangement in which a pair of tires I / o data and one bus column selection regularly arranged in the direction perpendicular to the word bus. This leads to reduction of the area of the wiring required to retrieve a data set of input-output.

Meanwhile, the structure for multiplexing tires I / o data 10 and the host bus I / o data 10 M will be described with reference to Fig. 9. This figure shows an embodiment of the multiplexer 20 of Fig. 4, in which many separate multiplexers 60 is part of a single multiplexer 20. Because of the architecture of Fig. 4 is constructed to output 256 bits of data, you can take that one single multiplexer 60 has eight pairs of tires I / o.

In Fig. 10 shows a diagram illustrating an embodiment of the single multiplexer 60 in multiplexor main bus I / o data 10 M, which passes a signal of the column selection CSL and its complementary signal transmitting key 64, installed between the complementary bus I / o data and the main bus I / o data which transmits the signals to the column selection CSL and logical-OR-NO 68, the inputs of which are served complementary signal of the column selection and signal IOPP; p-MOS transistor 70, which transmits the output signal of the logic element OR NOT 68 and connects the main bus data I / o 10 M and to align the two signal buses; and p-MOS transistors 72 and 74, which together transmit the output signal of the logic element OR NOT 68 and channels are arranged in parallel between the main bus I / o 10 M and for recharging each of the two signal buses. It should be noted that the structures in Fig. 9 and 10 is activated, only the selected bus I / o data 10 and the corresponding bus column selection CSL, which provides the transmission output to the master bus I / o data 10 M and

In Fig. 11 shows an embodiment of the circuit for generating the signal IOPP, which is introduced into the multiplexer 20 of Fig. 10. In Fig. 11 processes the activation of the input signals DSA and COL have been described with reference to Fig. 7.

Hot is about to be clear, what is acceptable changes in form and detail, if not leading to deviation from the essence and scope of the present invention.

As explained earlier, the device is a semiconductor memory and a method for arranging therein the signal tyres, which are implemented using the architecture of the crystal to achieve high performance without increasing the size of the crystal. In addition, the device is a semiconductor memory and a method for arranging therein the signal tyres have the advantage that the layout of the tire in the direction of columns and rows can be made in simple manner through the activation of matrix in the longitudinal direction of the crystal, and the urgency of loading tire can be reduced, since there will be only two bus I / o data used for data transfer between the matrix of cells and terminals I / o of the crystal. In addition, the device is a semiconductor memory and a method for arranging therein the signal tire has the advantage that the required high level of performance can be achieved by changing the connections of bit of tyres and tyre data I / o, and W includes memory banks, each of which contains submatrices memory consisting of a single matrix, activation of memory cells along a line which is in the direction of many groups of tires, while the set of bit tyres, tyre I / o and tires column selection feature perpendicular to the base tire, and each pair of sets of bit tire consists of bit bus and the complementary bit bus, for selecting a column of memory cells, each pair from a set of tyres I / o consists of bus I / o data and complementary bus I / o data, characterized in that between the layer where are the tires I / o data and tires column selection, and the substrate layer are bit of the tire and the base layer of the tire, and the tire column selection feature related to the corresponding bus I / o data and complementary bus I / o data, and to connect the base of the tire is intended line decoder for connecting bit tire is the decoder of the column, and in each single matrix included scheme bit bus in which to perform the read operations is the bus select signal read by which to choose one pair is lbca, through the respective transistors of the read, which transmit the data stored in the memory cell for write operations is the bus select signal recording, by means of which selects one pair from the set bit of the tire, connected to one pair of tires I / o, which transmit data in the memory cell through the respective transistors for recording in accordance with the entered address column, and when the write operation, the data is first passed to the main bus I / o, and then through the multiplexer serves in bus I / o data.

2. The way the signal tyres device, semiconductor memory, according to which link a matrix consisting of a set of memory cells have many word pairs of tires to select rows from a set of memory cells, and each of the word pairs of tyres fitted along the crystal, have many pairs of bit of tyres to select columns from a set of memory cells, and each pair of the multiple pairs of bit tire consists of bit bus and the complementary bit bus and it is placed in a transverse relation to the length of the crystal direction, have many pairs of tires I vyushin I / o consists of bus I / o data and complementary bus I / o data and each of which is capable of connecting to each pair of the multiple pairs of bit tyres, characterized in that you have many tires column selection (signal) related to pairs of tires I / o data and complementary tires I / o data.

3. The location of the signal buses in the device of the semiconductor memory under item 2, characterized in that each bus column selection feature between bus I / o data and a complementary bus I / o data corresponding pair of tires I / o.

 

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FIELD: radio engineering, communication.

SUBSTANCE: device contains at least two data channels; At least two memory chips installed one on top of another in the form of a stack. The memory chips include at least two memory units and at least a portion of the first data channel and a second data channel portion; And at least the first and second chip-chip connections. The first chip-chip connection is configured to connect the respective portions of the first data channel included in the first and second memory chips to form a first data channel, and the second chip-chip connection is configured to couple corresponding portions of the second transmission channel data included in the first and second memory chips to form a second data channel. Each of the communication channels thus formed is selectively connected to the first and second memory units included in the first chip of the memory and to the first and second memory units included in the second memory chip. Each of the memory units included in the first memory chip is configured to provide data into one channel from the formed data channels, and each of the memory units entering the second memory chip is configured to provide data to another channel from the generated data channels.

EFFECT: increase the data transfer speed and system memory bandwidth.

25 cl, 10 dwg

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