Device priority service requests
(57) Abstract:The invention relates to computer technology and can be used for priority service requests. The technical result is to increase the reliability and speed. The device contains a register of requests, the element OR generator of clock pulses, counter, multiplexer, the key decoder. 1 Il. The invention relates to computing, and in particular to a device priority service requests.A device for the priority service requests , containing a register of applications, the inputs of which are connected to the information input device, the registers of priority items AND, OR, the counter, the outputs of which are connected with the first inputs of the circuits compare the outputs are connected to first inputs of elements And the first group, and the counting input of the counter is connected to the output element And the first inverted input of which is connected to the zero input trigger control, a single entrance through which the first element OR is connected to control inputs of the device with a single input counter and the pulse generator.The disadvantage of this device is the limited availability of FUM priority is very large, in some cases, is illegal and may result in the loss of low-priority applications.The closest technical solution to the present invention is a device for servicing requests , which allows to extend the functionality of the device by ensuring that the waiting time to service requests and contains the register of applications, registers of priority made in the form of a summing counters, two groups of elements, And two groups of elements, OR a counter, a pulse generator and a frequency divider.The disadvantage of this device is low speed, the greater complexity and, consequently, low reliability.The purpose of the invention is to enhance reliability of the device by reducing its instrumental composition and performance of the device due to the formation in each cycle of operation of the queue at the service of all submitted applications, including low priority.This objective is achieved in that the device priority service requests containing the register of requests, a single input bits which is connected to the information input device, and outputs connected to the inputs of the OR element, the output of which coeditor device, and the output connected to the input of the counter inputs of the multiplexer, the keys and the decoder. The information inputs of the multiplexer connected to the outputs of the bits of register requests, control inputs connected to the outputs of the counter to the inputs of the decoder, the outputs of which are connected to the zero inputs of the respective bits of the register requests and information input keys, a common control input which is connected to the output of the multiplexer, the outputs of the keys are connected with the outputs of the device.Diagram of the device shown in the drawing (Fig. 1).Device priority service requests contains a register of requests 1, item OR 2, clock 3, the counter 4.Isolated inputs bits of register requests 1 with information inputs 5 receives the service requests application, setting the appropriate bits of the register in one state. Requests have their own priorities, rigidly associated with the bits of the register.The outputs of the bits of register requests 1 are connected to the inputs of the OR element 2, the output of which is connected with the allow of the entrance 6 of the clock 3. Prohibit entry 7 clock 3 is connected with the control decoder 10 and the keys 11.Informational inputs 12 of the multiplexer 9 is connected to the outputs of the bits of register requests 1, the control inputs 13 are connected to the outputs of the counter 4, the inputs of the decoder 10, and informational inputs 14 keys 11. The outputs of the decoder 10 is connected to the zero inputs of the respective bits of the register queries 1. Common control input 15 of the keys 11 is connected to the output of the multiplexer 9. Outputs 16 keys 11 are the outputs of the device.Device priority service requests is as follows.Isolated inputs bits of register requests 1 with information inputs 5 requests maintenance requests. A query that has a certain priority, sets the corresponding bit of register requests in one state. From the output of register requests 1 pings each of your lines of communication are received at the inputs of the OR element 2. When there is at least one request in the register 1, the output signal from the OR element 2 is supplied to an enable input 6 clock pulses 3 and runs it. The output signal of the oscillator 3 is coming to the counting input of a binary counter 4, which starts to work and generate on their outputs the sequence will stopout on the control inputs of multiplexer 13 9, the information input 12 which receives signals from the outputs of the bits of register requests 1, consistent with the priorities of the applications received. When matching the priority of the service request another application with binary code generated at the outputs of the counter 4, the output of the multiplexer 9 is formed of a single signal, which, acting on a common control input 15 of the keys 11, provides for the issuing of the code numbers of the most priority application on the outputs 16 of the device, from where he entered the service system and initiates the procedure for maintenance of the application. Simultaneously, the binary counter 4 is fed to the inputs of the decoder 10, the corresponding output of which is formed of a single signal. This signal sets the zero state of the corresponding bit of register requests 1, thus allowing the new application of this priority.Counter 4 continues to set the sequence number of priority applications until, until you come to the initial zero state. At each step repeats the same procedure of comparing the priority of the next application with the generated counter 4 code priority.If no service request of the i-th application, the corresponding also be zero. The device then verifies the availability of a request from another application with a lower priority.Thus, one cycle of operation of the device in the back-end system will be generated service requests according to their priorities.After queueing service system via the control input 8 of the device outputs a signal prohibiting the operation of the clock 3. The next cycle of Queuing of requests for service will begin only after servicing system will remove the inhibit signal from the control input 8 of the device.Since the proposed device, in comparison with the prototype  total number of items reduced by approximately two times due to the exclusion of registers-counters priorities, schema comparison, elements And the first and second groups, and also controls the starting and stopping of clock pulses, it reduces the failure rate of the device is approximately two times and, consequently, to improve reliability of the device.The increased performance provided by the fact that, firstly, the formation of the signal service ueatrtov register requests is carried out continuously during the cycle of operation of the device without stopping the clock, unlike the prototype, where the clock stops whenever it detects a request from the application with the highest priority. This improves throughput, especially in the presence of multi-service systems.In addition, it should be noted that during the cycle of operation of the device serves all applications, including low-priority. Thus, the goal has been achieved.Literature
1. USSR author's certificate N 475622, G 06 F 9/18, 1975.2. USSR author's certificate N 898435, G 06 F 9/46, 1982 - prototype. Device priority service requests containing the register of requests, a single input bits which is connected to the information input device, and outputs connected to the inputs of the OR element, the output of which is connected to allow the generator input clock pulses, prohibiting the entrance of which is connected with the control input device and the output connected to the input of the counter, characterized in that it additionally introduced multiplexer, the keys and the decoder, the data inputs of the multiplexer connected to the outputs of the bits of register requests, opravlyaushi testwuide bits of register requests and with the information input keys, a common control input which is connected to the output of the multiplexer, the outputs of the keys are connected with the outputs of the device.
FIELD: computer science.
SUBSTANCE: device has n-byte query register, query limits location systems, each of which consists of counting timer and OR element, OR element, AND element, keys cascade.
EFFECT: higher reliability and speed of operation.
FIELD: method and device for processing data for preserving recurrent status in data processing device.
SUBSTANCE: device has data processing block, having multiple functioning modes, for each of which special memory stack is present. Method describes operation of this device. Data carrier contains program, configuring data processing device for performing stages of method.
EFFECT: decreased size of code and decreased interruption processing delay.
3 cl, 16 dwg
FIELD: engineering of information processing systems.
SUBSTANCE: system contains master-system for processing information, interface, central communication device, client system for processing information, object model. In accordance to method each master system sends to central communication device elements of its data array determined in appropriate master-representation, while in master-representation of connected master system elements of data array are contained, for which system has data priority.
EFFECT: simplified specification and development of interfaces between technical applications.
2 cl, 6 dwg
FIELD: engineering of interrupt processing mechanisms in computer systems.
SUBSTANCE: system contains processor with multiple contexts for execution of commands stored in memory. In response to common interrupt logical processors of processor with multiple contexts compete for receiving access to jointly utilized register. First logical processor gaining access to aforementioned jointly utilized register processes common interrupt. Remaining logical processors return from interrupt.
EFFECT: increased productiveness of system.
4 cl, 5 dwg
FIELD: computer engineering, possible use in data exchange systems and local computing networks.
SUBSTANCE: device contains N≥2 client blocks, clock impulse generator, N client time controllers, OR element, AND-NOT element, selector-multiplexer, two N-input AND-NOT elements, two priority encoders, main wait time controller.
EFFECT: increased probability of timely servicing of clients under conditions of real functioning process of data exchange systems, with continuous dynamics of change of modes of different priority requests from clients.
4 cl, 7 dwg
FIELD: engineering of computers for controlling memory, in particular, external memory controllers.
SUBSTANCE: memory control device for operation in memory controller network contains memory controller being an owner unit, capable of controlling the blocking of certain data area during execution of input-output outputs, and component for exchanging messages, providing for transmission of at least one message with blocking request, permission of blocking, blocking removal request and blocking removal signal, and also input-output component, while any image of aforementioned data area, received by instant copying thereof, is maintained as coherent relatively to data area itself, and input-output component may position previous direct confirmation, that this data area remains coherent to any such image, to cash-memory, and may perform input-output operations on basis of aforementioned previous direct confirmation. Method describes operation of aforementioned device. Software product for computer is realized on machine-readable carrier and contains a program recorded thereon, realizing operations of aforementioned method.
EFFECT: expanded functional capabilities.
3 cl, 3 dwg
FIELD: engineering of means for pausing execution of a stream until certain memory access occurs.
SUBSTANCE: in one variant of realization, processor contains a set of executive devices, capable of executing a set of streams. First stream includes a command, which determines the address being tracked. Logical pausing means pause execution of first stream, and monitor causes renewal of first flow as reaction to access of given address being tracked.
EFFECT: increased processor productiveness.
5 cl, 14 dwg
FIELD: methods for automatic execution of a program, connected to data file, when data file and program being executed are positioned on different computer units.
SUBSTANCE: in methods, program being executed is accessed through graphic image of data file type, realized in the network, which includes client system and a set of server systems. Client system receives the scheme, which determines connection between the set of programs being executed and corresponding set of data file types. Graphic image of data files is displayed, information about selection of graphic image of data file is received from server system, on basis of it program to be executed is selected and executed.
EFFECT: increased productivity of system due to distributed execution of programs.
9 cl, 19 dwg, 3 tbl
FIELD: method and system for providing user interface information to client.
SUBSTANCE: in accordance to the invention, access system contains registration mechanism. Client environment for automatic processing of user interface receives registration information from the client and transmits user interface information after receipt. Server for automatic processing of user interface receives registration information from client environment for automatic processing of user interface and notifies processor of user interface about registration, and also receives user interface information from user interface processor. The server contains filtration device for filtering out information of no interest to client, and notification device for notifying the client about information which is of interest to the client.
EFFECT: ensured capacity for filtration and coordination of excessive and disorienting notifications.
2 cl, 11 dwg
SUBSTANCE: device contains a set of central processor units, which are assigned a common external up address in telecommunication network which allows packet data. IP messages, addressed to a network element, are received, and received IP messages which contain first messages are identified. First value is identified in first message and first message is transmitted to central processor unit on basis of identified first value, if identified first value is not equal to zero.
EFFECT: ensured load balancing for central processor when using several types of traffic.
3 cl, 3 dwg