Receiver serial multi-frequency signals

 

(57) Abstract:

The invention can be used for receiving digital data broadband systems with sequential multi-frequency (PMC) signals. Achievable technical result is to increase the noise immunity. Receiving PMC signals, taking into account their delays on the highway distribution is achieved by the fact that the well-known blocks: the input module, the set of quadrature correlators, the shaper of quadratures, the clock pulse generator of pseudo-random permutations, the sensor reference frequency, the shaper threshold signal, crucial unit, new units, multiplexers, switch modes, shaper adaptive threshold voltage, the delay unit, interface unit, Converter serial code into parallel code, a storage device, the shaper bars, driver commands, modes, block controlled delay element and the block comparison the switch and the multiplier at a fixed constant in each quadrature correlator, in a certain way United. 4 C.p. f-crystals, 3 ill.

The invention relates to radio communications, in particular, can be ispolzuemyi.

Known receivers with coherent multi-frequency (PMC) signals, also known as the discrete frequency-modulated (manipulated) signals (see, for example. Okunev ML B., Yakovlev, L. A. Broadband communication systems with composite signals. -M.: Communication, 1968, S. 13, Fig. 1.6; Aces, I. Statistical theory of complex reception signals. -M.: Owls.radio, 1977, S. 66, Fig. 2.8; Cherdyntsev Century A. the Design of radio systems with complex signals. -Minsk: High school, 1979, S. 18, Fig. 22; Aces, I. and other Interference protection radio systems with complex signals. -M.: Radio and communication, 1985, S. 34, Fig. 2.6. Zhuravlev, C. I. Search and synchronization in wideband systems. -M.: Radio and communication, 1986, S. 6, Fig. 1.3).

Also known receivers, the quadrature channels which the operation detecting replaced by the simplified operation of summing modules quadratures (see, for example, Mitchev Century. N. About the noise immunity of the two ways of receiving pulse signals. Radio engineering and electronics, 1961, n 5, 706-715; Product P-694. Technical description. CL.003.127, kN.1, 1987. Omsk research Institute of instrumentation).

Known receivers closest to the essential features and achieved when it is used the effect is what galimi. -M.: Radio and communication, 1985, S. 19, Fig.1.11. This device, together with the simplified quadrature channels (prototype), contains a set of quadrature correlators, the shaper of quadratures, shaper threshold signal, computing device, a switch, a frequency modulator, oscillator clock pulses (TI), the generator of pseudorandom permutations (ESPER), the first and second inputs which are connected respectively with the first and second generator output T, the sensor reference frequency, an input connected to the second output of the generator T, and the output connected to the signal input of the switch, the control input and the output of which is connected respectively with the output of the generator PSPER and the input of frequency modulator, the input block, the output of which is connected to the inputs of the quadrature correlators, the outputs of which are connected to information inputs of the decision making unit whose output is the output device, each of the quadrature correlator consists of two strings of series-connected multiplier, integrator and block generation module connected to the inputs of an adder whose output is the output of the quadrature correlator, and the first inputs of the multiplier products are combined and input quadratures of quadratures and the third generator output T, and the first auxiliary input of the decision making unit, the second additional input connected to the output of the shaper threshold signal.

Block diagram of the receiver of the prototype is shown in Fig.1, where

1 - input unit,

2-1,...,2-P - quadrature correlators,

2-1-1, 2-1-4 - multiplier products,

2-1-2, 2-1-5 integrators,

2-1-3, 2-1-6 - blocks forming module,

2-1-7 - adder,

3 is a generator of clock pulses (TI),

4 - the generator of pseudorandom permutations (ESPER),

5 - sensor reference frequency,

6 (6-1,...,6-P) - the driver of quadratures,

7 - shaper threshold signal,

8 is a decisive block,

9 - switch

10 (10-1,...,10-P) - frequency modulator,

Receiving and transmitting (as we will see for a clearer understanding of the operation of the receiver) serial multi-frequency (PMC) signals as follows.

At the sending end generator of pseudorandom permutations (identical to the generator PSPER 4 receiver prototype), for a duration T PMC signal is produced M different K-bit (2TO=M) numbers (pseudo-random permutation of M numbers), which are consistent over time, with tact ( = T/M) To the address circuits the ranks sensor 5) is a grid of M reference frequency, obtained, for example, by dividing a single reference frequency. Switch, depending on what code (the current value of the pseudo-random permutation) received at its address inputs permit the passage of the signal to the input information of the modulator from one of the M outputs of the sensor reference frequency. In the information modulator input signal is manipulated received by D (D K) circuits from the sensor information symbols of discrete messages, say the characters 0 or 1, if the information sequence from the sensor information is binary, or symbols 0,1,...,P-1, if the information sequence P-ranks (P=2D, P, M). In the first case, when the information symbol 0 code sequence which determines the order of changing frequency PMC signal, passes the information modulator unchanged, when the information symbol 1 is inverted, i.e., in the information modulator of the information sequence are summed modulo 2 with a code sequence output switch. In the second case (when P-primary information sequence) in the information modulator are summed modulo P sequences, arriving at its inputs. Thus, if a1, a2,...,aM is the ability PMC signal), in the information modulator transactions:

to transmit the symbol 0 - a1 0,..., aM 0,

character 1 - a1 1,..., aM 1, and so on.

where the summation modulo P.

Modulated in the information modulator code sequence which determines the order of switching frequencies in PMC the signal fed to the input of the generator elementary oscillation PMC signal, which is amplified by power and radiated by the antenna.

At the receiving side, the signal passed by the antenna, amplified, subjected to pre-filter the input unit 1, and arrives at the inputs of the quadrature correlators 2-1,...,2-P (P=2D) PMC signals to the other inputs of which the frequency modulator 10 via the driver 6 quadratures (in-phase and quadrature components) are offset by a discrete number of positions sensor signals 5 the reference frequency, a toggle switch 9 by the signal from the generator 4 PSPER, synchronized with the generator PSPER on the transmission side. On the quadrature correlator 2-1 output signal of the frequency modulator 10 is supplied, for example, with a zero offset, the correlator 2-2 - shifted by one position to the correlator 2-3 - 2 position and so on, Thus, kVA is elementarnykh vibrations emitted PMC signal, the first correlator 2-1 is tuned exactly to the frequency set by the oscillator 4, the second correlator is configured 2-2 with a shift of all frequencies in one position, the third correlator 2-3 - 2 position and so on, the Decisive unit 8, the input of which receives signals from the outputs of all quadrature correlators 2-1, ...,2-P, will select the highest signal of the correlator, the configuration of which coincides with a discrete shift of the pseudo-random sequence as a result of information modulation elements PMC signal on the transmission side.

Sync generator 4 PSPER, sensor 5 reference frequency, quadrature correlators 2-1, . . .,2-P, the decision making unit 8 is carried out by the generator 3 clock pulses, identical to the clock on the transmission side.

NOTE. In the original prototype (kN. Varakin HP communication Systems with noise-like signals. -M.: Radio and communication, 1985, S. 19, Fig. 1.11) information modulator on the transmission side is called a frequency modulator (FM), and the generators are pseudo-random permutation generators code sequence (GCM) frequency-shift keyed (FM) of the wideband signal (PSS). In our opinion, the title "information modulate the sure symbol of the original pseudo-random sequence, the control frequency of the switching elements PMC signal.

The generator 4 and its counterpart on the transmission side renamed the generators of pseudorandom permutations because, as noted in the original (kN. Varakin), "just use M frequencies, and none of them is used twice in the same PSS", PMC the signal, in our terminology, this means that for the duration T PMC signal generator 4 (and its counterpart on the transmission side) to produce a set of M different random numbers a1, a2,..., aM, which, as you know, is called a permutation (see, e.g., Bronstein, I. N., semendjajew K. A. Handbook of mathematics for engineers and students of technical COLLEGES. -M. 1957, S. 163 or-M 1980, S. 199).

Modulation PMC signal shift its basic frequency signal at some fixed position associated with the value of the information signal generated by the sensor information on the transmitting side, allows a simple technical implementation information modulator and a frequency modulator 10 at the receiving side, however, has one significant disadvantage - allows you to simulate an information signal, e.g. reradiation PMC signals with a constant shift of its elements to the same value the information symbols also does not exceed 16. We will, for concreteness, assume that the information symbols are numbers 0,1, ...,15. Then, as already mentioned, the transmission of information number, say 2, corresponds to a shift in the information modulator pseudo-random numbers a1,...,aM on two positions: a1 2,...,aM 2, which, in turn, corresponds to a frequency shift elements PMC signal generator output PMC signals on the transmitting side also two positions: 2 f1,..., fM 2. Clearly, if the transmitted information symbol 2 and simultaneously pereklokayutsia elements PMC signal more power-shift, for example, at the 3 position, the decision making unit 8 at the receiving side will provide PMC signal f1 5 ..., fM 5, i.e., a signal corresponding to the information symbol 5.

A similar lack - deterministic nature of functions of the modulation pseudo-random sequence, which determines the law of the switching elements PMC signal, the information sequence is inherent and analogues. So in the system of kN. Zhuravlev, C. I. Search and synchronization in wideband systems. - M.: Radio and communication, 1986, S. 9, Fig. 1.3 modulation method is used, similar to that already described, when a broadband signal (PSS) additionally manipulate symbols binary message is Eden Converter absolute code in the relative code (AK/OK), to the input of which receives the binary signals discrete message d(t)).

The disadvantage of this receiver is also no delay in the formation of PMC signals for quadrature correlators with respect to PMC signals generated on the transmission side that does not take into account the propagation time of the transmitted signal and leads to energy losses, when the length of elements PMC signal comparable to the signal delay on the highway distribution. Another drawback of the prototype is to reduce its noise immunity at the expense of use in the quadrature correlators suboptimal processing summation modules quadrature voltages.

The aim of the invention is to increase the noise immunity through more efficient use of the energy potential PMC signals.

This objective is achieved in that in the receiver PMC signals containing a set of quadrature correlators, the shaper of quadratures, shaper threshold signal, the deciding unit, a generator of clock pulses (TI), the generator of pseudorandom permutations (ESPER), the first and second inputs which are connected respectively with the first the and TI, as well as the input block, output connected to the parallel connected input the quadrature correlators, each consisting of two Chicks series-connected multiplier, integrator, and the processing unit module, and the adder, the first inputs of the multiplier products are combined and input quadrature correlator, the second inputs of multiplier products and integrators are connected respectively to the outputs of the shaper of the quadratures and the first additional entry of the decision making unit, and the output of the adder being the output of the quadrature correlator connected, except the first, to the information input of the decision making unit whose output is the output of a receiving device, introduced multiplexers, the signal inputs are connected to the output of the sensor PTS, switch modes, the elements of which contain two switching circuits, one of willows which is closed, the other open condition, the shaper adaptive threshold voltage, the first input is via closed circuit element of the switch is connected to the output of the first quadrature correlator and the second input and output respectively connected to the second generator output T ivystone with the second and third outputs of the generator T, the interface block, the first and second inputs which are connected respectively with the second output of the generator T and the output of the generator PSPER, Converter serial code into parallel code, consisting of a set of series-parallel registers, the information input and the last output of the first register which is connected respectively with the first output connection unit and the information input of the second register, and the information input and the last output of the second and the remaining registers are connected respectively through the closed and open circuits elements switch between modes a and the input of the following information register, a storage device, consisting of a set of registers, information inputs and outputs which are connected respectively to the outputs of the serial-to-parallel registers Converter serial code into parallel code and the control inputs of multiplexers, clock inputs of the first and second registers connected to the second output of the generator T, and the clock inputs of the third and the remaining registers are connected through the closed circuit elements of the switch of modes respectively with first and second outputs of the delay block, and carecrow connected to a clock input of the next register, the frequency dividers, the inputs and outputs of which are connected respectively to the outputs of multiplexers and input shaper of quadratures, shaper bars, the first and second inputs which are connected respectively with the fourth output of the generator T and the second output interface block, and the output is connected with United clock input serial-to-parallel registers Converter serial code into parallel code, the driver command modes, the first input and the output of which is connected respectively through open circuit element switch modes with the second inputs of the integrators quadrature correlators and the third input of the shaper bars and block controlled delay the input and the output of which is connected respectively to the second input of the shaper command modes and the input of the generator of T, while the fifth and sixth outputs of the generator TI through closed and open circuit element of the mode switch, the outputs of which are combined, connected to the second inputs of the integrators quadrature correlator, the output of the first quadrature correlator via open circuit element of the switch connected to the first input of the decision making unit, the third and fourth inputs formicola and the first additional entry of the decision making unit, the output of which is connected to the input of the controllable delay and an output receiving device, and the output of the shaper command modes connected directly and via the item is NOT with the signal inputs of the switch, each of the quadrature correlator introduced the unit of comparison, the switch and the unit of multiplication by a constant, while the first and second inputs of the block comparison and switch, respectively, are combined and connected to the outputs of the blocks forming module, and the output of the Comparer is connected to the third input of the switch, the outputs of which are connected, one directly, the other through the power of multiplication by a constant, to the inputs of the adder. This shaper adaptive threshold voltage contains two register block comparison and the multiplier, and the information input of the first register, United clock inputs of the first and second registers and the setting input of the second register are respectively the first, second and fourth inputs of the adaptive shaper threshold voltage, the first outputs of the registers are connected to the inputs of the block comparison, the output of which is connected to a second input of the first register and the second input and second output of the second register socotora are, respectively, a third input and output of the shaper adaptive threshold voltage; the delay unit includes a counter, installation and information inputs which are respectively the first and second inputs of the delay unit, and a shift register whose outputs are the outputs of the delay unit and the clock and information inputs of the shift register are connected respectively with the release and installation of the meter inlet; shaper bars contains a counter and three OR element, and the output of the meter through the serially connected first, second and third elements OR connected to its own information block, set counter input and the second input of the first element OR combined and are the second input of the shaper bars, the second inputs of the second and third elements OR are respectively the first and the third inputs of the driver cycles, and the output of the second element OR is the output of the shaper bars; shaper command modes contains a counter, a D-flip-flop with set to zero and the element OR the output of the counter is connected to the first input of D-flip-flop with set to zero, a second input connected to a source of fixed voltage, and through the element OR the second input of which is connected to a source of fixed voltage, connected to its own yavlyaetsya respectively the first, the second inputs and the output of the shaper command modes.

Structural diagram of the proposed receiver is shown in Fig. 2, where

1 - input unit,

2-1,...,2-M - quadrature correlators,

2-1-1, 2-1-4 - multiplier products,

2-1-2, 2-1-5 integrators,

2-1-3, 2-1-6 - blocks forming module,

2-1-7 - adder,

2-1-8 - block comparison,

2-1-9 - switch

2-1-10 - multiplier on a fixed constant,

3 is a generator of clock pulses (TI),

4 - the generator of pseudorandom permutations (ESPER),

5 - sensor reference frequency (PTS),

6 (6-1,...,6-M) - driver of quadratures,

7 - shaper threshold signal,

8 is a decisive block,

9-1,...,9-M - multiplexers,

10 - switch modes,

10-1, 10-2,...,10-2M-1 elements of the switch of modes,

11 - shaper adaptive threshold voltage,

11-1, 11-3 registers,

11-2 - block comparison,

11-4 - multiplier,

12 - unit delay,

12-1 - counter

12-2 - shift register,

13 is a block mates,

14 Converter serial code into parallel code,

14-1,...,14-M - series-parallel registers,

15 is a storage device,

15-1,...,15-M - registers

16-1,...,16-M - d is irovel command modes,

18-1 - element, OR

18-2 - counter

18-3 - D-flip-flop with set to zero,

19 - the item is NOT,

20 - unit controlled delay.

In the proposed receiver oscillator 3 TEE connected to the first and second outputs respectively to the first and second inputs of the generator 4 ESPER, and also to the first input sensor 5 PTS, the output of which is connected to the signal inputs of the multiplexers 9-1, ...,9 M; input unit 1 is connected by the output to the parallel-connected input the quadrature correlators 2-1,...,2-M, each of which consists of two chains of series-connected multiplier 2-1-1, integrator 2-1-2, shaper 2-1-3 module and multiplier 2-1-4, integrator 2-1-5, shaper 2-1-6, connected to the corresponding inputs of the block 2-1-8 compare and switch 2-1-9, the first inputs of the multiplier products 2-1-1 and 2-1-4 United and are input quadrature correlator, the second inputs of multiplier products 2-1-1, 2-1-4 and integrators 2-1-2, 2-1-5 connected respectively to the outputs of the shaper 6 (6-1,...,6-M) quadratures and the first additional entry of the decision making unit 8, the output unit 2-1-8 comparison connected with the third input of the switch 2-1-9, the outputs of which are connected, one directly, the other through the block 2-1-10 multiplying the intercept is and with the exception of the first, to the information input of the decision making unit 8; the output of the quadrature correlator 2-1 through open and closed circuit element 10-2 switch modes respectively connected with the first information input of the decision making unit 8, with the first input of the shaper 11 adaptive threshold voltage, the second input and the output of which is connected respectively to the second output of the generator 3 MINUTE and second auxiliary input of the decision making unit 8, and the third and fourth inputs connected respectively to the output of the shaper 7 threshold signal and the first additional entry of the decision making unit 8; unit 12 delays the first and second inputs connected respectively with the second and third outputs of the generator 3 T; unit 13 pairing the first and second inputs connected respectively to the second output of the generator 3 T and the output of the generator 4 ESPER; Converter 14 serial code into parallel code consists of a set of series-parallel registers 14-1,...,14-M, information input and the last output of the first register 14-1 respectively connected with the first output unit 13 pairing and information input of the second register 14-2, and the information input and the last output of the second register 14-2 and the rest of the El regimes between itself and the input of the following information register; the storage device 15 consists of a set of registers 15-1,...,15-M, information inputs and outputs which are connected respectively to the outputs of the serial-to-parallel registers 14-1,...,14th Converter 14 serial code into parallel code and the control inputs of multiplexers 9-1,...,9-M, connected to outputs through the dividers 16-1,...,16-M frequency to the input of the shaper 6 (6-1, ...,6-M) quadratures, and the clock inputs of the first and second registers 15-1 and 15-2 is connected to the second output of the generator 3 T, and clock inputs of the third and remaining registers 15-3,...,15-M are connected through the closed circuit elements 10-M+1,...,10-2M-2 switch modes respectively with first and second outputs 1, . ..,M-2 unit 12 delays, in addition, through the open circuits of these elements 10-M+1,...,10-2M-2 mode switch clock input of the second register 15-2 and other registers 15-3,...,15-M-1 is connected to a clock input of the next register 15-4,...,15-M; first and second inputs of the former (17 cycles are connected respectively with the fourth output of the generator 3 TEES and a second output unit 13 of the coupling, and the output is connected with United clock input serial-to-parallel registers 14-1 ,... , 14th Converter 14 consecutive s; the input and output unit 20 controlled delay are connected respectively to the second input of the shaper 18 teams modes and the input of the generator 3 T; the fifth and sixth outputs of the generator 3 MINUTE through a closed and open circuit element 10-2 switch modes, the outputs of which are combined, connected to the second inputs of the integrators 2-1-2 2-1-5 and quadrature correlators 2-1,... ,2-M and via open circuit element 10-1 switch modes with the first input of the shaper 18 teams modes; output deciding unit 8, which is the output of a receiving device, connected to the input unit 20 controlled delay and the output of the shaper 18 teams modes connected directly and through the element 19 is NOT with the signal inputs of the switch 10 modes. In addition, in the imaging unit 11 adaptive threshold voltage, contains two register 11-1 and 11-3, unit 11-2 comparison and multiplier 11-4, the first outputs of registers 11-1 and 11-3 are connected to the inputs of the block 11-2 comparison, the output of which is connected to a second input of the first register 11-1 and the second input and second output of the second register 13-3 are connected respectively with the second output of the first register 11-1 and the first input of the multiplier 11-4, a second input and output which are, respectively, the third wogo and second registers 11-1 and 11-3 are respectively the first and second inputs of the former (11 adaptive threshold voltage; in the delay block 12 containing a counter 12-1, installation and information inputs which are respectively the first and second inputs of the block 12, and the register 12-2 shift whose outputs are the outputs of the delay block 12, while the clock and informational inputs register 12-2 shift connected respectively with the release and installation of the meter inlet 12-1; shaper 17 cycles containing counter 17-1 and three element 17-2, 17-3, 17-4, OR the output of the counter 17-1 through the serially connected elements 17-2, 17-3 and 17-4 OR connected to its own, information input, installation the meter inlet 17-1 and the second input element 17-2 OR combined and are the second input of the shaper 17, second input elements 17-3 and 17-4 OR are the first and third inputs of the driver 17, and the output element 17-3 OR is the output of the shaper 17 cycles; shaper 18 teams modes containing counter 18-2, D-trigger 18-3 installing to zero and the element 18-1 OR the output of the counter 18-2 is connected to the first input of D-flip-flop 18-3 installing to zero, a second input connected to a source of fixed voltage, and through the element 18-1 OR the second input of which is connected to a source of fixed voltage, connected to its own installation wheatherstone first the second inputs and the output of the shaper 18 teams modes.

The principle of operation of the proposed receiver is illustrated in the cyclograms Fig.3 and consists in the following.

The receiver operates in two modes: in the "Information" is information on a consistent multi-frequency (PMC) signals that represent segments (sequence) of harmonic oscillations, whose carrier frequencies are changed by the law of the pseudorandom sequence, the same for transmitting and receiving sides, and the structure is defined as the time-frequency matrix, and in the "dot clock" when it comes to the reception of signals consisting of several PMC signals corresponding to multiple information packages of the same symbol, say "0".

Duty (standby) mode is "dot clock", in which the closed and open circuits elements 10-1, 10-2,...,10-2M-1 switch 10 modes are in the position shown in Fig. 2. The switch 10 modes is controlled by the output signal of the shaper 18 teams modes, for example a logical "0" for mode "dot clock" and logical "1" to "Information" (see sequence diagram 4, Fig. 3) supplied - the via element 19 (Fig.2 these circuits are conventionally connected to the element 10-M). Shaper 18 teams modes, in turn, is driven by: when switching to "Sync" signals from the second output of the generator 3 T applied to the first input of the shaper 18, when switching RPU mode Information signal from the output of the decision making unit 8 is supplied to the second input of the shaper 18.

Formation and processing of PMC signals in the Information mode is as follows.

At the sending end generator of pseudorandom permutations, similar to the generator 4 of the claimed RPU, is formed column of M different K-bit 2TO-M) numbers (pseudo-random permutation of M numbers), of which, in accordance with the sensor information, selects one of the K-bit number that determines the carrier frequency of the element PMC signal. Clocking generator of pseudo-random permutations, the formation of the reference frequency is made by the generator of clock pulses, a sensor reference frequency identical to the generator 3 T and the sensor 5 reference frequency of the claimed RPU. In the next step of forming the second element PMC signal generator pseudoscutellaris again chosen K-bit number, determining the carrier frequency of the second element PMC signal and so on up to P (P is the number of elements PMC signal), and for the duration PMC signal (P cycles) select the number of each current column pseudorandom permutation is carried out in the same way, say for a given transmitted information symbols from the column is selected the third number (third line). In other words, to transmit one of M PMC signals, say the j-th PMC signal consisting of P elements on the transmission side is formed MxP matrix of pseudo-random K-bit numbers:

< / BR>
from which selects the j-th line, which determines the sequence of changing the carrier frequencies PMC signal (P values of its elements). The first row of the matrix (1) can correspond to, for example, the information symbol "0", the second line is "1" and so on

At the receiving side in the "Information" generator 4 pseudorandom permutations for P clock cycles (Ziklag. 2) is a matrix of numbers, similar to (1), at each time-step (Ziklag.1) generator 4 generates MK binary numbers - pseudorandom permutation - column of M different K-bit numbers (Ziklag. 3), which through the block 13 pairing is written to the inverter 14 posledovatelno (first in series-parallel register 14-1, then in register 14-2, then through the open circuit element 10-3 switches, which in the "Information" is, in the register 14-3, etc. to register 14th), and then stored in the storage device 15 (registers 15-1,..., 15-M) and on the next cycle at the same time served on the control inputs of multiplexers 9-1,...,9-M, the signal inputs of which receive M frequency from the sensor 5 reference frequency. On the first beat to the control input of multiplexer 9-1 received, for example, the number of a11, the second quantum number a12 and so on, similarly, on the first beat to the control input of the multiplexer 9-M will be the number aM1, on the second time - the number of aM2 and so on, in accordance with which on the first beat of the multiplexer from 9-1 M transmits the reference frequency to the output frequency, say f11, the multiplexer 6-M - frequency fM1, etc. Switched to the reference frequency by M channels are routed to the inputs of corresponding blocks 16-1,.., 16th division, where possible switching phase jumps are eliminated by dividing the reference frequency to the value of the intermediate frequency, and Then converted oscillations with frequencies that are shifted in phase by 90oin the shaper 6-1,.. .,6th of quadratures, serves as a reference to the inputs of multiplier products 2-1-1 and 2-1-4 quadrature correlators 2-1, th time-frequency matrix (1), the quadrature correlator is configured 2-2 at the frequency defined by the second row of the matrix (1), etc.

The signal received at the inputs of the quadrature correlators 2-1,...,2-M after amplification and pre-filtering in the input unit 1, is multiplied by the multiplier products 2-1-1 and 2-1-4 with the reference signals, the results of the multiplication are accumulated in the integrators 2-1-2 and 2-1-5, which blocks 2-1-3 and 2-1-6 modules are formed of accumulated stress, then supplied to the inputs of the block 2-1-8 compare and switch 2-1-9. Depending on the results of the comparison, the switch 2-1-9 controlled by the output voltage of the unit 2-1-8, directs a lower modulus value ranging through the multiplier 2-1-10 at a fixed constant, say 0.5, and to the input of the adder 2-1-7, and a larger value of the quadrature - directly to the second input of the adder 2-1-7. Thus, in blocks 2-1-3, 2-1-6, 2-1-8, 2-1-9, 2-1-10 and 2-1-7 instead of the optimal processing Z = (X2+Y2)1/2is simplified operation , if , if , which shows a statistical experiment, optimal loses not more than 3%. The results of the summation of the outputs of the quadrature correlators 2-1 (adders 2-1-7),... arrive at the inputs of the decision making unit 8, which selects the highest signal and (row of the matrix (1)) on the transmission side.

In our example (passed PMC signal, the frequency of which are determined by the j-th row of the matrix (1)) of the quadrature correlator 2-j, which sequentially in time served from the shaper 6-1,...6-M reference quadrature oscillation frequency corresponding to the string values aj1, aj2,... ,ajP, for P clock cycles (duration PMC signal) accumulate the maximum voltage and the deciding unit 8 will allocate the transmitted information symbol (room j-th row), which goes from the output of the unit 8 for further processing (e.g., decoding, if the losing party was made encoding messages). In the reception mode information symbols a loop element 10-2M-1 mode switch (see Fig.2) is open, and the open circuit is closed, and the output of the quadrature correlator 2-1 is connected to the information input of the decision making unit 8, and at its second additional input from the imaging unit 11 adaptive threshold voltage zero voltage. For forming blocks of 4, 13, 14, 15 for the duration element PMC signal MK binary numbers (pseudo-random permutation of M K-bit numbers) to the first input of the generator 4 serves clock pulses from the first output of the generator 3, the clock generator 4, a block sa pulses from the second output of the generator 3, MK clock pulses (Ziklag. 8) on clock inputs serial-to-parallel registers 14-1,. . . , 14-M produced by the shaper 17 cycles, and reset voltages of the integrators 2-1-2 and 2-1-5 correlators 2-1,.,.,2-M and the output voltage deciding unit 8, with period T=P , equal to the duration PMC signal (Ziklag. 2), produces clock pulses supplied from the sixth output of the generator 3 through the circuit element 10-2 switch modes (Fig. 2 it is open).

In the "dot clock" during transmission and reception, several times (several periods T= P is formed a row of time-frequency matrix (1), say the first, and on each clock cycle (Ziklag. 1), as in the Information mode, the generator of pseudorandom permutations 4 MK produces binary numbers (Ziklag. 3), which through the block 13 pairing fed to the input of the inverter 14 serial code into parallel code (data input serial-to-parallel register 14-1). However, if in the "Information" all series-parallel registers 14-1,.. . , 14-M are connected in series, in the mode of "the synchronization Signal information from the last output register 14-1 filed on a subsequent registers 14-2,..., 14-M in parallel with the formation of the IU "Information" (Ziklag.8), what in the storage device 15 is recorded only two K-bit numbers (say, on the first-stage registers 15-2,..., 15-M will be written the same number of a11, and in register 15-1 - number a21, the second step of respectively the number of a12 and a22 and. so on).

On the next step of these two numbers with the outputs of registers 15-1,...,15-M serves on the control inputs of multiplexers 9-1,...,9-M, the signal inputs of which receive M frequency from the sensor 5 reference frequency, and the clock pulses to the registers 15-1, 15-2 come from the generator 3 directly, and registers 15-3,...,15-M - through unit 12 delays, respectively, with a delay ,...,(M-2) seconds (Ziklag. 10-12); delay element is chosen so that the delay of (M-2) seconds blocked the possible range of delays PMC signal on the highway distribution (e.g., for M=16, =3 MS, the overlap range is equal to 143=42 MS, i.e. provides a route 12600 km). As a result of this clocking registers 15-1,...,15-M reference signals from the sensor 5 is transmitted through multiplexers 9-1, 9-2,... dividers 16-1, 16-2,... and shapers 6-1, 6-2,... correlators 2-1, 2-2,... with zero latency, and the correlators 2-3, 2-4,... - latency , 2 , ... seconds, the correlators 2-2, 2-3,...,2-M receives the reference signals corresponding to the first row by the step reference signals, corresponding to the second row of the matrix (1), is not consistent with the timing. Samples from the output of the quadrature correlator 2-1 through a closed item 10-2M-1 switch modes served on the first input of the shaper 11 adaptive threshold voltage, in which adaptive noise at the output of the correlator 2-1 (and the samples at the output due to correlativeness reference signals with the clock characterize the level of noise in the correlator) is formed by a voltage that serves as a threshold on the second auxiliary input of the decision making unit 8, in order to exclude the possibility of false alarms from noise (remember that standby mode receiver operation mode is "dot clock", when transmitted, and may not be transferred to the synchronization signal, therefore, crucial unit 8 in the "dot clock" should be a threshold, say according to the criterion of Neyman-Pearson, in contrast to the mode Information, it is known that one of the channels (correlators) the signal is present, and the deciding unit 8 can operate without a threshold, say according to the criterion of the ideal observer). Crucial unit 8 selects the maximum signal of the correlator (2-2,...,2-M), the delay of the reference signal which naibolshim delay to the input of the generator 3 to adjust (delay) clock pulses. This output signal of the decision making unit 8 is supplied to the second input of the shaper 18 teams modes, which produces an output signal to the transfer switch 10 modes in the state of "Information", i.e., switches the receiver in the receive mode information PMC signals. The reset voltages of the integrators 2-1-2 and 2-1-5 correlators 2-1,...,2-M, shaper 11 adaptive threshold voltage and the output voltage deciding unit 8 with a period equal to the duration of the synchronization signal (several times greater period T - duration PMC signal), is a clock pulse supplied from the fifth output of the generator 3 via closed circuit element 10-2 switch modes.

The essence of the shaper 11 adaptive threshold voltage is potatoe recording noise from the output of the quadrature correlator 2-1 (adder 2-1-7) in the first register 11-1, comparing this level in the block 11-2 with the contents of the second register 11-3 (which is reset at the end of each cycle of the reception clock together with integrators 2-1-2 and 2-1-5 and the deciding unit 8 clock pulses from the fifth output of the generator 3) and rewriting the noise level on the second output register 11-3, if the voltage in the last less voltage in register 1 clock cycles, say N, is equal to the duration of the clock divided by the duration element PMC signal (e.g., the duration of the clock 20, duration PMC signal 1 and the number of elements PMC signal 16, the number of cycles N = 320) in the register 11-3 selected maximum voltage output of the quadrature correlator 2-1, which, being multiplied in the block 11-4 with a threshold signal output from the imaging unit 7, then served as an adaptive threshold signal to the second auxiliary input of the decision making unit 8. Thus, in the final block 8 in the "dot clock" implemented decision rule, invariant (insensitive) to the intensity of noise in the quadrature correlator:

maxj>< C*maxto< / BR>
2jM 1KN

wherej- readings of the voltages at the outputs of the quadrature correlators 2(2,..., 2-M,

to- readings of the voltages from the output of the quadrature correlator 2-1,

C*- threshold voltage (constant), depends only on the probability PLTfalse alarm, the number of samples N and defined by the expression

< / BR>
the value of the constant C and the method of their finding for N=2(x2)128 and probability of false alarm PLT=0,1, to 0.05, 0.01, 0.001 to see, e.g., in article Pus centuries "Izv. universities Rzanovo decision rule is not optimal estimation, based on the sample variance (more precisely the root of the variance), and the estimate based on sequence statistics (the first maximum value maxto), which efficiency is almost optimal 1KN, but is easier to implement (no need for the operations of summation of samples of the voltage output of the quadrature correlator 1-1 and taking the square root).

The delay block 12 includes a counter 12-1 and register 12-2 shifts. Counter 12-1 is a frequency divider; for example, when the frequency of clock pulses at 500 kHz supplied from the third output of the generator 3 to an informational sign, and the coefficient 1500 meter 12-1 produces output pulses with a period of 3 MS, served on the clock input of the register 12-2 shift. Clock pulses with a period (Ziklag. 1) are received from the second output of the generator 3 installation the meter inlet 12-1 and information input register 12-2 and linger in the past , 2,... seconds - 3, 6,... MS in our example (Ziklag. 10-12).

Shaper 17 cycles contains a counter 17-1 and three element 17-2, 17-3, 17-4, OR. The purpose of the shaper 17 - each-step (time consuming element PMC signal, set the clock pulses from the second output of the generator 3 - ceclor.1) transport the swarm input element 17-3 OR; hereinafter, for brevity, the element and its circuit - in this case, the second input element 17-3 - denote: 17-3:2), in the "Synchronization" and MC clock pulses in the mode of "Information" (Ziklag.3). Shaper 17 cycles is controlled: by the third input (second input element 17-4: 2) signals from the output of the shaper 18 teams modes, for example, as with the explanation of the operation of the switch 10 modes, logical "0" in mode "dot clock" and logical "1" in the mode of "Information" (Ziklag.4); on the second input (set input of the counter 17-1:1 and the first input element 17-2:1) signal BS (block 13 pairing), for example, a logical "0", duration overlapping the duration of the generation of the MC clock pulses (Ziklag. 5). If the installation log counter 17-1:1 - logical "1", the output of the counter 17-1:3 is set to "0" which is applied to the input element 17-2: 2. Until the signal BS in state "1", the output element 17-2:3 (the input element 17-3: 1) is "1" and the clock pulses from the fourth output of the generator 3 does not pass through the element 17-3 or registers 14-1,...,14th (there is "1") or counter 17-1 (through the element 17-4). With the arrival of the signal BS is "0" at the output of the element 17-2:3 is set to "0" (Ziklag. 7) and the clock pulses are output element 17 is inhibiting pulses to the counter 17-1 through the element 17-4 not pass, and will go on registers 14-1,...,14-M (right side Ziklag.7). If the input item 17-4: 2 entered "0" ("Sync", Lev. part Ziklag. 4), the information input counter 17-1:2 are the same clock pulse that registers 14-1,...,14. When the counter 17-1 counts 2K pulses, it will produce a "1" (Ziklag. 6), through which the element 17-2 submission of "1" to the input element 17-3: 1 (Ziklag. 7) will prohibit the passage 'of the clock pulses to the registers and (Ziklag. 8 and 9), i.e. in the "dot clock" shaper 17 cycles will produce only 2K clock pulses.

Shaper 18 teams modes contains a counter 18-2, D-trigger 18-3 installing to zero, to the second input of which (18-3:2) is fixed logical "1", and the element 18-1 OR, to the second input of which (18-1:2) is a fixed logical "0". The purpose of the imaging unit 18 to produce at its output (18-3:4) the control signals for the driver 17 cycles and switch 10 modes: logical "0" to translate receiver mode "dot clock" and logical "1" for translation in the Information mode, D-trigger 18-3 installing to zero produces at its output (18-3:4) logical "0" if the input 18-3:3 output deciding unit 8 receives "0" and produces "1", if ecode D-flip-flop with set to zero 18-3:4 logical "0") is also the supply of clock pulses from the sixth output of the generator 3 through the element 10-1 (Fig. 2 it open) switch modes on the information input counter 18-2: 1. Suppose the receiver goes into "Information" (D trigger 18-3 moved from "0" to "1", ceclor.13), the output 18-2:3 counter reset, on his installation log 18-2:2 "0," and he begins to count the clock pulses received at its data input 18-2:1. He counted out the number of pulses equal to the volume of codogram, the counter will produce an output 18-2: 3 logical "1" (Ziklag.15), which is entered to the input of D-flip-flop 18-3: 1, throws him into the zero state (Ziklag. 16) and passing through the element 18-1 OR the installation of the meter inlet 18-2:2, reset it, preparing for further work.

Thus, using the proposed receiver new units - multiplexers, mode switch, driver adaptive threshold voltage, the delay block, the interface block, Converter serial code into parallel code, storage devices, shaper bars, driver commands, modes, block controlled delay element, and block compare, switch and multiplier at a fixed constant in each quadrature correlator - allows you to make consistent mnogochastotnykh), and also to eliminate the major drawback of the receiver prototype - the impossibility of taking into account the time lag PMC signals on the track distribution, and hence the adjustment of the delay reference signal for quadrature correlators.

The proposed receiver in "dot clock" to estimate the delay PMC signal on the track distribution, based on it to adjust the clock when the mode Information, and to enhance the capacity of the radio link. To increase the energy potential also contributes to replace in each of the quadrature correlator operation of summing modules quadratures close to the optimal operation of the weighted sum of modules of the quadratures (the introduction of the above-mentioned block compare, switch and multiplier at a fixed constant).

Technical implementation of the proposed receiver does not cause any fundamental difficulties. Put the blocks can be performed, for example, for M-16 (K= 4) on the chip 564 series: the switch 10 of the logical elements AND / OR 564 LS, unit 12 delays - on the counter-divider 564 A and the shift register 564 IR, the Converter 14 serial code into parallel code -

1. Receiver serial multi-frequency signals containing a set of quadrature correlators, the shaper of quadratures, shaper threshold signal, the deciding unit, a generator of clock pulses, a generator of pseudo-random permutations, the first and second inputs which are connected respectively with the first and second outputs of the clock generator pulses, the sensor reference frequency, an input connected to the second generator output clock pulses, an input unit, output connected to the parallel connected input the quadrature correlators, each consisting of two chains of series-connected multiplier, integrator and block generation module, and an adder, the first inputs of the multiplier products are combined and input quadrature correlator, the second inputs of multiplier products and integrators are connected respectively to the outputs of the shaper of the quadratures and the first additional entry of the decision making unit, and the output of the adder being the output of the quadrature correlator connected, except the first correlator, to the information input of the decision making unit, the output of which is the output of the receiver, characterized in that the input multiplestage contain two switchable circuit, one of which is closed, the other open condition, the shaper adaptive threshold voltage, the first input is via closed circuit element of the switch is connected to the output of the first quadrature correlator and the second input and output respectively connected to the second generator output clock pulses and the second auxiliary input of the decision making unit, the delay unit, the first and second inputs which are connected respectively with the second and third outputs of the clock generator pulses, the connection unit, the first and second inputs which are connected respectively with the second generator output clock pulses and the output of the generator of pseudorandom permutations, Converter serial code into parallel code, consisting of a set of series-parallel registers, the information input and the last output of the first register which is connected respectively with the first output connection unit and the information input of the second register, and the information input and the last output of the second and the remaining registers are connected respectively through the closed and open circuits elements switch between modes a and information input by the which are connected respectively to the outputs of the serial-to-parallel registers Converter serial code into parallel code and the control inputs of multiplexers, clock inputs of the first and second registers connected to the second output of the clock and clock inputs of the third and the remaining registers are connected through the closed circuit elements of the switch of modes respectively with first and second outputs of the delay block, and through the open circuits of these elements of the switch to the clock input of the second register and the other registers is connected to a clock input of the next register, frequency dividers, the inputs and outputs of which are connected respectively to the outputs of multiplexers and input shaper of quadratures, shaper bars, the first and second inputs which are connected respectively with the fourth output clock pulses and a second output interface block, and the output is connected with United clock input serial-to-parallel registers Converter serial code into parallel code, the driver command modes, the first input and the output of which is connected respectively through open circuit element switch modes with the second inputs of the integrators quadrature correlators and the third input of the shaper bars and block controlled delay, the input and output of which, the ri that the fifth and sixth outputs clock pulses through a closed and open circuit element of the mode switch, the outputs of which are combined, connected to the second inputs of the integrators quadrature correlator, the output of the first quadrature correlator via open circuit element of the switch connected to the first input of the decision making unit, the third and fourth inputs of the shaper adaptive threshold voltage are connected respectively with the output of the shaper threshold signal and the first additional entry of the decision making unit, the output of which is connected to the input of the controllable delay, and the output of the shaper command modes connected directly and via the item is NOT with the signal inputs of the switch, in addition, in each quadrature correlator introduced the unit of comparison, the switch and the unit of multiplication by a constant, while the first and second inputs of the block comparison and switch, respectively, are combined and connected to the outputs of the blocks forming module, and the output of the Comparer is connected to the third input of the switch, the outputs of which are connected, one directly, the other through the power of multiplication by a constant to the inputs of the adder.

2. Receiver the voltage contains two registers, the Comparer and the multiplier, and the information input of the first register, United clock inputs of the first and second registers and the setting input of the second register are respectively the first, second and fourth inputs of the adaptive shaper threshold voltage, the first outputs of the registers are connected to the inputs of the block comparison, the output of which is connected to a second input of the first register and the second input and second output of the second register are connected respectively with the second output of the first register and the first input of the multiplier, a second input and output which are, respectively, a third input and output of the shaper adaptive threshold voltage.

3. Receiver serial multi-frequency signals on p. 1, wherein the delay unit includes a counter, installation and information inputs which are respectively the first and second inputs of the delay unit, and a shift register whose outputs are the outputs of the delay unit and the clock and information inputs of the shift register are connected respectively with the release and installation of the meter inlet.

4. Receiver serial multi-frequency signals under item 1, characterized in that formie first, the second and third elements OR connected to your information entrance, installation of the meter inlet and the second input of the first element OR combined and are the second input of the shaper bars, the second inputs of the second and third elements OR are respectively the first and the third inputs of the driver cycles, and the output of the second element OR is the output of the shaper bars.

5. Receiver serial multi-frequency signals under item 1, characterized in that the driver command modes contains a counter, a D-flip-flop with set to zero and the element OR the output of the counter is connected to the first input of D-flip-flop with set to zero, a second input connected to a source of fixed voltage, and through the element OR the second input of which is connected to a source of fixed voltage, connected to its own installation input, the data input of the counter, the third input and output D flip-flop with set to zero are respectively the first, the second inputs and the output of the shaper command modes.

 

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FIELD: radio communications.

SUBSTANCE: pulse noise is detected upon conversion of signal received into intermediate frequency, noise active time is determined, information signal is disconnected from amplifier incorporated in superheterodyne receiver, noise-affected part of information signal is recovered by eliminating simulator signals during extrapolation, and superheterodyne receiver is checked for serviceability at intermediate frequency.

EFFECT: enhanced precision of superheterodyne receiver serviceability check.

1 cl, 1 dwg

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