Electrically erasable and programmable non-volatile storage cell

 

(57) Abstract:

Usage: microelectronics. The essence of the invention: electrically erasable and programmable non-volatile storage cell, which is formed by only one formed by the transition of the source-channel-drain MOS transistor in which the semiconductor substrate (1) of the first conductivity type made of the drain region (2) and region of origin (3) of the second conductivity type to the polarity opposite to the first conductivity type, located on the floating potential of the gate electrode (4) which is electrically isolated from the field drain (2) the tunnel oxide and between the drain region and the source (2, 3) channel region (9) a gate oxide (5, 10) and rubbed in a direction crossing the source-channel-drain at least over part of the channel region (9) and part of the area of flow (2), and with a control electrode (7) which is electrically insulated by the oxide of communication (8) from the gate electrode (4). For programming the cumulative cell to the control electrode (7) apply the high negative voltage to the drain electrode (D) - supply voltage and the source electrode (5) is zero volts. To erase the cumulative cell to the control electronic is electrod drain (D) leave unconnected. The technical result of the invention is to reduce the absolute value of the high voltage, which leads to cost reduction for manufacturing the parts of the schema. 6 C.p. f-crystals, 4 Il.

Microcontrollers need when applying for common management tasks, in particular in the cards with chip, non-volatile storage storage of programs and data storage devices. First of all when used in a portable data carrier with battery-powered, as in the case of mobile data transmission and data processing, or when the wireless supply of energy, as in the case of contactless cards with microchips, in particular, to data storage devices are acceptable ways of programming and erasing with low power consumption. In the same way and voltage must be less than the 3rd Century as controllers and microchip cards are subject to strong price pressure, for wide application important is negligible complexity of the manufacturing process of the nonvolatile storage devices.

Widely used today in the cards with chip FLOTOX-EEPROM-cells (electronically-erasable programmable constant cumulative cell (EEPROM) for MOS transistors with floating roelektronische Speicher", the Springer, Vienna, 1992, in particular, page 122, feature low power consumption, as they are programmed and erased by the tunneling currents Fowler-Nordheim. Due to this, the programming voltage can just get the chip from low supply voltages, which may be less than the 3rd Century Reprogramming in the event of such drives is possible Politova, so FLOTOX-EEPROM-cells are particularly suitable for data storage devices that can be reprogrammed during operation. These FLOTOX-EEPROM cell consists of a transistor of sample and the cumulative effect transistor and therefore require a large area of the cell, so that a single chip can be implemented only small drives. In addition, due to the high programming voltage 15 - 20 In the implementation of high-voltage transistors, to enable these programming voltage is difficult.

EEPROM with the "fast erase" (Flash) implemented in contrast to EEPROM (EEPROM) with only one transistor on cumulative cell so that there are possible much more complex drives than with the FLOTOX-EEPROM-cells. They, of course, is programmed by hot nositelyah minimum supply voltage up to about 5 C. They are therefore not applicable as data storage devices, which must be reprogrammed during operation of the low-voltage power supply or via contactless energy supply. Normal today Split-Gate Flash EEPROM cell ("Fast erase" EEPROM split-gate) are described and presented in the book "Mikroelektronische Speicher" on page 126.

Also US-5,294,819 shows-transistor EEPROM-cell, which is formed by only one formed by the transition of the source-channel-drain MOS transistor in which the semiconductor substrate of the first conductivity type made of the area of the drain and source of the second type conductivity opposite to the first conductivity type polarity. The cell contains located on the floating potential of the gate electrode, which is electrically isolated from the area of flow through the tunneling oxide and between the drain region and the source channel region by the gate oxide and extends in the direction of the source-channel-drain, at least over part of the channel region and part of the area of flow, and a control electrode that is electrically isolated from the gate electrode due to the oxide of communication.

As the erasing and programming of producing ladywood or to the control gate, or the output of the drain of the transistor to make the electrons on the control gate, or to take them with him. Through the application of a high positive voltage it should have a large absolute value of the order of 18, due to what must be the high cost of isolation on a semiconductor chip.

Patent Abstracts of Japan, vol 15, No. 241 and JP-A-3074881 also show cumulative non-volatile cell with the above described construction. There to the control gate is applied with a negative voltage and a small voltage to the drain electrode, to remove electrons from the savings shutter. However, it is not disclosed how the electrons fall on a rollup shutter.

The present invention therefore is to specify a method for operating an electrically erasable and programmable non-volatile cumulative cell, which avoids the disadvantages of the prior art.

This problem is solved by a method with the characteristics of paragraph 1 of the claims. A preferred form of further development are specified in the dependent claims.

Underlying the invention cumulative cell consists of only one TRANS is to it is programmed and erased in the same way, as such FLOTOX-EEPROM cell by tunneling currents Fowler-Nordheim.

At the relevant invention applying positive and negative voltages for programming and erasing, the absolute value of the high voltage can be kept relatively small, so nevisokosnye part of the scheme must also be less electrically durable and thus can be manufactured with lower technology costs. Besides, it is necessary to create high-voltage built-in crystal charging pumps can be smaller.

If the first conductivity type is p-type conductivity, that is, in the case of forming the cell MOSFET it comes to n-channel transistor, the cell is programmed typically due to the fact that its control gate is applied a voltage of -12 V, and the drain +5 V, while the source is connected to the housing. Due to this, in the area of tunnel oxide, i.e. in the area in which are located on the floating potential of the gate electrode, the so-called floating gate overlaps the drain region, the charge carriers tunneling through the tunnel oxide, so that the floating gate electrode is charged positively. Due to this the m a programmed cell to the control electrode is applied typical voltage of 12 V, and to the electrode of the source do typical voltage -6 V, while the drain electrode remains open. Due to this, the charge carriers tunneling between the floating gate and the area of the source and channel region so that the floating gate is again discharged and the threshold voltage of the transistor is shifted to higher values. In case of a programmed cell threshold voltage have a value of order 1, and in the case reprogrammirovaniyu cells of about 5 C. To read and therefore to the control gate applied voltage of about 3 V, while the drain applied voltage of about 1 V, and the source voltage 0 C. Only in the case of a programmed cell, then current will flow, which can be detected, for example, as a logical "1".

At the relevant invention the simultaneous application of positive and negative voltages for programming and erasing corresponding to the invention of the cumulative cell, it is possible to refuse additional, requiring a lot of space transistor selection and yet to have the opportunity of addressing each of the cumulative cell individually. Under normal location cumulative the s sinks with a bit tyres, under the application of negative voltage to the bus of the words all of the cumulative cell, the conclusions of the shutter which is connected to this bus words, inevitably connected with this negative voltage. However, it is programmed only one storage cell, the output of the drain of which is connected to a positive voltage. The condition that both voltages simultaneously applied only to a single storage cell, can be thereby performed by selecting only one bus words and only one bit of the bus.

In the case corresponding to the invention accumulating the output cell flow maximum applied voltage, so that bit on the bus, which is connected to the output of the flow and thus the assessment schemes applied maximum voltage, and thus should not be taken any special precautions to protect these assessment schemes.

Corresponding to the invention cumulative cell together with standard CMOS logic circuits can be preferably implemented on a single semiconductor substrate, i.e. on a single crystal chip. In addition, it is possible to simultaneously implement the same self is lnyh and negative voltages. As the accumulation of cells and high-voltage circuits for this purpose have deep tubs with the polarity of the conductivity type, which is the opposite polarity of conductivity type semiconductor substrate.

In the first form of implementation of the relevant invention cumulative cell, the floating gate electrode extends in the direction of the source-channel-drain over the entire channel region and another part of the field runoff. This area of overlap of the floating gate-drain defines here the tunneling region during programming.

In a particularly preferred form of execution of an insulating oxide, at least part of the overlapping region is thinner than over the channel region. Due to this thinner region is then determined by the tunneling region. To avoid field induced gate leakage current drain during programming, however, is especially preferred, if the oxide in the region of the p-n junction of the drain to the channel region is thicker than the tunnel oxide.

In cumulative cell in which the floating gate electrode overlaps the entire channel region, when too long programming the threshold voltage of the cell becomes negative is about to discourage through a preferred form of execution of the so-called cell with a split gate. A floating gate extends only over part of the channel region, while the control electrode extends over the entire channel region and in areas where there is no longer a floating gate, performs capacitive communication with the channel for its management. Such a cell with a split gate through the educated from the control electrode and the gate oxide serial transistor is limited to the lower threshold voltage of the cell, even if the threshold voltage of the transistor portion of the floating gate and the gate oxide becomes negative.

The invention is illustrated below by the example of execution with the help of figures, which show:

Fig. 1 a schematic representation of a cross section corresponding to the invention cumulative cell,

Fig. 2 a schematic representation of a cross-section through the form of further development of the invention cumulative cell,

Fig. 3 in a schematic diagram the location of such cumulative cells in the matrix of the cumulative cell and

Fig. 4 in schematic form the principal realization of the cumulative field, standard CMOS logic and high-voltage CMOS circuits in polopoly, for example, should be p-type. In it the drain region 2 and source 3 are of type conductivity to the polarity opposite to the conductivity type of the semiconductor substrate 1 in the present example n-type. Accordingly, in the case of the transistor of this cumulative cell we are talking about the n-channel transistor. The drain region 2 is provided by the output of the drain D and the source output source S. Above the drain region 2 and region source 3 and located between the regions of the channel region 9 is made of an oxide layer as an electric insulating layer. On this oxide layer 5, 6 is made of the gate electrode 4, which is electrically floating potential. It is usually referred to as a floating gate. It extends the relevant invention in the direction of the source-channel-drain MOSFET above the channel region and at least part of the region of flow 2. The area of the oxide layer between the floating gate 4 and the channel region is denoted as the oxide of the shutter 5, and the area of the oxide layer between the floating gate 4 and drain region 2 is designated as the tunneling oxide 6. In shown in Fig. 1 form of the development of the invention, the tunnel oxide 6 has a smaller thickness than the gate oxide 5. Otok 2 to the channel region 9 has the same thickness, as the oxide of the shutter 5, which eliminates or at least decreases the induced field of the gate leakage current drain. For applications in which the programmer can tolerate higher this leakage current drain, the device of Fig. 1 can be simplified in such a way that the thickness of the tunnel oxide 6 and the gate oxide 5 choose the same. For this simplified cumulative cells in the method of manufacturing a drop of some technological operations. Over the gate electrode or, respectively, a floating gate 4 is electrically insulated from the floating gate 4 oxide communications control electrode 7. It is connected to the output of gate G.

Fig. 2 shows the further development of the cumulative cell according to Fig. 1, and identical parts have the same reference position. Presents the cell with a split gate. While the floating gate electrode 4 extends only over part of the channel region 9. Due to this control electrode 7 over a partial region 10 of the gate oxide can implement capacitive communication with a channel region 9 and to manage it due to this. Due to this measure compensated by the action of the negative threshold voltage of a CR is the cumulative cells in the matrix of the cumulative cell. The cumulative matrix of cells arranged into bus words ...WLn, WLm... and bit bus ... BLkBLl... Cumulative cell are connected respectively to its output gate G with one of the tires of words ...WLn, WLm... and his conclusion drain D with one bit of tyres ...BLkBLl.... Conclusions the source S of all cumulative cell connected to the bus source SL. Of course that may also be many tire source, which are then connected respectively with only one group of terminals of the source S of the cumulative cell.

In the formed n-MOS transistor storage cell for programming to the control electrode, that is, to the output of the gate G of the cumulative cell, must be applied to the high negative programming voltage. According Fig. 3 this means that the programming voltage must be applied to the bus words WLn. This means, however, that the programming voltage is simultaneously applied to all the other memory cells, the findings of the shutter which is connected to this bus words.

Thus, corresponding to the invention of the storage cell, however, actually happened programming, simultaneously with atragene to the conclusion of the drain D. Once again, it follows from Fig. 3, this positive voltage must be applied to bit bus BLk, which is a positive voltage is again applied to all the terminals of the drain D connected to this the bit-line BLkcumulative cell. Programming, however, will take place only when simultaneously on the output of the gate is applied a negative programming voltage and the output flow positive voltage. If you selected only one bus words and only one bit, this condition is fulfilled only for a single cumulative cell. Thus, if executed with the relevant invention cumulative memory cells, each storage cell can be addressed separately. Of course is possible by addressing the many tyres words and/or multiple bit buses simultaneously programming a lot of the cumulative cell.

To erase to the conclusion shutter cumulative cell must be applied a high positive voltage, and to output a source of negative voltage. If all the terminals of the source is connected to the bus of the source, when you select only one bus words to which is applied a high Polo is the cumulative number of cells, which are connected with the bus words. Due to this measure the erase process is considerably accelerated.

When implementing the above-described electrically erasable and programmable non-volatile memory with CMOS logic, in particular, through the use of high positive and negative voltages must be taken special precautions. They are represented in a schematic way in Fig. 4. On the basis of the p-conductive semiconductor substrate, the n - and p-channel MOS field-effect transistors for logic is fabricated in a p-substrate and n-tub. Due to this, the CMOS logic is compatible with standard CMOS circuits. For high-voltage CMOS transistors required a thicker gate oxide, in addition, n-channel MOSFET to switch a negative voltage feature in isolation from the substrate in the p-tub inside a deep n-tub. High-voltage p-channel MOS transistors are n-tub. When only low speed requirements switching logic high and logic transistors can also be realized with the same thickness of the oxide layer. Cumulative cell made in isolation from the substrate in the p-tub inside Glubokaya impact on the logical part.

By applying positive and negative voltages, the absolute value of available programming voltage is limited to 12, so that the high-voltage should be calculated only on this value. Through the use of an isolated p-tubs inside a deep n-tub can handle negative voltages without the need to resort to high-voltage part to the inverter or p-MOS istokov repeaters. Field cumulative cells isolated p-bath has the advantage that the total bus source can contribute to a negative voltage without due to this effect on CMOS-logic part. Positive and negative programming voltage due to the low consumption power programming Fowler-Nordheim can easily be obtained on the crystal chip due to the charging pumps.

An individual part in Fig. 4 are separated from each other by regions of field oxide. Although the gate electrodes G of the CMOS logic and high-voltage CMOS circuits and is shown in Fig. 4 with the same distance relative to the channel region, but in practice, if you want fast CMOS logic, the thickness of the oxide under the gate electrodes G USI gate SG is shown a schematic way.

1. A method of operating an electrically erasable and programmable non-volatile cumulative cell, which is formed by only one formed by the transition of the source-channel-drain MOS transistor in which the semiconductor substrate (1) of the first conductivity type made of the drain region (2) and region of origin (3) of the second conductivity type to the polarity opposite to the first conductivity type, located on the floating potential of the gate electrode (4) which is electrically isolated from the field drain (2) tunnel oxide (5) and located between the drain region and the region of origin (2,3) channel region (9) gate oxide (5,10) and extends in the direction of the source-channel-drain at least over part of the channel region (9) and part of the area of flow (2), and with a control electrode (7) which is electrically insulated by the oxide of communication (8) from the gate electrode (4), characterized in that the programming of the cumulative cell to the control electrode (7) apply the high negative voltage to the drain electrode (D) the supply voltage to the electrode and source ($) zero volts and to erase the cumulative cell to the control electrode (7) apply a high positive voltage to the electrode, trichosis the fact that the gate electrode (4) extends over the entire channel region (9).

3. The method according to p. 1, characterized in that the storage cell of the oxide layer above the channel region (9) is divided into the first region of gate oxide (5), which connects the capacitor, the gate electrode (4) with a channel region (9), and the second region of the gate oxide (10), and the second field oxide shutter (10) provides a capacitive connection of the partial region of the control electrode (7) with a channel region (9).

4. The method according to any of the preceding paragraphs, characterized in that the storage cell tunnel oxide (6) is thinner than the gate oxide (5).

5. The method according to p. 4, characterized in that the storage cell, the gate oxide (5) extends into the region of the transition from the field of flow (2) to the channel region and partially overlaps the drain region (2).

6. The method according to any of the preceding paragraphs, characterized in that the MOS transistor is made in a bath of the first conductivity type, which is located in a deep bath of the second conductivity type.

7. The method according to p. 6, characterized in that the MOS transistor together with standard logic CMOS circuit and/or high-voltage circuit located the

 

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