The wireless link with the amplitude-photomanipulating noise-like signals

 

(57) Abstract:

The invention relates to the field of radio and can be used in communication systems operating in an uncertain noise. The technical solution is to develop a radio that can improve the reception quality in the transmission of heterogeneous information in terms of the impact of an uncertain interference limited average power, and is achieved by the fact that the wireless link with AFM PSS introduced additional control blocks and blocks alternations. Introduced additional elements allow in line with AFM PSS implement an algorithm alternation and uneven energy distribution of signals by changing their duration. In the case of transmission, for example, an independent digital samples of analog data the implemented algorithm provides a coding gain of up to 13 dB in comparison with the algorithm of uniform distribution without alternation and up to 5.5 dB in comparison with the algorithm of uniform distribution with alternation. 6 Il.

The invention relates to the field of radio and can be used in communication systems operating in an uncertain noise.

Known radio, ipsps) with constant amplitude and extended frequency range (see AC USSR N 489254, CL H 04 27/18 from 1973; AC USSR N 509194, CL H 04 9/00 from 1974; AC USSR N 563730, CL H 04 7/00 from 1976; U.S. patent N 3665472, CL H 04 1/38 from 1972 ). However, due to the impact of the worst interference of unknown structure and limited average power (for example, when the ripple of the power level of interference) immunity of links with FM PSS significantly reduced.

Also known radio link using amplitude-photomanipulation signals (afss) with varying amplitude and phase (see application UK N 1356179, CL H 04 27/00 from 1974; the application of Germany N 2153376, CL H 04 27/18 from 1976 ; the application of Japan N 55-24826, CL H 04 27/00 from 1976; the application of Germany N 3322954, CL H 04 27/00 from 1985; the application of Germany N 3243373, CL H 04 27/00 from 1985). However, used in these links, the rules of the switching phases and amplitudes are not designed to provide noise immunity due to the impact of the worst interference of unknown structure and limited average power.

Most similar in its essence to the proposed device is known radio line with amplitude-photomanipulating noise-like signals (AFM PSS), described in the as of the USSR N 1635275 A1, class H 04 L 27/18 from 1991 /1/.

The closest analogue (prototype) contains on the transmission side East who built the device, the synchronization unit, the pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter, and the output of an information source connected to the first input of the phase modulator, the output of which is connected to the first input of the modulator, the output of the generator carrier frequency is connected to the second input of the modulator, the output of which is connected to the information input of the amplifier, the output of which is connected to the input of the power amplifier, the output of which is connected to the input of the antenna device, the first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register, and its second output to the clock input of storage register, the output of a pseudorandom sequence generator connected to the information input of the shift register, (N+1) informational outputs of the shift register, where N is 2, is connected to the corresponding (N+1) information input storage register, N informational outputs of the storage register connected to the corresponding N to the information inputs of the decoder, and the additional (N+1) output of the storage register connected to the second input of the phase modulator, the N outputs of the decoder are connected to the line is at the receiving side, the prototype contains the antenna device, mixer, intermediate frequency amplifier, a multiplier, amplifier, integrator, the deciding unit, a local oscillator, the synchronization unit, the pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter and receiver information, and the output of an antenna device connected to the first input of the mixer, the mixer output is connected to the input of the intermediate frequency amplifier, the output of which is connected to the information input of the multiplier, the output of which is connected to the information input of the amplifier, the output of which is connected to the input of the integrator, the output of which is connected to the input of a casting device and to the input of the synchronization unit, the first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register, the second output of the synchronization unit is connected to the clock input of the storage register, the third output of the synchronization unit is connected to the input of the local oscillator, the output of which is connected to the second input of the mixer, the output of a pseudorandom sequence generator connected to the information input of the shift register, (N+1) informational outputs of which are connected to the corresponding (N+1) the information is passed to the inputs of the decoder, and the additional (N+1) output of the storage register connected to the control input of the multiplier, N outputs of the decoder are connected to the respective N inputs to analog Converter whose output is connected to the control input of the amplifier.

Due to the additional pseudo-random variation of the amplitude of the sub signal, manipulated by the phase of the pseudorandom signal extend range, the wireless link is the prototype compared to the radio - analogs using FM PSS with a fixed amplitude of subcells, provides increased resistance to intermittent interference limited average power of affecting the individual subcells PSS. Theoretically, the energy gain in this radio link with the specified quality requirements can achieve more than 3 dB /2/.

The specified prize is provided under the condition of homogeneous transmission of information, the reception quality of which can be estimated by the average probability of error of any of the transmitted bits.

However, the device is a prototype has several disadvantages. First, the device is a prototype does not provide high quality reception when transferring heterogeneous information services individual bits of the information signal, which more strongly than other places, affect the final quality of communication, as measured by the accuracy of reconstruction of blocks of information, including many places. As such blocks of information bits can be data packets with separately encoded headers cycles group of signals with a temporary seal operational and service channels, digitized samples of analog data, etc. secondly, implemented in the device algorithm uniform distribution of the energy resource is not rational in terms of homogeneous noise with the same noise immunity of the individual digits and the heterogeneity of the structure of the information blocks.

The aim of the invention is to develop a radio link with AFM PSS that can improve the reception quality in the transmission of heterogeneous information and the efficiency of energy resource under the influence of uncertain interference with reduced average power.

This goal is achieved by the fact that in the known radio with AFM PSS containing on the transmission side information source, a phase modulator, modulator, oscillator carrier frequency, amplifier, power amplifier, antenna device is a decoder, d / a Converter. Moreover, the output of the phase modulator connected to the first input of the modulator. The output of the generator carrier frequency is connected to the second input of the modulator, the output of which is connected to the information input of the amplifier, the output of which is connected to the input of the power amplifier, the output of which is connected to the input of the antenna device. The first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register, and its second output to the clock input of the storage register. The output of a pseudorandom sequence generator connected to the information input of the shift register, (N+1) informational outputs of the shift register, where N is 2, is connected to the corresponding (N+1) to the information inputs of register storage. N informational outputs of the storage register connected to the corresponding N to the information inputs of the decoder. Additional (N+1) output of the storage register connected to the second input of the phase modulator. N outputs of the decoder are connected to the respective N inputs to analog Converter whose output is connected to the control input of the amplifier. At the receiving side radio line-prototype contains: antenna device,the synchronization unit, the pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter and the receiver of information. Moreover, the output of an antenna device connected to the first input of the mixer. The mixer output is connected to the input of the intermediate frequency amplifier, the output of which is connected to the information input of the multiplier, the output of which is connected to the information input of the amplifier. The amplifier output is connected to the input of the integrator, the output of which is connected to the input of the decision making unit and to the input of the synchronization unit. The first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register. The second output of the synchronization unit is connected to the clock input of the storage register. The third output of the synchronization unit is connected to the input of the local oscillator, the output of which is connected to the second input of the mixer. The output of a pseudorandom sequence generator connected to the information input of the shift register, (N+1) informational outputs of which are connected to the corresponding (N+1) information input storage register, N informational outputs of which are connected to the corresponding N to the information inputs of the decoder. D. the and connected to the respective N inputs digital to analogue Converter, the output of which is connected to the control input of the amplifier.

Added on the transmission side control unit, the power alternation, and at the receiving side control unit and the block interleave. Thus the output of the information source connected to the information input unit of alternations. The output of block alternation connected to the first input of the phase modulator. Additional (N+1) output of the storage register connected to the control input of the control unit. The second output of the synchronization unit is connected to the clock input of the control unit. The first and second clock outputs a control unit connected to the respective clock inputs of the data source and block interleave, and the third clock output control unit connected to the third clock input block interleave. To control output of the control unit, where K 2, connected to the corresponding K control inputs of the block interleave. The output of block alternation connected to the input of the phase modulator. At the receiving side to the second output of the synchronization unit is connected to the clock input of the control unit. Additional (N+1) output of the storage register connected to the control input of the control unit. First, in the alternation, and the third clock output control unit connected to the third clock input block interleave and the clock input of the decision making unit. K control output control unit connected to the corresponding K control inputs of the block interleave. The output of the decision making unit connected to the information input unit of alternation, and the output of block alternation connected to the input of the receiver of the information.

Thanks to a new set of features will increase the quality of reception of the transmitted information by equalizing the degree of influence of the distortion of the individual digits on the final quality of reception of the k-bit information block in General, the transmission of individual bits i=1,..., k equal powerc1,.. -Pckbut with different duration of T1...Tk. When this limit, the total energy of the radio resource is expressed in the constant total energy of the emitted signals of duration T transmit k-bit information block.

For a given duration T of the transmission of an information block of k binary digits uneven distribution of energy resource ec=xEcwhere x={ xi}kxi0, i=1,...,k, x1+. the snasti Pciand duration of Tisatisfying the condition PciTi=xiEc. In the inventive device serves to implement the uneven distribution of duration Ti=x1T for a fixed power Pc. In Fig.2 shows an example of such a non-uniform energy distribution of the signals Ec=PcT between k=4 information bits. The advantage of this implementation is that it saves both the amplitude and spectral characteristics of the emitted signals, and it is easier to implement path control, because in this case no interference in the work of radiotracked.

The analysis of the level of technology has allowed to establish that the analogues, characterized by a set of characteristics is identical for all features of the proposed technical solutions are missing, which indicates compliance of the claimed device, the condition of patentability "novelty". Search results known solutions in this and related areas of technology in order to identify characteristics that match the distinctive features of the prototype of the features of the declared object, showed that they do not follow explicitly from the prior art. The prior art also does not viable to achieve the technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The inventive device is illustrated by drawings, showing:

Fig. 1 - structural diagram of the radio link with the amplitude-photomanipulating pseudonoise signals;

Fig. 2 is an example of the uneven energy distribution of the signals Ec=PcT between k=4 information bits;

Fig. 3 is an example implementation of an information source;

Fig. 4 is an example implementation of a control unit;

Fig. 5 is an example implementation of block interleave;

Fig. 6 - graphs of the dispersion error on the relative interference power at different energy distribution of signals and interference between the bits of the digitized analog samples.

Declare the wireless link with the amplitude-photomanipulating noise-like signals, shown in Fig. 1, contains a transmitting-side information source 1, the control unit 2, block interleave 3, the phase modulator 4, a modulator 5, the amplifier 6, the amplifier 7, the antenna device 8, the synchronization unit 9, the generator carrier frequency 10, the pseudo-random sequence generator 11, the shift register 12, the storage register 13, desimama input block interleave 3. The output of block interleave 3 connected to the first input of the phase modulator 4. The output of the phase modulator 4 is connected to the first input of the modulator 5. Additional (n+1) output of the storage register 13 is connected to the control input of the control unit 2. The second output of the synchronization unit 9 is connected to the clock input of the control unit 2. The first and second clock outputs of the control unit 2 is connected to the respective clock inputs of the information source 1 and block interleave 3, and the third clock output control unit 2 is connected to the third control input of the block interleave 3. To control output of the control unit 2, where k 2, connected to the corresponding k control inputs of the block interleave 3.

The output of the generator carrier frequency 10 is connected to the second input of the modulator 5, the output of which is connected to the information input of the amplifier 6, the output of which is connected to the input of the amplifier 7, the output of which is connected to the input of the antenna device 8. The first output of the synchronization unit 9 is connected to the input of the pseudorandom sequence generator 11 and to the clock input of shift register 12, and its second output to the clock input of storage register 13. The output of the generator pseudolocal the Istra shift 12, where N is 2, is connected to the corresponding (N+1) information input storage register 13. N informational outputs of the storage register 13 is connected to the corresponding information to the inputs of the decoder 14. Additional (N+1) output of the storage register 13 is connected to the second input of the phase modulator 4. N outputs of decoder 14 is connected to the respective N inputs d / a Converter 15, the output of which is connected to the control input of the amplifier 6.

At the receiving side of the wireless link includes: the antenna device 16, the mixer 17, the intermediate frequency amplifier 18, the multiplier 19, the amplifier 20, the integrator 21, a crucial block 22, block interleave 23, the control unit 24, a receiver 25, a local oscillator 26, a synchronization unit 27, the pseudo-random sequence generator 28, the shift register 29, the storage register 30, the decoder 31, a d / a Converter 32. The output of an antenna device 16 connected to the first input of the mixer 17. The output of mixer 17 is connected to the input of the intermediate frequency amplifier 18, the output of which is connected to the information input of the multiplier 19. The output of multiplier 19 is connected to the information input of the amplifier 20. The amplifier output is connected to the input of the integrator 21, the output of which is otklyuchen to the input of the pseudorandom sequence generator 28 and to the clock input of shift register 29. The second output of the synchronization unit 27 is connected to the clock input of the storage register 30 and to the clock input of the control unit 24. The third output of the synchronization unit 27 is connected to the input of the local oscillator 26, the output of which is connected to the second input of the mixer 17. Additional (N+1) output of the storage register 30 is connected to the control input of the control unit 24. The first, the second clock output control unit 24 connected to the respective clock inputs of the block interleave 23, and the third output control unit 24 is connected to the third clock input block interleave 24 and the clock input of the decision making unit 22. To control output of the control unit 24 is connected to respective control inputs of the block interleave 23. The output of the decision making unit 22 is connected to the information input unit interleave 23, and the output of block alternation connected to the input of the receiver 25. The output of a pseudorandom sequence generator 28 connected to the information input of the shift register 29, (N+1) informational outputs of which are connected to the corresponding (N+1) information input storage register 30, N informational outputs of which are connected to the corresponding N information inputs desif the s decoder 31 is connected to the respective N inputs digital to analogue Converter 32, the output of which is connected to the control input of the amplifier 20.

Separate blocks of the inventive device has the following functions.

Information source 1 itself generates or accepts external source information and converts it into a sequence of binary pulses are grouped into code blocks corresponding to distinct parts of the transmitted information. In particular, when transmitting the digitized analog information, each block may represent a binary k-bit digital code of the reference quantumg on 2klevels.

An information receiver 25 converts the input sequence of binary pulses to perceived (or for subsequent transmission to an external device) type of information. In particular, when receiving a digitized analog information code blocks can be transformed into a sequence of voltage levels, optionally by filtering is formed of a continuous analog signal.

As a source of information 1 and the information receiver 28 may be any terminal or intermediate (encoder, channel-forming, switching, and so bound, for example, through a digital interface S1-FL-BI (GOST 24174-80, GOST 26532-85)/14,15/. As an example in Fig. 3 shows an embodiment of the source of the digitized analog information.

Source of information consists of a source of an analog signal 1.1, analog-to-digital Converter 1.2 and Converter parallel to serial 1.3. Moreover, the source output analog signal 1.1 connected to the input of analog-to-digital Converter 1.2, a k outputs of analog-to-digital Converter 1.2 is connected to the k input of the inverter of the parallel code in a sequential 1.3. The inverter output of the parallel code in a sequential 1.3 is the output of the source of information 1.

Inputs kT0and T0information source 1 are used for synchronization of the read bits to the output device.

As the source of the analog signal can be used a microphone or pickup /18/ / 671-687.

An embodiment of the analog-to-digital Converter described /5/ page 215 Fig. 2.22.

An embodiment of the Converter of the parallel code in a sequential described in /3/ page 208 of Fig. 5.4 (d).

In the role of receiver of information can be the device of (in)) and digital to analog conversions, similar to the above described blocks 15(32).

The control unit 2(24) is used to control processes: a) uniform bitwise read the transmitted code blocks from the information source 1 in block interleave 3 (uneven bitwise read the received code blocks from the output of the decision making unit 22 to the input of the block interleave 23), b) change the order of sequence of binary bits in a code block (restore the original sequence of bits) and uneven bitwise read code blocks from a block interleave 3 phase modulator 4 (uniform bitwise read the transmitted code blocks output from the block interleave 23 to the input of the receiver 25) in accordance with the sequence of pulses generated in the sync block 9, 27, and pseudo-random sequences generated by a pseudorandom sequence generators 11, 28.

An embodiment of the control unit 2(24) shown in Fig.4. The control unit consists of two counters 2.1 (B-pulses) and 2.2 (k-pulses), the decoder's clock cycles 2.3, RS-flip-flop 2.4, item AND 2.5, 2.81-2.8kS-bit shift register 2.6, decoder 2.7, 2.10 and Affairs of sinhroneziruyu output device 2. The word clock output of the counter 2.2 is the second synchronizing output device 2 and an R-input trigger 2.4. The Q outputs of counter 2.1 is connected to the Q inputs of the decoder 2.3 S bars where . The output of the decoder is connected to the S input of the trigger 2.4. The trigger output 2.4 connected to the first input element And 2.5. The second input element And 2.5, the input counter 2.1 and the input of the divider 2.9 are a clock input of the control unit 2 (24). The output element And 2.5 connected to the first input of the S bit of the shift register 2.6. Second input of the S bit of the shift register 2.6 is a control input of the control unit 2 (24). S outputs of the shift register 2.6 is connected to the S inputs of the decoder 2.7 and K outputs of the counter 2.2 is connected to the K inputs of the decoder 2.7. K outputs of the decoder 2.7 are the outputs of the control unit and K inputs of the decoder 2.10. V outputs of the decoder 2.10 are the first inputs of V elements AND 2.81- 2.8V. V outputs of the divider 2.9 are the second inputs of V elements AND 2.81- 2.8V. V the outputs of the elements AND 2.81- 2.8Vconnect with V inputs item OR 2.12. The output element OR 2.12 is the reset input of the divider 2.9, the meter inlet 2.2 and the third clock output control unit 2(24).

Warior 2.3, 2.7, 2.10 described /5, page 131, Fig. 1.95/.

An embodiment of the S-bit of the shift register described in 2.6 /3, page 209, Fig. 5.6/.

Implementation option elements AND / OR described in /4, page 176 Fig. 5.2/ and RS-flip-flop /3, page 174, Fig. 4.12/.

In shown in Fig.4 diagram of the control unit 2(24) for forming various permutations of k bits is used by the decoder, similar to the decoders 14 and 31, but with a different rule to convert binary codes. Part of the bits of the input code from S<<B symbols, where B is the base PSS, is formed from the initial pseudo-random binary characters SRP received at a control input of the control unit in the interval between the formation of the last digit of the previous information block and the first digit of the next. These bits define a variant of the pseudo-random sequence of numbers read bits from the outputs of the control unit depending on the quantum numbers coming from counter data cycles on the rest of the K inputs of the decoder (in addition to the above S inputs) in the control unit. Describes the functions of the decoder with high values of S and To more effectively can be accomplished by using reprogrammable or permanent zapomina the deposits received from the output of the decoder 2.7 non transferable discharge (in block 2) or received (block 24) in the binary code of the divider is 2.9, forming together with the elements OR 2.12 and 2.81- 2.8kpulse reading this discharge in accordance with the algorithm uses non-uniform energy distribution of signals between the individual bits of information blocks.

The interleave blocks 3, 23 are designed for periodic change of the position of the individual bits in the transmitted code blocks (4) and recover their original sequence (25) when taking into account the uneven read bits from the output of the block interleave 3 to the input of the phase modulator 4 and the output of the decision making unit 22 to the input of the block interleave 23. As a basis for the implementation of interleave blocks 3, 23 (together with the control units 2, 24) may be a device listed in /16/ pages 327-330 Fig. 8.11 in /17/ pages 83-85 Fig.2.10. In addition, an embodiment of the data blocks of the standard logic elements /3, 4, 5/ shown in Fig. 5

Block interleave 3(23) consists of a d-flip-flop 3.1, 3.16 elements AND 3.2, 3.3, 3.61- 3.6k, 3.8, 3.9, 3.111- 3.11k, 3.12, 3.13, k-bit shift registers 3.4 and 3.10, decoder 3.5, elements OR 3.7, 3.14, 3.15. The inputs of the decoder 3.5 are the control inputs of the device interleave 3(23). The outputs of the decoder 3.5 aplayer 3.1 is connected to the second inputs of elements And 3.8 and 3.9 and to the second input element And 3.13. Inverted output of D-flip-flop 3.1 is connected to the information input of D-flip-flop 3.1, and the second inputs of elements And 3.2 and 3.3 and to the second input of element B 3.12. The clock input of D-flip-flop 3.1 is the first clock input unit interleave 3(23).

The first inputs of elements And 3.3 and 3.9, the second input element And 3.13 are information input unit interleave 3(23), and the first inputs of elements And 3.2 and 3.8 are the second (third) clock input block interleave 3(23).

The output element And 3.2 is connected to the clock input k-bit shift register 3.4, and the output element And 3.3 connected to the information input k-bit shift register 3.4, and his k outputs connected to first inputs of elements AND 3.61- 3.6k. The outputs of the elements AND 3.61- 3.6kconnected to the corresponding inputs of the element OR 3.7. The output element OR 3.7 connected to the first input element And 3.13. The output element And 3.8 is connected to the clock input k-bit shift register 3.10, and the output element And 3.9 connected to the information input k-bit shift register 3.10, his k outputs to the first inputs of elements AND 3.111- 3.11k. The outputs of the elements AND 3.111- 3.11kconnected to the line And 3.12 and 3.13 connected to the first and second input respectively of the element OR 3.15. The output element OR 3.15 connected to the information input of D-flip-flop 3.16. The clock input of D-flip-flop 3.16 is the third (second) clock input block interleave 3(23). Direct output of D-flip-flop 3.16 is the output of the block interleave 3(23).

Implementation option elements AND 3.2, 3.3, 3.61- 3.6k3.8, 3.9, 3.111- 3.11k, 3.12, 3.13 described in /4, page 176 Fig. 5.2/.

An embodiment of the D-flip-flop 3.1, 3.16 described in /4, page 163, Fig. 4.26/.

An embodiment of the k-bit shift registers 3.4 and 3.10 described in /3, page 209, Fig. 5.6/.

An embodiment of the decoder described in 3.5 /5, page 131, Fig. 1.95/.

Implementation option elements OR 3.7, 3.14, 3.15 described in /5, page 35, Fig. 1.19/.

In shown in Fig.5 is a schematic block interleave 3(23) for combining procedures even read bits from the information source 1 (uneven reading of the decision making unit 22) in the order of their receipt of information input and procedures uneven read data bits from the output of the block interleave 3 to the input of the phase modulator 4 (uniform reading data bits from the output of the block interleave 23 to the input of the receiver 25) in the order specified by the sequence of the input shift register (with open cells And 3.2, 3.3 or 3.8 and 3.9) and the output storage register (in conjunction with the decoder 3.5, elements OR 3.15 and D-trigger 3.16 with open cells And 3.12 or 3.13 together with the elements AND 3.61- 3.6kOR 3.7 or elements AND 3.111- 3.11kand OR 3.14) due to the switching of the D trigger 3.1 clocked by pulses with a period T=KT0).

The phase modulator 4 is designed to change the polarity of the pulses of the reference pseudo-random sequence, forming PSS, in accordance with the polarity of the next samples of the transmitted information sequence. An embodiment of the phase modulator 4 is described in /8, Fig. 11.3 and Fig. 11.4, pages 273-274/.

The generator carrier frequency 10 generates a carrier frequency oscillation. An embodiment of the generator carrier frequency 10 described in /12, Fig. 7.6 and Fig. 7.7, page 212 and 217, respectively/.

The modulator 5 is designed to change phase high-frequency carrier oscillations in accordance with the polarity of the transmitted videokursov. An embodiment of the modulator 5 is described in /12, Fig. 5.13 page 157/.

Amplifiers 6,20 are designed to implement the algorithm amplitude manipulation of the PSS. Implementation will strengthen the on signal to the value necessary to compensate for losses in the environment of radio wave propagation. An embodiment of the power amplifier 10 is described in /13, Fig. 11.24, page 327/.

An antenna device 8, 16 are designed to convert high-frequency signal in the radio wave in the transmission (8) and back at the reception (16). An embodiment of the antenna device 8, 16 described in /8, Fig. 7.2 and Fig.7.4, pages 169-172/.

The sync block 9, 27 are designed to align processes functioning generators of pseudorandom sequence 10, 28, shift registers 12, 29, registers, storage 13, 33 and the control units 2, 24. In addition, the synchronization unit 27 at the receiving side radio controls setting the receiving channel on the received radio signal and determines the moments of reception of received binary pulses in the final block 22. Implementation option for sync blocks 9, 27 described in /9, page 266-328/.

The pseudorandom sequence generators 11, 28 are used to form the same on the transmitter (11) and receiving (28) the parties to the radio sequences are equiprobable binary pulses. Implementation option pseudorandom sequence generators 11, 28 described in /11, Fig. 20.20, page 357/.

R is x numbers and the implementation of procedures for converting serial data code numbers in parallel. An embodiment of the shift registers 12, 29 described in /3, pages 208-210, for example, Fig. 5.4 (C)/.

The storage registers 13, 30 are designed to hold the parallel code the next pseudorandom numbers over the duration of the formation and processing of a single subcell PSS. An embodiment of the storage registers 13,30 described in /3, pages 208-210, for example, Fig. 5.4 (a)/.

The decoders 14, 31 are designed to convert the pseudo-random numbers with uniform distribution in the pseudo-random numbers with a specified distribution in accordance with the algorithm uses AFM PSS. Implementation option decoders 14, 31 described in /4, pages 119-135/.

D / a converters 15, 32 are used to convert binary code to an analog voltage levels, control gains, respectively, of the amplifiers 6, 20. An embodiment of the digital-to-analogue converters 15,32 described in /4, pp. 185 - 193/.

The mixer 17 is designed to transfer the received signals to an intermediate frequency. An embodiment of the mixer 17 is described in /12, pages 151-159/.

The local oscillator 26 is designed to generate a frequency offset, which is the difference between the frequency of received radio is tx2">

The intermediate frequency amplifier 18 is designed to amplify the received radio signal to an intermediate frequency to the value required for the subsequent blocks of the receive path. Implementation of intermediate frequency amplifier 18 is described in /4, Fig. 2.2(g) and Fig. 2.2(K), page 27/.

The multiplier 19 is designed to remove pseudo-random manipulation of the received signal. An embodiment of the multiplier 19 is described in /6, Fig.4, page 203/.

The integrator 21 is designed for narrow-band filtering of the received signal. An embodiment of the integrator 21 is described in /12, Fig. 6.6(d), page 191/.

Crucial unit 22 is designed for reception of the next received binary information bits. A variant of implementation of the decision making unit 22 shown in /3, pages 363-371/.

The inventive device operates as follows.

In the transmitting part from information source 1 a sequence of binary symbols with a constant period0(T0the repetition period of the clock pulses of the second clock output control unit 2) to the input of the multiplier 3, which tracks the boundaries of the blocks of information, including k binary symbols (osna with period T=kT0), and within these boundaries is the permutation information symbols (digits) in accordance with the sequence numbers received in parallel with the control output of the control unit 2. Synchronously (but with a different repetition period of the clock pulses Ti, i= 1, k, where Ti- the current time interval between the pulses of the third clock output control unit 2) with data enter numbers corresponding binary symbol is read at the input of the phase modulator 4. Pseudolocality sequence number of the retrieved bits is provided by the corresponding transformation in the control unit 2 binary pseudo-random sequence received at the control input of this block with the additional (N+1) output storage register 13.

From the pseudo-random sequence generator (gpsa) 11 with an additional (N+1) output storage register 13 to the second input of the phase modulator 4 receives a binary signal with pulse width = T0/B, where B is the number of subcells PSS per information symbol. In fact, this number indicates the base PSS. The repetition period of the pulses at the output gpsa 14 equal 0the sequence of binary pulses from the output gpsa 14 is written in the shift register 12, and then the signals from the second output of the synchronization unit 12, the following frequency f = 1/ - in the storage register 13. With the first N outputs of the storage register 13 N bits of the binary random number R[0,...,2N-1] do for N inputs of the decoder 14. On the N outputs of the first decoder 14 receive the N-bit binary number equal to the value of one of the m 2 pseudo-random amplitudes corresponding to the sector number on the unit interval, which gets a random number R/2N(in this case, a geometric interpretation of the m-step discrete probability distribution). The ratio of these areas should correspond to the ratio of the probabilities of m different amplitudes of subcells according to the used algorithm AFM PSS /1/. Digital to analog Converter (DAC) 15 converts the input binary combination in an analog signal corresponding to one of the m pseudo-random amplitudes. From the output of the first DAC 15 the signal at the control input of the amplifier 6.

The synchronization unit 9 generates two pulse trains with frequencies f and (N+1)f. The second data sequence control 2.

The PSS sequence, transferring the information symbols from the output of the phase modulator 4 is supplied to the modulator 5, which is the phase modulation of the carrier wave supplied to the second input of the modulator 5, a generator carrier frequency 10. Photomanipulating pseudonoise signal output from the modulator 5 is fed to the input of amplifier 6. From the output of the amplifier 6 AFM PSS is fed to the input of amplifier 7, where the signal is amplified to the desired level and then through the transmitting antenna 8 is radiated into space.

In the receiving part of the radio signal, adopted by the receiving antenna 16, passes through the mixer 17 is transferred with the help of the local oscillator 26 to an intermediate frequency, is amplified in the intermediate frequency amplifier (if amplifier) 18. Output amplifier 18, the signal is sent to the multiplier 19, the second input of which the reference signal from gpsa 28 via an additional (N+1)-th output of the storage register 30. The result of the multiplication of the input and reference signals supplied to the amplifier 20, the gain of which depends on the level of the signal received at the control input of the amplifier 20 output DAC 32. The formation of the signal at the output of the DAC 32 is using gpsa 28, register of the DAC 15. From the output of the amplifier 20, the signal at the integrator 21 and further to the synchronization unit 27 and a deciding unit 22.

The synchronization unit 27 generates two pulse trains with frequencies f and (N+1)f, controls the operation mode deciding unit 22 searches the AFM signal PSS frequency and time. To search for AFM PSS frequency synchronization unit 27 rebuilds the local oscillator 26, and by time delays or accelerates gpsa 28 and its associated blocks. This, along with the juxtaposition in time of pseudo random sequences generated in gpsa 11 and 28, is provided by the combination of the boundaries of the blocks of information tracked by the control units 2 and 24. Due to this, the block interleave 23 after reading the received symbols from the output of the decision making unit 22 taking into account differences in their duration of Tion the basis of the sequence numbers coming from the K outputs of the control unit 24, restores the original sequence of information bits and with a constant repetition period T0give them the information receiver 25.

The positive effect of the inventive device will show in the following example.

Let the radio link transfer Ozerov obrazuemyh in the information source 1 in the k-bit binary code. As indicator of the quality of analog samples will be considered error variance 2aboutWcharacterizing the degree of deviation of the samples taken from the passed.

The total error variance2aboutWthe sum of the variance of the quantization errors2toinand variance of channel errors2toENcaused by the distortions of the individual bits in the communication channel. The variance of the quantization errors (assuming a uniform distribution Utbetween adjacent quantization levels) is determined by the formula2toin= U2o/12 where U0=Um/2k-1- step quantization. The variance of channel errors2toENdepends on the probability of distortion of the individual bits of the pOsh.i, i= 1,..,k, and can be accurately calculated by the formula /8/:

< / BR>
When using the radio link with AFM PSS with base B >> 1 action interference with any distribution is asymptotically equivalent to the effect of Gaussian noise /2/. In the worst case, when exposed to the i-th bit of coherent noise with a relative average poweri(allowing for intermittent exposure) the probability of the UB>i<0,7 B the worst interference is intermittent with a duty cycle of li/0,7 B) and the relative power of the noise pulse peak= 0,7 B.

We denote the ratio of the average interference power to average power of the signals on the duration of transmission of the k bits of one of the analog reference letter . Then, when the energy distribution of interference y={yi}kand the energy distribution of signals x= { xi}kget i= yi/xi. In Fig. 6 shows graphs of the error variance 2aboutWfrom the relative average interference power at different energy distributions of signal and noise at k=8. In particular, line 1 corresponds to the case of conventional uniform energy distribution signals with a uniform energy distribution of interference, i.e., xi= yil/ki= , i = l,...,k.

Line 2 corresponds to the worst energy distribution of interference y*={yi*}kwith a uniform energy distribution of the signals. This distribution y*depends on the size and is calculated, in General, by numerical solution of the somewhat cumbersome system of differential equations. With a small value for this distribution is characterized by the allocation of all energy interference which disguises all most of the energy of interference is allocated to suppress the younger grades. In particular, (k-1)-th digit starts suppressed by > 5B/k.

By introducing interleave bits can be excluded sighting suppression of high-order bits, resulting in the dependence of the dispersion error on the relative interference power will be guaranteed not above the line 1 in Fig.6. However, as follows from expression (1) is equal to the error probability of receiving individual bits of the contribution to the error variance of the distortion senior ranks much higher than the contribution of the distortion low. In General, at a known energy distribution of interference, it is possible to solve the corresponding optimization problem and find the best energy distribution of the signals, and then implement it in the proposed radio link with AFM PSS. It can be shown that in the worst case when the unknown distribution of the interference limited average power is the best energy distribution of the signals is described by the expression

< / BR>
Note that from the expression (4) should a simple ratio: i/xi-1= 4, i = 2,...k, simplifying the implementation of this uneven distribution by uneven distribution of discrete time intervals that are multiples of four. When using the energy distribution of the signals (4) it is guaranteed that at any the t above the line 3 in Fig.6.

In Fig. 6 shows graphs of the dispersion error on the relative interference power at different energy distribution of signals and interference between the bits of the digitized analog samples. As follows from the graphs in Fig. 6, when using uneven distribution (4) energy signals in line with AFM PSS guaranteed energy gain in the region of small noise about 13 dB compared to the case with uniform distribution without alternation and about 5.5 dB compared to the case with uniform distribution with alternation.

Literature

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2. Chudnov A. M. the correlation Immunity of a reception pseudo-random signals, modulated in amplitude and phase //radio engineering and electronics, 1987. -T. XXXII. - N1, - N-62-68.

3. Alekseenko, A. G., Sagarin And. And. Microcircuitry. M.: Radio and communication, 1982. - 414 S.

4. Batashev Century A. Circuits and their application. M.: Radio and communication, 1983. - 271 S.

5. Shyla Century Popular HP digital chip. M.: Radio and communication, 1988. - 352 S.

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9. Varakin L. E. communication Systems with noise-like signals. M.: Radio and communication, 1985. - 384 S.

10. Banquet Century A. Dorofeev, C. M. Digital techniques in satellite communications. M.: Radio and communication, 1988. -213 C.

11. U. Titze, K. Schenk. Semiconductor circuitry: a reference guide. M.: Mir, 1982. - 512 S.

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14. Macaw A. A., szczerba Century, the Interfaces of the data processing systems. M.: Radio and communication, 1989. - 416 S.

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The wireless link with the amplitude-photomanipulating noise-like signals with the transmitter is Amnesty, the antenna device, the synchronization unit, the pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter, and the output of the phase modulator connected to the first input of the modulator, the output of the generator carrier frequency is connected to the second input of the modulator, the output of which is connected to the information input of the amplifier, the output of which is connected to the input of the power amplifier, the output of which is connected to the input of the antenna device, the first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register, and its second output connected to the clock input of storage register, the output of a pseudorandom sequence generator connected to the information input of the shift register, (N+1) informational outputs of the shift register, where N is 2, is connected to the corresponding (N+1) information input storage register, N informational outputs of the storage register connected to the corresponding N to the information inputs of the decoder, and the additional (N+1) output of the storage register connected to the second input of the phase modulator, the N outputs of the decoder are connected to the respective N inputs analog is nanoe device, mixer, intermediate frequency amplifier, a multiplier, amplifier, integrator, the deciding unit, a local oscillator, the synchronization unit, the pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter and receiver information, and the output of an antenna device connected to the first input of the mixer, the mixer output is connected to the input of the intermediate frequency amplifier, the output of which is connected to the information input of the multiplier, the output of which is connected to the information input of the amplifier, the output of which is connected to the input of the integrator, the output of which is connected to the input of the decision making unit and to the input of the synchronization unit, the first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register, the second output of the synchronization unit is connected to the clock input of the storage register, the third output of the synchronization unit is connected to the input of the local oscillator, the output of which is connected to the second input of the mixer, the output of a pseudorandom sequence generator connected to the information input of the shift register, (N+1) informational outputs of which are connected to the corresponding (N+1) information in the ladies decoder, and the additional (N+1) output of the storage register connected to the control input of the multiplier, N outputs of the decoder are connected to the respective N inputs to analog Converter whose output is connected to the control input of the amplifier, characterized in that additionally introduced on the transmission side control unit and the power alternation, and the output of the information source connected to the information input unit interleave, output block alternation connected to the first input of the phase modulator, an additional (N+1) output of the storage register connected to the control input of the control unit, the second output of the synchronization unit is connected to the clock input of the control unit, the first and second clock outputs a control unit connected to the respective clock inputs of the data source and block interleave, and the third clock output control unit connected to the third clock input block alternation, To control output of the control unit, where K2 is connected to respective control inputs of the block alternation, and at the receiving side inputs of the control unit and the power alternation, and the second output of the synchronization unit podkiwu the input of the control unit, the first and second clock outputs a control unit connected to the respective clock inputs of the block interleave, and the third clock output control unit connected to the third clock input block interleave and the clock input of the decision making unit To control output of the control unit are connected to respective control inputs of the block interleave, output deciding unit connected to the information input unit of alternation, and the output of block alternation connected to the input of the receiver information.

 

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