The regeneration method for dynamic storage devices with random access


G11C11/403 -

 

(57) Abstract:

The invention relates to a method of regeneration of the memory cells in the dynamic memory device with random access and, in particular, to a method, which reduces interference regeneration on the tension drain dynamic memory with random access, having a CMOS structure. The technical result is an increase in time to restore the voltage to its original level. How is that in the process of regeneration cycles provide serial access to the memory blocks that do not share a common capacitor snubber. 2 s and 5 C.p. f-crystals, 4 Il.

The present invention relates to a method of regeneration of the memory cells in the dynamic memory device with random access and, in particular, to a method, which reduces interference regeneration on the tension drain dynamic memory with random access, having the CMOS structure (complementary structure of metal-oxide-semiconductor).

The background to the present invention

As is well known in this technical field, dynamic storage ustroystva random access to data stored in each memory cell is not destroyed or decayed beyond the stipulated time. By periodic regeneration of each line memory in a dynamic storage device, random access to each cell of the capacitive memory in the string energy serves so as not to corrupt the data stored in the memory cells.

Thus, the volatile memory devices regeneration is an essential element of the storage mass storage device.

Regeneration can be sampled address column before regeneration sampling line address or only the regeneration sampling line address. Sample address column before regeneration sampling line address includes the establishment of a level of a signal sample address column before installing the signal sample address line to indicate that the next cycle is the regeneration cycle. In response to the setting signal sample address column before establishing signal sampling line address internal address counter in the memory device reports the address line of the next line, subject to regeneration. Regeneration only fetch address line works similar oegema regeneration, reported external regeneration scheme.

However, whenever is regeneration, the emission current in a recycled dynamic storage device, random access leads to a fall in the voltage applied to dynamic storage device with random access. Interference caused by the voltage drop of the network may affect the work of this dynamic memory with random access, or other dynamic devices, random access, on which it is served. This is especially true for dynamic storage devices with random access, using CMOS technology, since the internal circuits such dynamic storage devices with random access particularly sensitive to sudden voltage drops or interference.

Thus, to avoid large bursts of interference in the process of the regeneration cycle ways regeneration, the relevant prior art, provide the estimated regeneration in a checkerboard pattern, carried out in the adjacent memory modules with a single pin, so that the regeneration was carried out, slimpulse. In addition, to reduce the magnitude of the voltage drop caused by accesses regeneration, provide capacitors snubber for each memory block to maintain voltage during large discharge current. Although this method is designed to distribute the voltage drop arising in the process of regeneration, even many of the repetition periods of the clock or the clock pulses, reducing the voltage drop is not yet optimized. This is because sometimes adjacent memory blocks share one or more capacitors, snubber, so if, for example, the first and second memory blocks regenerate in series, capacitors snubber does not have enough recovery time to re-charge to the nominal mains voltage. Thus, if the memory blocks that share the same smoothing capacitor filter, regenerated over successive repetition periods of the clock or the clock pulses, there is a likelihood that on-line supplying an electrical voltage that is connected with having access blocks of memory, there is a big drop narasappaya device with random access.

Known method of regenerating blocks of dynamic memory (SU inventor's certificate 982081 G 11 C 11/401, 1982). The disadvantages of this method above.

The aim of the present invention is to eliminate these disadvantages.

This goal is achieved by using the method of regeneration of the non-volatile memory blocks, comprising initiating regeneration of memory blocks, and to smooth the voltage drop on the supply line voltage using the capacitor of the smoothing filter common to the first and second memory blocks, and first initiate regeneration of the first memory block, then initiate regeneration of the third memory block, and then initiate the regeneration of the second memory block. Preferably the first, second and third memory blocks are memory blocks, made by CMOS technology. Mainly additionally provide for initiating regeneration of the fourth memory block following the initiation of the regeneration of the second memory block, and these third and fourth memory blocks share the other capacitor of the smoothing filter. Usually each regeneration involves the selection of the address column in front of regionsize drop of the voltage supplied during regeneration of memory blocks, including initiating regeneration of memory blocks, and initiate regeneration of the first memory block together with the second memory block using at least one capacitor of the smoothing filter to initiate regeneration of the specified second memory block after holding a sufficient number of regeneration cycles initiated on the memory block that does not use the specified capacitor used in the first and second blocks, and the specified regeneration of the second memory block is performed so that the voltage drop across these first and second memory blocks was not higher than the voltage drop across the first and second blocks with separate conduction of regeneration on these blocks. Mainly specified a sufficient number of regeneration cycles is one regeneration cycle. Preferably each specified regeneration involves the selection of the address column is conducted to the regeneration of an address selection line.

Brief description of drawings

Fig. 1 is a basic block diagram, which illustrates two pairs of memory blocks, each of which shares the capacitor of the smoothing filter.

Fig. 2 - timing diagram, kotoraya level of technology.

Fig. 3 is a timing diagram that illustrates the order of accesses regeneration to each of the memory blocks shown in Fig. 1, in accordance with the method of the present invention.

Fig. 4a-4c is a schematic signal flow, which illustrate the voltage drop that occur in the process of regeneration for the case where (a) - method of the prior art used to access staggered in adjacent memory blocks that do not use the capacitor of the smoothing filter; (b) the method of the prior art used for the regeneration of the adjacent memory blocks that share the same capacitor of the smoothing filter; and (c) is a method corresponding to the present invention, used for access to adjacent memory blocks in spaced intervals, where the capacitor of the smoothing filter used in conjunction between the memory blocks.

A detailed description of the preferred alternative implementation of the present invention

Fig. 1 is a fundamental block diagram that illustrates some number of blocks 100 memory dynamic memory with random access in connection with the line 110 to the supply voltage. As pok is a block 130 memory dynamic memory with random access share battery 140 capacitors snubber. This design is typical for those applications where, for example, memory, ROM, and conclusions are made so as to have a dynamic memory with random access on both sides of the PCB. As will be obvious to the ordinary skilled in this technical field, the battery 140 of the capacitor may include a number of capacitors that are shared by each of the elements of the dynamic memory with random access in blocks 120,130 memory dynamic memory with random access. Similarly, as additionally shown in Fig. 1, the third block 150 memory dynamic memory with random access, and the fourth block 160 memory dynamic memory with random access share battery 170 capacitors.

In the process, the regeneration of the memory cells in each of the blocks 120, 130, 150 and 160 memory dynamic memory with random access is carried out in a specified order to reduce the instantaneous current consumption line 110. As is well known skilled in this technical field specialists, is the sudden electric surge there is a chance that in that location line 110 will be a large voltage drop. For this reason, the capacitors 140, 170 smoothing filter is included in several places on line 110 voltage source to reduce the effects of such voltage drop. In addition, to reduce the total emission current in any given place along the line 110 accesses regeneration, which are often responsible for sudden inrush currents on the line 110, is carried out in a checkerboard pattern.

Some of the ways corresponding to the prior art, the reduction of the emission current in any given place along the line 110 provided for the regeneration carried out in a checkerboard pattern, each of the memory blocks dynamic memory with random access to the selector line address line was not installed at the same time for any of the blocks 120, 130, 150, 160 memory dynamic memory with random access. As shown in Fig. 2, to initiate a regeneration operation, after the selector lines of the column address is sequentially set each of the gate lines address lines (i.e. lines corresponding to each block 120, 130, lektornye signals of the address line set in rapid sequence to blocks of memory dynamic memory with random access, together using the same capacitors snubber, there is a probability that the capacitors snubber will not have enough time for recovery after discharge current that follows the installation of the sample of the first line, so that additional emission current, which follows the setting of the selector signal of the address of the second line causes a voltage drop along the line 110 from the voltage level, which is already below the normal voltage level. This case is illustrated in Fig. 4a and Fig. 4b. In particular, in Fig. 4a shows the voltage drop that would otherwise occur along the line 110 in blocks 120, 130 memory dynamic memory with random access, if the signal is an address selection line of the second memory block is installed directly after the signal sampling access line of the first memory block (as shown in Fig. 2) in the absence of capacitor 140 smoothing filter. Thus, in Fig. 4a illustrates the close proximity of the voltage drops observed on the voltage inputs in blocks 120, 130 memory dynamic memory with random access, when these adjacent memory blocks regenerate in posledovateljami filter presents on line 110 connecting blocks 120, 130 memory dynamic memory with random access, the observed voltage drop has the appearance as shown in Fig. 4b. Although the voltage drop observed at the voltage inputs in blocks 120, 130 memory dynamic memory with random access is not as great as the voltage drop, which would, if it were not for the capacitor 140 at the first voltage when the second voltage, while the voltage on line 110 near the blocks 120, 130 memory dynamic memory with random access has not yet recovered to their original values when you install the second gate signal line address there is a big drop. Thus it is obvious that in some cases, the method corresponding to the prior art, leads to a significant voltage drop on the input voltage, contiguous blocks of memory dynamic memory with random access, if the regeneration is carried out in rapid succession, so that the capacitor 140 smoothing filter has no time to recover from the initial voltage drop. This problem is further compounded by, the technology, since CMOS technology is particularly sensitive to interference when such voltage drops.

However, in accordance with the present invention offers an improved way of accessing blocks of memory dynamic memory with random access in the regeneration process, as shown in Fig. 3. As shown in Fig. 3, the sequence of regeneration dynamic memory with random access change so that the blocks of memory dynamic memory with random access, together using the same capacitors snubber, had no access in successive repetition periods of the clock or the clock pulses. That is, as shown in Fig. 3, the sample address line used for the regeneration of the second block 130 memory dynamic memory with random access, set before the selector signal line address used for the regeneration of the fourth block 160 memory dynamic memory with random access, next before the selector signal line address used for the regeneration of the first block 120 dynamic memory , ispolzuemyi for the regeneration of the third block 150 memory dynamic memory with random access. Thus, from Fig. 3 it follows that regeneration of memory blocks that share the same capacitor snubber, never initiate in successive periods of repetitions clock or clock.

The benefits of this advanced regeneration sequence shown in Fig. 4c. As shown in Fig. 4c, the voltage drop sufficiently spaced relative to each other so that the capacitor 140 has sufficient time to recover to the original value 5B before the capacitor 140 is observed following the voltage drop. In this case, the voltage inputs of the blocks 120, 130 memory dynamic memory with random access are only a small voltage drop. Similar effects are also observed in blocks 150, 160 memory dynamic memory with random access. Thus, an improved method for the regeneration sequence corresponding to the present invention, ensures the absence of a significant voltage drop in any of the b the l described in detail the preferred implementation of the present invention, a qualified specialist in this field of technology are obvious modifications which may be made without deviating from its scope or essential characteristics. For example, the present invention can be used in the system where instead of sampling access column before regeneration sampling line address carry out regeneration only a sampling of the access line. For this reason, the scope of the present invention should be interpreted in the light of the attached claims.

1. The regeneration process of the nonvolatile memory blocks, comprising initiating regeneration of memory blocks, wherein the smoothing of the voltage drop on the supply line voltage using the capacitor of the smoothing filter common to the first and second memory blocks, and first initiate regeneration of the first memory block, then initiate regeneration of the third memory block, and then initiate the regeneration of the second memory block.

2. The method according to p. 1, wherein the first, second, and third memory blocks are memory blocks, made by CMOS technology.

3. The method according to p. 1, characterized in that it further include initiating rasanya third and fourth memory blocks share the other capacitor of the smoothing filter.

4. The method according to p. 1, characterized in that each regeneration involves the selection of the address column before regeneration sampling line address.

5. The way to reduce the drop of the voltage supplied during regeneration of memory blocks, comprising initiating regeneration of memory blocks, wherein initiate regeneration of the first memory block, together with the second memory block using at least one capacitor of the smoothing filter to initiate regeneration of the specified second memory block after holding a sufficient number of regeneration cycles initiated on the memory block, nailpolishes specified capacitor used in the first and second blocks, and the specified regeneration of the second memory block is performed so that the voltage drop across these first and second memory blocks was not higher than the voltage drop across the first and second blocks with separate conduction of regeneration on these blocks.

6. The method according to p. 5, characterized in that the sufficient number of regeneration cycles is one regeneration cycle.

7. The method according to p. 5, characterized in that each of the specified regeneration involves choosing the

 

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