Process for the selective programming of non-volatile memory
(57) Abstract:The invention relates to the field of programming non-volatile storage. The technical result is to reduce energy consumption. How is that first put a negative programming voltage to all tyres words WLi, WLj, and then all messelektronik tyres words WLj apply a positive voltage to compensate them negative charges. 2 C.p. f-crystals, 2 Il. Programmable non-volatile cumulative cell (memory cell) are in an electrically floating state, the gate electrode, the so-called "floating gate" ("Floating Gate"). This floating gate is separated by an insulating layer from a channel region of cumulative cell that is otherwise made in the form of a MOS transistor, and the electrode of the control gate and located between them.Programming of the cell is due to the fact that the floating gate electrode is applied charge. Due to this charge changes the threshold voltage, i.e. the voltage at which forming of the cumulative cell field MOS transistor begins to conduct. When reading the cell, then to control grammirovanie and programmed cell. Depending on flows do then talk, read, or logical "0" or logical "1".Still there are two ways that can be applied to the charges on the floating gate. In the first method, to the control gate is applied a high positive voltage of about 12 V, while the drain and source forming a cumulative cell MOS transistor is applied typically 7 or 0, that is normal for MOS circuits working voltage. Due to this, through the channel of the MOS transistor flows in a strong current, from which the so-called "hot" electrons hit the "floating gate".Another way to control shutter apply the high negative voltage of about 12 V, while the drain applied voltage of about 5 V. For this hole tunneling through the gate oxide to the floating gate and charge it positively, due to which the threshold voltage generating cumulative cell MOS transistor decreases.This method though has the advantage that when charging the floating gate through the channel does not flow any current losses, however, creates the problem of requiring selective vklyucheno here can not be applied, as its n-doped region of the drain or the source for the application of a negative voltage formed would be quasi-short circuit linked with the case of p-doped substrate.So is the normal position for this purpose n-channel MOS transistors in the p-doped tub, isolated because of the deep n-stainless steel tubs. Here, however, there are additional technology costs, special equipment, such as high-energy installation for ion implantation, and the risk of possible charges isolated tubs and associated stress the gate oxide during the process.Another solution is known from EP 0 456 623 A2. There is a high negative voltage to include bus words non-volatile memory through the p-channel MOS transistors. These p-channel MOS transistors though and can be produced by the conventional methods, however, require to enable negative voltage of the gate. It is generated by inverting the voltage circuits from a high positive voltage. In any case, these inverting voltage circuit is required for each bus that requires considerable circuit-technical outlay.
Fig. 1 is a schematic representation of the non-volatile memory for implementing the method according to the invention;
Fig. 2 is a time chart for a visual representation of the method according to the invention.Schematically shown in Fig. 1 non-volatile memory shows the cumulative matrix of an ordered structure with cumulative ST cells arranged in rows and columns. Cumulative cell ST can be selected via bus words WL1...WLi, WLi+1 and bit (bit) bus... BLi-1, BLi, BLi+1... in order to have the possibility of programming, erasing and reading. For programming specific cumulative STi cell to the corresponding bus words WLi should kiss high negative programming voltage to the corresponding bit bus BLi normal positive voltage of about 5 C. High negative voltage generated by the negative charge pump NLP and through the diode D, which is formed by p-channel MOS transistors, is applied simultaneously to all tyres words WL1... WLi, WLi+1... All tyres words WL1... WLi, WLi+1... through switches S can svedka 5th Century The switches S are controlled by the circuit SEL to select bus words. They can, for example, be formed of CMOS inverters.In Fig. 2 presents the time course of the method according to the invention. At time t0 include a negative charge pump NLP. It creates point-in-time t1 required high voltage of about -12 C. This voltage is simultaneously applied through the diode D to all tyres words WL1... WLi, WLi+1. .. so that they are charged to negative voltages. This is shown in Fig. 2 for selected for silage preparation or respectively selected bus words WLi and the unselected tyres words WLj. At time t2, the negative charge pump NLP off again. To the next shortly after the time t3, the switches S of all unselected tyres words WLj closed so that these tyres words WLj is connected with a positive voltage on the negative charges due to this offset. Due to the diodes D of these positive charges have no impact on the selected bus words WLi so that it retains its negative charge. The time of discharge thus negatively charged tyres words WLi can be many seconds so that there is dostatus, to program the selected cumulative cell or selected cumulative STi cell. After the time t4 the last programming pulse has been applied to bit bus BLi, the programming process is complete and tyres words WLi and WLj are in a neutral state. 1. Process for the selective application of negative programming voltage to the bus words WLi non-volatile memory with consecutive steps: a) application of negative programming voltage to all tyres words (WLi, WLj), (b) disconnect the negative programming voltage so that all tires of words (WLi, WLj) are in a floating state, (C) the application of a positive voltage to all messelektronik tyres words (WLj).2. The method according to p. 1, characterized in that the negative programming voltage is applied to the tires of words (WLi, WLj) through the diode (D).3. The method according to p. 2, characterized in that the diode (D) is formed by p-channel MOS transistors.
FIELD: information technology.
SUBSTANCE: method of programming a NAND flash memory IC, in which device initialisation is carried out, for a data read command, the read command cycle is executed, the required number of cycles for establishing the page address is executed, for a data write command, the write command cycle is executed, the required number of cycles for establishing the page address is executed, for a data delete command, the delete command cycle is executed, wherein after receiving the commands, command parameters are extracted, and after executing the given number of data read cycles, the page address is incremented and the parity between the number of read pages and the given number is checked, for a command to establish IC parameters, IC parameters are stored in the parameter register of a flash-interface, these parameters are applied and then switched to the cycle for waiting for the next command.
EFFECT: broader functional capabilities of NAND flash-memory IC programmers by creating a flexible, user adjustable interface for communicating with the NAND flash-memory IC, which enables to work with all NAND flash-memory ICs, as well as by adding functions for reading the identification number of the IC, reading the status of the IC and an IC reset function.
7 cl, 3 dwg
FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering. Method of data recording into smart card nonvolatile memory device comprises input of recording command into smart card volatile memory device buffer memory; comparison by smart card of object identification parameter corresponding to recording command with object identification parameter, stored in smart card nonvolatile memory; with positive result of comparison: recording of intended for recording data included into recording command, from buffer memory into object corresponding to recording command, on predetermined address, which value is stored in nonvolatile memory; calculation of address corresponding to sum of predetermined address and recorded data size; storing of calculated address instead of predetermined address; with negative comparison result: recording of intended for recording data included into recording command from buffer memory into object corresponding to recording command, to default address; calculation of address corresponding to sum of default address and recorded data size; storing of calculated address as predetermined address.
EFFECT: technical result consists in large size data recording to smart card.
9 cl, 3 dwg
FIELD: computer engineering, possible use for designing rapid action clocked recording devices of high capacity.
SUBSTANCE: decoder contains field transistors of first and second conductivity types (8-19), zero first (1), zero inverse (2) and first, second, ..., n (3) address inputs, input of mode selection (4), power contacts of first (5) and second (6) of voltage level, block of parallel-connected n transistors (7) with channel of first type, gates of which are connected to corresponding n inputs (3), first output buffer element (20), output of which is the first output (21) of decoder, second output buffer element (22), output of which is the second output (23) of decoder.
EFFECT: increased reliability and reduced mass-dimensional characteristics.
FIELD: charge reading device and energy-independent memorizing device with passive matrix addressing.
SUBSTANCE: charge reading device contains two charge support means, two pseudo-differential support reading amplifiers (RSA1; RSA2) and a pseudo-differential reading amplifier (SA). Another variant of the device is meant for reading charges from a set of means (701) for charge storage and contains at least two pairs of charge supporting means, two pseudo-differential support reading amplifiers (RSA1; RSA2) and at least two pseudo-differential reading amplifiers (SA). Energy independent memorizing device with passive matrix addressing contains dielectric memorizing material, having hysteresis and capable of electrical polarization, and aforementioned system of reading amplifiers.
EFFECT: improved charge balancing, output signal control, ensured automatic shift in cophased mode, automatic correction of zero level shift.
3 cl, 10 dwg
FIELD: method, aimed at weakening interfering voltages which occur in data storage device which has passive matrix addressing.
SUBSTANCE: in accordance to the method, injection of electric potentials is performed in time-coordinated manner, which corresponds to impulse injection protocol. During execution of addressing operation a memory cell adjusts to first polarization state by receiving first active voltage impulse. Then, depending on the protocol used, second voltage impulse is injected, which may be second active voltage impulse with polarity which is opposite to polarity of first impulse. Given voltage impulse is used for switching the cell to second polarization state. Cells of device are configured in two or more electrically divided segments in such a way, that each segment corresponds to an individual space of physical addresses. During conduction of addressing operation data is directed into segment, which is selected on basis of information about previous and/or planned injections of active voltage impulses into segments.
EFFECT: increased efficiency.
36 cl, 35 dwg
FIELD: information technology.
SUBSTANCE: electronic device for saving power in a memory device has memory comprising a plurality of number buses. The memory includes a plurality of memory banks, wherein each of the plurality of memory banks includes a pair of sub-banks, each pair of sub-banks sharing pre-decoded data. The electronic device also includes a plurality of number bus generators connected to memory, wherein each number bus generator is associated with the number bus from the plurality of number buses of the memory. Power in each of the plurality of number bus generators is switched off in the default state except during the period for accessing the number bus. The electronic device also includes a decoder which is connected to the plurality of number bus generators in order to receive a request for accessing memory, and in order to decode the request for accessing memory in order to determine the address associated with the request for accessing memory. The decoder records the selected number bus generator but not other number bus generators from the plurality of number bus generators, in response to the request for accessing memory.
EFFECT: reduced current leakage in memory devices.
11 cl, 9 dwg, 3 tbl
FIELD: information technology.
SUBSTANCE: dual voltage semiconductor memory device having a plurality of write drivers receiving low voltage data input signals; a plurality of bit lines connected to the plurality of write drivers, wherein the plurality of write drivers is configured to write low voltage data input signals in the plurality of bit lines in response to reception of low voltage data input signals; a timing tracking circuit configured to delay a high voltage number line signal in accordance with the time associated with the plurality of write drivers which write low voltage data input signals; and a plurality of memory cells which react to the high voltage number line signal and the plurality of write drivers writing the low voltage data input signals.
EFFECT: reduced power consumption.
30 cl, 6 dwg
FIELD: information technologies.
SUBSTANCE: device comprises four logical NOT elements, four logical AND elements, two signal breeders.
EFFECT: increased efficiency and development of a device, in which internal transformation of information is carried out in two-digit current form of signals determined by condition of input current binary signals.
4 cl, 10 dwg
FIELD: physics, communications.
SUBSTANCE: invention relates to digital communication systems, and specifically to methods of retransmitting data via a user datagram protocol (UDP). Method comprises comparing a current user datagram with a previous datagram. In case of detecting a loss, a mechanism for re-requesting the lost datagram is launched, which is executed until the lost datagram is obtained. In the device, a payload processing unit includes a lost datagram read and search control unit, a re-request timer, a lost datagram search unit, a unit for reading useful data from a useful data storage unit, a recorded/read datagram counter, an overhead information recording unit, a payload data receiving unit, a useful data recording unit, a FIFO unit, a datagram read and search multiplexer, and the payload processing unit of the transmission unit includes an error packet forming unit, a re-request system control unit, a processed data counter, a transmitted data counter, a useful data recording unit, a useful data multiplexing unit, a useful data read unit.
EFFECT: invention reduces data loss while maintaining high speed characteristics.
3 cl, 8 dwg, 2 tbl
SUBSTANCE: device comprises a cell memory matrix with banks, wherein each bank includes rows, the first word lines provided in accordance with the rows, an address latch-circuit, which latches the first row address signal, a row decoder, which activates one of the first word lines, and a control circuit, that is configured to perform the first operation, which activates one of the banks on the basis of the bank address signal, when the first instruction is loaded, and the second operation, which latches the first row address signal in the address latch-circuit and to perform the third operation, which activates one of the first word lines by the row decoder on the basis of the second row address and the first row address signal latched in the address latch-circuit, when the second instruction is loaded after the first instruction.
EFFECT: increasing the number of the address bits with the unchanged device specifications.
35 cl, 21 dwg
FIELD: radio engineering, communication.
SUBSTANCE: device contains at least two data channels; At least two memory chips installed one on top of another in the form of a stack. The memory chips include at least two memory units and at least a portion of the first data channel and a second data channel portion; And at least the first and second chip-chip connections. The first chip-chip connection is configured to connect the respective portions of the first data channel included in the first and second memory chips to form a first data channel, and the second chip-chip connection is configured to couple corresponding portions of the second transmission channel data included in the first and second memory chips to form a second data channel. Each of the communication channels thus formed is selectively connected to the first and second memory units included in the first chip of the memory and to the first and second memory units included in the second memory chip. Each of the memory units included in the first memory chip is configured to provide data into one channel from the formed data channels, and each of the memory units entering the second memory chip is configured to provide data to another channel from the generated data channels.
EFFECT: increase the data transfer speed and system memory bandwidth.
25 cl, 10 dwg
SUBSTANCE: semiconductor memory device capable of performing the first mode with the first delay and the second mode with the second delay, greater than the first delay, contains a block of pads configured to accept external address and command; the first delay circuit configured to delay the address at the time corresponding to the first delay; the second delay circuit including shift registers connected in series and configured to delay the address at the time corresponding to the difference between the first delay and the second delay; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode, wherein the first mode and the second mode are write operations or read operations, the controller is able to perform one of the first mode and the second mode.
EFFECT: reducing the number of shift registers used for the delay.
12 cl, 32 dwg