Semiconductor memory

 

(57) Abstract:

The invention relates to a synchronous dynamic memory with random access. Memory allows you to access the data in the matrix of memory cells synchronously with the system clock from an external system, such as the Central processor. Synchronous memory includes a matrix of memory, divided into two banks of memory. Each of the banks can be either in an active cycle or in a cycle of regeneration. In each of the banks contains line decoder, buffers I / o. The selected memory Bank, responding to the activation signal, operates in an active cycle, while the non-selected memory Bank, responding to the signals of the absence of activation, will work in the regeneration mode. The technical result of the invention is to provide a synchronous dynamic memory with random access, in which input and output are free to synchronize external system clock high-speed data transmission. 3 C.p. f-crystals, 62 Il, 3 tables.

The invention relates to semiconductor memories and in particular to a synchronous dynamic memory with random access, which is able to provide about the pipeline processor (CPU).

A computer system typically includes a CPU for executing commands according to the tasks and main memory for storing data, programs and the like requested by the CPU. In order to improve the performance of computer systems mainly trying to increase the speed of the CPU, and make the access time to main memory as short as possible, so that the CPU could work, at least without of wait States. Cycles of clock pulses modern CPUs, such as the latest microcontrollers, reduced more and more with a clock frequency of 33, 66, 100 MHz, and the like. However, the working speed dynamic memory with random access (DRAM) with a high degree of integration, which is very cheap from the point of view of cost per bit and is used as a main memory device, not able to keep up with the increasing speed of the CPU. For DRAM is characterized by the minimum access time (address strobe line), i.e. the minimum period of time between an active state during which the signal changes its level from high to low and provides data output from a crystal with the address column, fixed activation (address strobe column). Such access is called "delay from metal called "delay from (delay of data output activation signal ). In addition, the required regeneration time before the subsequent cycle or a read operation. These factors reduce the overall operating speed of a DRAM, causing wait States for the CPU.

To compensate for the gap between CPU performance and the speed of the main memory like DRAM, a computer system includes enhanced high-speed buffer memory, such as cache memory, which is located between the CPU and main memory. The cache memory stores data requested by the CPU from main memory. When the CPU requests data, the controller cache intercepts the request and checks the cache for the presence in it of these data. If the required data is there, it is called a "cache hit", and high speed data transfer occurs immediately from the cache memory in the CPU. If they are not there, then it is called a "cache miss", and the controller cache memory reads the data from the slower main memory. These read data stored in the cache memory and sent to the CPU. Thus the following query this data, they can be immediately read from the cache memory. In the case of a cache hit can be made high-speed data transfer from the cache memory. Addtoany standby CPU. Thus it is extremely important to develop DRAM used as the main memory, so as to ensure high-speed operation.

Data transfer between the DRAM and the CPU or cache the consecutive blocks of information or data. For transmission of serial data at high speed DRAM implemented various kinds of operating modes, such as page, static column, polarity etc. These operating modes are described in U.S. patent N 3969706 and N 4750839. The matrix cells of the DRAM polubite regime is divided into four equal parts, so that the multitude of memory cells can be accessed by the same address. The data temporarily stored in the shift register, so that they can be sequentially read and write. However, since DRAM with polubite regime cannot forward continuously for more than 5-bit data, such a system may not be proposed for use in high-speed data transmission systems. The page mode and static column mode, after you select the same row address within one period, can be consistently refer to the column addresses in synchronism with the switching, or cycles, and the motion of addresses strnom time such as setup time and the retention time column address to receive the next address column after selecting previous, it is impossible to refer to coherent data access frequency to the memory above 100 bps, that is, it is impossible to reduce the cycle times below 10 NS. Also, since any reduction in cycle time page mode cannot guarantee sufficient time to select a column to write data in the selected memory cell during a write operation, the memory data can be written with errors. However, as these high-speed operating modes are not synchronized with the system clock CPU, whenever the CPU is replaced with a higher speed, the system data transfer should use the newly developed DRAM controller. Thus, to be able to work together with high-speed processors such as CISK and RISK (computers with a simplified set of commands), there must be the development of a synchronous DRAM, which would make it possible to access data synchronously with the system clock pulse of the microprocessor at high speed. The mention of the synchronous DRAM without detailed disclosure schemes appeared in Nikkey Microdevices in April, 1992, pages 158-161.

For pallah to work not only at various frequencies of the system clock, but also to be able to program the DRAM to operate in different modes, such as:

with a delay, depending on the frequency of the clock pulses;

with the length or size of the package that defines the number of output bits;

addressing columns, etc.

Examples of selecting the operating mode in the DRAM described in U.S. patent N 4833650, issued may 23, 1989, and in U.S. patent N 4987325, issued January 22, 1991, in which pursues the same goals. In these previous developments disclosed technology select one of the operating modes, such as page, static column and nibble. Operating mode selection in these previous projects carried out by the destruction of the fuse jumper with a laser beam from an external laser or electric current from an external power source or by using specially designed pads. However, in these earlier technologies can be selected only one operating mode, and the selected operating mode cannot be changed to another operating mode. Thus, prior design have the disadvantage that it is not allowed to change operating modes, if necessary. The present invention is shannow dynamic random-access memory, high performance, in which input and output data that may be synchronized by an external system clock, memory, which allows to work with high speed data transfer.

This synchronous dynamic random-access memory designed to operate at different frequencies of the system clock, and the number of input or output data can be configured.

Another problem solved by the present invention is the creation of a computing device, in which computing operations could be performed either in binary or in the alternate mode.

Another problem solved by the present invention is the creation of a semiconductor memory, which can prevent unnecessary internal operations in the crystal memory, regardless of the number of input or output data, and can set the different operating modes.

Another problem solved by the present invention is the creation of a semiconductor memory including a data forwarding scheme to ensure recovery and data transfer, operating with high speed data transfer, and containing at least two >/P>In accordance with the first aspect of the present invention a semiconductor memory formed on a semiconductor chip having different operating modes, includes input address of the device for receiving external address indicating at least one of the working modes of the crystal, the device for generating the control signal mode setting for the operation mode setting and the memory device codes based on the external address in accordance with a control signal installation code and signal operation mode representing the operating mode defined by these codes.

In accordance with another aspect of the present invention a semiconductor memory having multiple operating modes, includes a device for forming a signal exceeding the capacity of the power source a predetermined level, and an automatic device for storing the set of code signals in accordance with the specified signal is exceeded, and forming an internal signal operation mode indicating the internal operating modes defined code signals.

In accordance with another aspect of the present invention dinamicamente memory cells and acts either in the active cycle, denoting the scan cycle, or loop through the records, or regeneration;

the device for receiving the gate signal line addresses and commit logic level gate signal of row address in response to the front or rear edge of the clock;

the input address of the device for receiving the generated outside of addresses selected one of the memory banks;

and device for:

receive fixed logic level signal from the device for receiving and fixing;

receiving the address from the input address.

output enable signal to the memory Bank selected by the address signal and omissions to the unselected memory banks, when fixed logic level equal to the first level, so that the selected memory Bank responsive to the activation signal, operates in an active cycle, while the unselected memory banks responsive to the signals of inactivity, work in regeneration.

In accordance with another aspect of the present invention a semiconductor memory formed on the semiconductor chip, receiving an external clock pulse and outputs the data read from the memory cells via the buffer device output, VK is synchronous with the clock using the buffer output device data over a time interval, corresponding to the signal length of the package.

In accordance with another aspect of the present invention a semiconductor memory includes a matrix of memory cells consisting of a set of memory cells grouped in rows and columns. Many submetric obtained by dividing a matrix of memory cells in the row direction, and each submarine has many dictionary tires attached to the respective columns of memory cells and a lot bit buses connected respectively to corresponding rows of memory cells. Bit bus each submatrices divided into a first bit group of the tire and the second group of bit buses, which are respectively divided into a first subgroup bit of tyre and second subgroups bit buses. The first group each submatrices alternate with the second group, resulting in the first subgroup of each submatrices alternate with the second subgroups and the resulting line input/output (1/0) are respectively parallel to the dictionary buses between submatrices on their outer sides. These highways are divided into the first 1/0 line and the second 1/0 highway, located respectively at odd and even positions. Each 1/0 highway tstone are connected using switches column selection bit with the tyres in the first and second subgroups of the first group of adjacent submetric. The first and second 1/0 bus second 1/0 highways respectively connected by means of a key column selection bit with the tyres in the first and second subgroups of the second group of neighboring submetric.

Hereinafter the invention is explained in the description of specific examples of its implementation and the accompanying drawings, in which

Fig.1 depicts the arrangement of figures 1a and 1b, which represent the various components formed on the same semiconductor chip, synchronous DRAM in accordance with the present invention.

Fig.2 is a diagram showing the organization of the relationship one of submetric in Fig.1 with the United with her tire pairs 1/0.

Fig.3 is a block diagram of the device control lines in accordance with the present invention.

Fig. 4 is a block diagram of the control device of columns in accordance with the present invention.

Fig. 5a and 5b are timing diagrams showing various commands used in the processing of the front and the signal level, respectively.

Fig.6 is a circuit buffer device clock (CLK) in accordance with izaberete the present invention.

Fig.8 represents a timing diagram CLK and CKE buffer, respectively, shown in Fig.6 and 7.

Fig. 9 is a diagram of the multifunction input buffer pulse in accordance with the present invention.

Fig.10 represents a timing diagram of control signals and column pulses used in the present invention.

Fig.11 is a diagram of a generator of high frequency clock pulses to generate a number of clock recovery in accordance with the present invention.

Fig.12 represents a diagram of the buffer column address in accordance with the present invention.

Fig.13 is a block diagram of the device installation operating mode in accordance with the present invention.

Fig. 14 is a diagram of the device generating the control signal mode setting for the circuit in Fig.13.

Fig.15a-15c are schematic code register address in Fig.13.

Fig. 16 is a diagram of the logical unit delay Fig. 13.

Fig. 17 is a diagram of the logical unit length of the package in Fig.13.

tvii with the present invention.

Fig. 19 is a diagram of the device generating the main line sync pulse to generate a main line sync pulse Ri in accordance with the present invention.

Fig. 20 represents a timing diagram showing the temporal relationship installation mode and autoregeneration in accordance with the present invention.

Fig. 21 is a diagram of a device for generating signals that allow the generation of control signals columns.

Fig.22 represents a timing diagram of the generator of high frequency clock pulses in Fig.11.

Fig. 23 is a block diagram of the data flows associated with one of the highways of the data in accordance with the present invention.

Fig. 24 is a diagram of a device for 1/0 regeneration and selection in accordance with the present invention.

Fig. 25 is a diagram of the output data multiplexer in accordance with the present invention.

Fig.26 is a diagram of the output data buffer in accordance with the present invention.

Fig. 27 is a detailed diagram of the input demultiplexer analnogo input/output (PIO) in accordance with the present invention.

Fig. 29 is a diagram of a buffer in accordance with the present invention.

Fig. 30 is a diagram of the buffer recording resolution in accordance with the present invention.

Fig.31 is a circuit DQM (dynamic memory) buffer in accordance with the present invention.

Fig.32 represents a timing diagram illustrating operation DQM buffer in Fig.31.

Fig. 33, consisting of Fig.33a-33c, are a timing diagram illustrating a write operation, in accordance with the present invention.

Fig. 34 is a diagram of the buffer column address in accordance with the present invention.

Fig.35 is a diagram of the address counter column in accordance with the present invention.

Fig. 36a is a diagram of each discharge, forming a first counting unit of Fig.35.

Fig. 36b is a diagram of each discharge, forming a second counting unit of Fig.33.

Fig. 37 represents a timing diagram illustrating the operation of the circuit of Fig.36a.

Fig. 38 is a diagram of the column decoder in accordance with the present invention is a scheme of the second predesignate in Fig.38.

Fig. 40 is a diagram of one of the main decoders in Fig. 38.

Fig. 41, including 41a-41c is a timing diagram illustrating a read operation in accordance with the present invention.

Fig.42 and 43 is a schematic of the device determine the length of the package in Fig.4.

Fig.44 is a diagram of the signal generator to reset the address column in Fig.4.

Fig. 45 is a diagram of the control counter forward in Fig. 4.

Fig.46 is a diagram of the clock generator for sending read data.

Fig. 47 is a diagram of the device generating the signal CL used in the multiplexer output data in Fig.25.

Fig. 48 is a diagram of the clock generator to transmit the recorded data in Fig.4.

Fig. 49, consisting of 49a-49c, is a timing diagram of a write operation is interrupted by a signal in accordance with the present invention.

Fig.50 is a diagram of a device generating control signals, regenerating 1/0 bus and P10 bus in accordance with the present invention.

Fig.51 predstava) bus in accordance with the present invention.

Fig. 52 is a diagram of a device for generating signals select the Bank to be used in the driver P10 tire of Fig.28.

Fig. 53 is a diagram of a control device for generating control signals used in the output data buffer of Fig.26.

Fig. 54-57 are timing diagrams illustrating the temporal relationships in different working modes in the synchronous DRAM using a pulsed RAS signal.

Fig. 58 is a diagram of a buffer using level signal.

Fig.59, a,b is a diagram of a special address buffers in accordance with the present invention.

Fig. 60 is a control unit for generating the main synchronous setup mode and main clock recovery, which is used in level

Fig. 61 represents a timing diagram illustrating the temporal relationships in the synchronous DRAM using level signals.

Fig.62 is a diagram showing how United the fragments of the drawings figures 1a and 1b, figures 33a-33c, the figures 41a-41c and the figures 49a-49c.

Preferable in mind, what in the drawings, similar elements are represented by the same symbols and designations where possible. In the following description numerous individual parts are numbered the same as the number of memory cells of the matrix of memory elements or memory banks, individual potentials of individual parts or elements, circuits, etc. in order to ensure full understanding of the present invention. For those who are expert in this field, it will be obvious that the invention can be implemented without these specific details.

Synchronous DRAM in this preferred embodiment, the implementation is based on the use of dual CMOS (CMOS) technology and uses an n-channel MOS (MOS) transistors having a threshold voltage from 0.6 to 0.65, p-channel MOS transistors having a threshold voltage from -0.8 to -0.85 In and the supply voltage Vccof approximately 3.3 Century.

The architecture of the crystal

Please refer to Fig.1, consisting of Fig. 1a and 1b, which illustrates the various groups of elements arranged on the same semiconductor chip synchronous DRAM in accordance with the present invention. DRAM in this implementation represents 16777216-bit (16 - as shown respectively in figures 1a and 1b, to increase the speed of data transmission. Each Bank consists of the upper matrix of memory cells 16T and the bottom of the matrix of memory cells 16B, located respectively in the upper and lower parts, each of which contains 4194304-bit memory cells (Mbit). The top and bottom of the matrix of memory cells are divided respectively by the left matrix of memory cells is 20tl and 20BL and right matrix of memory cells 20TR and 20BR, 2 Mbits of memory cells, each touching the sides. On the left and right matrix of memory cells of the upper matrix of memory cells 16T each Bank will respectively be referred to as the upper-left matrix of memory cells, or the first matrix of memory cells is 20tl, and on the top right of the matrix of memory cells, or a third matrix of memory cells, 20TR. Also, we will refer to the first and right matrix of memory cells of the lower matrix of memory cells 16B of each of the Bank as on the lower left of the matrix of memory cells or the second matrix memory cells 20BL, and on the lower left of the matrix of memory cells, or the fourth matrix of memory cells 20BR. Thus, each Bank is divided into four matrix of memory cells, containing from the first to the fourth matrix of memory cells. The upper left and right matrix of memory cells and lower left and right matrix of memory cells on 22TL8, eight top right submetric memory cells (or upper right submetric) 22TR1 on 22TR8, eight bottom-left submetric memory cells (or bottom-left submetric) 22BL1 on 22BL8 and eight lower right submetric memory cells (right or bottom-right of submetric) 22BR1 on 22BR8. Each submetric has 256K-bit memory cells arranged in matrix form 256 rows and 1024 columns. Each memory cell is a transistor odnokomnatruyu cell of known type.

In each Bank line decoder 18 is installed between the upper matrix of memory cells 16T and the bottom matrix of memory cells 16B. Line decoder 18 of each Bank is connected to 256 lowercase tires (dictionary tyres) each submarine. Dictionary tires corresponding matrix of the upper and lower pairs of submetric 22TL1, 22BL1; 22TL2, 22BL2;...; 22TR8, 22BR8 arranged symmetrically with respect to the outputs of the row decoder 18, diverge parallel to each other in opposite directions vertically. Line decoder 18, which responds to lowercase address buffer row address selects one of submetric relevant matrices (from the first to the fourth matrix of memory cells) and from the dictionary of tyres in the selected submatrices, and delivers the line at the Troc in each Bank line decoder 18 selects four simultaneously dictionary tires, one word bus is selected in one of the selected top left submetric 22TL1-22TL8, another dictionary bus is selected in one of the selected bottom-left submetric 22BL1-22BL8, the third dictionary bus is selected in one of the selected top right submetric 22TR1-22TR8 and the last dictionary bus is selected in one of the selected lower right submetric 22BR1-22BR8.

The column decoders 24 are adjacent respectively to the right edges of the upper and lower matrices of memory cells 16T and 16B in the first Bank 12, and the left edges of the upper and lower matrices of memory cells 16T and 16B in the second Bank 14. Each of the column decoders 24 is connected to a 256 bus sample columns, which are directed horizontally and perpendicular dictionary tires, and these decoders are used for sample one of the tires of the columns in accordance with the column address.

1/0 line 26 adjacent to both edges of the respective submetric 22TL, 22BL, 22TR and 22BR, breaking parallel dictionary tires. 1/0 line 26 connecting the opposite edge of submetric shared these two adjacent submatrices. Each of 1/0 highways 26 consists of four pairs 1/0 tire, and each pair, which consists of two signal complementary tires, connected to what I consider now Fig.2, which illustrates one of the odd submetric with 22TL1 on 22TL8 in the upper matrix of memory cells 16T and the 1/0 lines, which corresponds to it. The first, or left, 1/0 line 26L and the second, or right, 1/0 line 26R, respectively, are parallel dictionary tires WL0-WL225 on the left and right edges of submatrices 22. Each of the first and second 1/0 highways 26L and 26R consists of a first pair 1/0 tires, which consists of pairs 1/00, 1/01, and the second 1/0 pair, which consists of pairs 1/02, 1/03 Submatrices 22 contains a 1024-bit bus pairs 28, perpendicular dictionary tires WL0-WL255, which are arranged in the form of a folded bit of tyres. Memory cell 30 is located at the intersection of vocabulary and bit buses. A pair of bit buses 28, suitable to submatrices 22, divided into many groups based tire 28L1 on 28L256 located in odd places, and many of the second group bit buses with 28R1 on 28R256 installed on even ground. Each of the bit groups of the tires has given her a number of pairs of bit buses (two pairs of bit buses in this implementation). The first group bit tires 28L alternate with the second group bit buses 28R. Odd pairs of bit buses (or the first subgroup) 28L1, 28L3,..., 28L255 and even a pair of bit is m and the second 1/0 pairs of tyres in the first 1/0 line 26L using the corresponding read amplifier 32L and key column selection 34L. In the same way, an odd pair of bit buses (or the first subgroup) 28R1, 28R3,..., 28R255 and even a pair of bit buses (or the second subgroup) 28R2, 28R4,..., 28R256 second groups of bit DIN 28R are connected respectively with the first pairs 1/0 tires and second pairs 1/0 tyres second 1/0 26R line with appropriate amplifiers 32R and keys select columns 34R. The first bus select columns L0, L2, . . . and L254, which are connected with the keys of the select columns associated with the first pairs 1/0 tire 1/00, 1/01, in the left and right 1/0 lines 26L and 26R, parallel, alternating with the second tire choice columns L1, L3, . . ., L255, which is connected to the keys of column selection associated with the second 1/0 pairs of tires 1/02, 1/03, Therefore, when a read operation, after selecting one of the dictionary of the tire, that is, one page with the address lines, the first and second pairs 1/0 tire in the left and right 1/0 lines 26L and 26B give continuous data, alternating extradition case of double-bit data with sequential sampling tyre selection of columns from L0 to L255. Tire pair 36, which are connected to respective amplifiers read 32L and 32R and extend alternately in opposite directions associated with the respective bit groups of tires 28L and 28R using sootvetstvuyu 1/0 bus pair and the second 1/0 bus couples the first 1/0 line 26L are connected respectively with the odd bit pairs of tires (or the first subgroups) and the even-numbered pairs of bit buses (or second subgroups) of the first group bit buses left adjacent submatrices (not shown) using the corresponding keys select columns 32L and the corresponding read amplifiers. In the same way the first couple 1/0 tire and the second pair 1/0 tyres second 1/0 line 26R respectively connected to odd bit pairs of tires (or first sub-groups) and the even-numbered bit pairs of tires (or the second sub-groups) of the second group bit buses right adjacent submatrices (not shown) using the keys select columns 32R and the corresponding read amplifiers. Thus, as the bit pair of tires of the respective submetric divided in the same manner as the first and second bit group bus submatrices 22, as shown in figure 2, 1/0 line associated with the first group bit buses, alternate with 1/0 routes associated with the second bit groups of the tires. Thus, each of the first 1/0 highways located in odd places, connected with the first bit group of tires in two adjacent submatrices, while each of the second 1/0 highways located on even ground, is connected with the second bit groups of the tire adjacent submatrices. With regard to the relevant submetric in Fig.1, their communication with the first and second pairs 1/0 tires first and second 1/0 highways will be included in the consideration in the explanation that will be given in connection with Fig 2. As the amplifier read 32L or 3O transfer transistors, N-channel amplifier, reading and balancing schemes and regeneration. Thus 1/0 highway 26 between two adjacent submatrices are common 1/0 highways to read and write data from/to summarize, which is selected under the control of the separating transistors of the transfer.

Let us return to Fig.1. Every Bank in the upper part of the first and second arrays of memory cells is 20tl and 20TR placed accordingly, the device of choice 1/0 bus and regeneration 38TL and 38TR amplifiers read 1/0 and bus drivers 40TL and 40TR, United appropriately, and similarly, in the lower part of the second and fourth matrices of memory cells 20BL and 20BR placed accordingly, the device of choice 1/0 bus and regeneration 38BL and 38BR amplifiers read 1/0 and bus drivers 40BL and 40BR, United appropriately. Device select 1/0 tires and regeneration 38TL, 38TR, 38BL and 38BR respectively connected to the alternating 1/0 highways 26 in the respective matrices of memory cells is 20tl, 20TR, 20BL and 20BR. Thus the device of choice 1/0 tires and regeneration, located in odd places, connected respectively with pairs 1/0 highways posted at odd places in the respective matrices of memory cells and devices choice of tires 1/0 and Regener is the shaft in relevant matrices of memory cells. Therefore, in each Bank, each of the devices located on the edge of the device select 1/0 tires and regeneration, can have access to the data in the memory cells connected with the first bit groups of the tires in third submatrix, and even located the device select 1/0 tires and regeneration, and even located the device select 1/0 tires and regeneration, eliminating located on the edge of the device select 1/0 tires and regeneration, associated respectively with the first bit groups of tires and second groups of bit buses. Each of the devices of choice 1/0 tires and regeneration 38 consists of a device select 1/0 line for selecting one of the pair attached 1/0 highways and devices regeneration 1/0 tires for the regeneration of the other pair 1/0 tires, when any of the first 1/0 wine pairs 1/00, 1/01, and second 1/0 bus pairs 1/02, 1/03, forming a selected 1/0 line, transmits the data.

Device select 1/0 tires and regeneration 38 are connected respectively to amplifiers read 1/0 and bus drivers 40 through P10 highways 44. Each P10 line 44 is connected with the 1/0 line, selected the appropriate device select 1/0 highway. Thus P10 highway 44 consist of four pairs P10 tire analogichnaya input data using the appropriate device select 1/0 highway and P10 line in a read operation, and the bus driver to control 1/0 line input, selected by the device selection 1/0 line using the appropriate device select 1/0 highway and P10 line in a write operation. Thus, as described above, if the data on any of the first or second bus pairs are entered in the read amplifier via respective P10 tire pair, P10 tire pair associated with other 1/0 bus pairs, regenerated together with the 1/0 bus pairs. In addition, in a write operation, when the driver 40 sends the data to the appropriate 1/0 bus through selected pairs P10 tire pair, unselected P10 bus pair and the corresponding 1/0 bus pairs begin to regenerate.

To the top and bottom edges of the crystal synchronous DRAM come running horizontally, respectively, the top line data 42T and the lower line data 42B. Each of the upper highways data 42T and lower routes data 42B consists of four main roads data, each of which, in turn, consists of four pairs of data bus, which have the same number as the above-mentioned 1/0 highway and P10 highway. One ends of the four routes data DB0-DB3, forming the top line data 42T, and four mages/output data 46, which are connected with the contacts I/o (not shown), by means of bus I/o 47 and buffers input/output data 48.

In each Bank amplifiers read 1/0 and bus drivers 40TL associated with the first matrix of memory cells is 20tl, connected serially with the first and second routes data DB0 and DB1, and amplifiers read 1/0 and bus drivers 40TR associated with the third matrix memory cells 20TR, serially connected with the third and fourth lines DB2 and DB3. Similarly, the amplifiers read 1/0 and bus drivers 40BL associated with the second matrix memory cells 20BL, serially connected with the fifth and sixth lines of data DB4 and DB5, and amplifiers read 1/0 and bus drivers 40BR associated with the fourth matrix of memory cells 20BR, serially connected with the seventh and eighth lines of data. Central amplifiers read 1/0 and drivers 43T and 43B are connected respectively to 1/0 highways between the first matrix of memory cells 20TR and the third matrix memory cells 20TR and between the second matrix memory cells 20BL and a fourth matrix of memory cells 20BR each Bank. In each Bank Central power reading of 1/0 and a bus driver 43T in the upper part consist of amplifier read 1/0 to enhance data Souverain reading and the bus driver for directions data line DB1 or DB3 on the 1/0 line in response to the control signal in a write operation. Similarly, the Central power reading of 1/0 and a bus driver 43 in the lower part is connected to the fourth and eighth highways data DB5 and DB7.

Now suppose that submatrices 22TL3, 22BL3, 22TR3 and 22BR3 at the first Bank 12 and one word bus in the relevant submatrices selected string decoder 18 in response to the row address. Then line decoder 18 generates a signal block information denoting the corresponding submatrices 22TL3, 22BL3, 22TR3 and 22BR3. Then, in the read operation, the control unit, as will be discussed below, generate consecutive addresses of the columns in response to an external address column, and the column decoder 24 generates a serial column selection signals in response to this thread addresses column. Assuming that the first signal of the column selection must select bus select column L0, then opens the appropriate selection key columns 34, shown in Fig.2, and the data collected on the respective pairs of bit buses will be forwarded to the tire pairs 1/00, 1/01, left and right 1/0 highways located on both edges of soybean signals block information, and device selection 1/0 tires and regeneration associated with the selected submatrices 22TL3, 22BL3, 22TR3 and 22BR3, is chosen so the associated left and right 1/0 highway. Data on the first pairs 1/0 tire in the left and right 1/0 highways are forwarded to the appropriate bus pairs of corresponding routes data DB0-DB7 through respective pairs P10 tire and the corresponding read amplifiers included in the control signal, which is generated in response to a signal block of information. However, at this time, the pair 1/0 tires, but the forwarding data, that is, the second pair 1/0 tire and connected pairs P10 tyres are kept in a state of regeneration through devices 1/0 regeneration. Also, pairs of data bus, nepereslushat data regenerated by the multiplexers of the input/output data 46, as will be explained below. Then, if the second signal of the column selection CSL1 on the bus column L1 address flow columns corresponding keys of the column selection is enabled in the same manner as discussed above, the data on the corresponding bit of the tire is transmitted through the second pair 1/0 tire in the left and right 1/0 highways and through corresponding pairs P10 tire of the pairs of data bus, while the connected first 1/0 bus pairs,samples with CSL2 on CSL255 tires columns L2 on L255, following the column selection signal CSL1 on the bus column L1, are consistently taken, such as sending data, if the column selection signals CSL0 and CSL1 again. Thus, all data on the pairs of bit buses, which were formed from all memory cells associated with the selected dictionary tires, can be read.

Thus, the page is read. In reading the first couple 1/0 tire and the second pair 1/0 tires send a lot of data, alternating between the data transfer and regeneration, and the first and second pairs of data bus associated with the first and second pairs 1/0 tires periodically repeat the data transfer and regeneration. The multiplexer output is connected to each line of data, not only stores a lot of data transmitted in parallel by using any one of the first or second pairs of data bus, but also regenerates other pairs of data bus. Thus, each multiplexer output data continuously generates serial data in response to the selection signals data, pre-selecting data of the first or second pairs of data bus with the specified period. Serial data is output with the corresponding in the 8-bit parallel data is continuously output in each cycle of the clock.

A write operation is performed in reverse order with respect to read operations, discussed above. As will be briefly explained, the serial input data is output synchronously with the system clock from the input data buffers through a rolling contact data. Serial data from the input buffers of data are sent alternately to the first and second pairs of data bus corresponding data highways, in the form of multiple parallel data with each cycle of the system clock using the appropriate demultiplexes the input data. Data on the first and second pairs of data bus sequentially written into the selected memory cell via the corresponding bus drivers, 1/0 routes selected by the device selection 1/0 tires, and the respective pairs of bit buses. Data transmission and regeneration of first and second pairs of tires alternately performed in each cycle of the sync pulse in the same manner as in the read operation.

Between the first and second banks is set, the control unit 50 to control the operation of the synchronous DRAM in accordance with the present invention. The control unit 50 serves to generate control sync is the generation of 38, amplifiers read 1/0 and bus drivers 40 and 43, the multiplexer input/output data buffers 46 and input/output data 48. The control device 50 may be regarded as a device of control lines and the control unit columns. The device management data lines, the data path and the control unit columns will be described below.

The device control strings.

Well-known DRAM activated to perform operations of reading, writing, etc. logic level such as a low level. Referring to this, we will use the term "level ". The level has some information, for example, switching from high to low indicates an active state, and switching from low to high indicates regeneration. However, since synchronous DRAM must operate synchronously with the system clock, the above commands used in known DRAM cannot be used in a synchronous DRAM. Thus, as for synchronous DRAM, you must choose the command information on the leading or trailing edge of the system clock (sampling command information in this implementation is to be used.

In Fig. 5a and 5b are shown timing diagrams of the commands used in the synchronous DRAM described in the present invention. Fig.5a represents a different command for the case when used as a pulse signal (hereinafter called pulse , and Fig.5 represents various commands for use case level As can be seen from the drawings, when the low level and the enable signal recording have a high level at the time of the leading edge of the system clock CLK, it means the active state (activation). After activation at the time of the leading edge of the system clock high-level low and a high level indicates a read command. After activation, at the time of the leading edge of the system clock CLK, high-low and low is a write command. When set low level to the high level and low level at the time of the leading edge of the clock CLK, the operation of regeneration. The command to set the operating mode in accordance with features of the present invention is set at a low level at the time of the leading edge of the clock CLK. - before (CBR) updates the input commands, when kept at low levels, and WE is a variation of the CBP recovery when they are at low levels, and WE on high for three consecutive edges of the clock CLK.

Similarly, as in the well-known DRAM, synchronous DRAM has a time period between activation and activation of the time delay and the period of regeneration, prior to activation, that is, the regeneration time For

to guarantee the correctness of the data when reading and writing, for developers of systems of memory is the minimum value (respectively 20 NS and 30 NS in the synchronous DRAM of the present invention). For the greater convenience of the developers of the systems, it is preferable that the minimum value was set by a number of clock cycles of the system clock. For example, in the case where the frequency of the system clock is equal to 100 MHzand the minimum values respectively equal to 20 NS and 30 NS, then expressed in clock cycles will be respectively equal to 2 and 3. Device control string is a means to generate signals or clock pulses for selecting dictionary tires for time tRCDby filing for bit data bus of the memory cells for a read operation and implementation of regeneration during the times of the Referring to the drawing, note that the buffer clock (hereinafter called CLK buffer) 52 is a buffer for converting the external system clock CLK TTL level (TTL) in the internal system clock pulse level CMOS (CMOS). Synchronous DRAM performs various internal operations to select the signals from the external crystal or send data to an external crystal at the time of the leading edge of the clock CLK. CLK buffer 52 generates a clock pulse CLKA faster than to change the phase of the CLK caused it.

Buffer resolution sync (CKE) 54 is a device for generating a signal masking sync pulse in order to mask the generation of a sync pulse in response to an external enable signal of the clock CKE and the clock CLKA. As will be discussed below, the internal system clock pulse is prohibited signal will cause the operation of "freezing" the internal operations of the crystal, and the input and output data through this, you will be blocked. the buffer 56 receives an external signal, the address signals SRA10 and SRA11, the signal buffer signal buffer, thus generating the sync pulse for selective activation banks synchronously with a sync pulse to selectively or completely regeneris the scrap i marked the Bank. The buffer 56 generates a signal RPthat activates on sync

Device installation operating mode 58 responds to the command to set the operating mode, signals and address signals RA0-RA6, in order to set the different operating modes, for example, operating modes to set the delay for packet length representing the number of continuous output, and the address mode representing the encrypted internal address column. The device operating mode setting sets the default operating mode in which a predetermined delay is the length of the packet and the address mode is automatically selected if there is no command to set the working mode.

Generator main clock line 62 responds to the control signal and the delayed signal CLj and generates the main clock pulse line which is formed in the generation of synchronizing pulses or signals associated with the circuit in the selected Bank. In accordance with features of the present invention, the main clock pulse line has a time delay that depends on the delay value which ensures the case of double-bit output data synchronously with the system clock after regeneration.

The generator control signal line 64 receives the main clock pulse line and a signal block of information from BLS row decoder 18 for generating an additional control signal dictionary tiresXstarting signal reading Sto activate the selected amplifier readout, the reset signal of row address for resetting the buffer row address signal a RALto actuate the buffer address column 344 and signal for informing of the completion of the synchronizing pulses or signals related to strings.

Generator resolution sync columns 66 receives the signal and the main clock pulse line in order to generate signals for the resolution of devices connected to the columns.

High-frequency master clock oscillator 68, in the case when the frequency of the external system clock CLK is low, and you want to output case of double-bit data read operations after regeneration, generates a clock pulse CNTCLK9 with greater frequency than the frequency of the clock CLK, in order to prevent decrease in the regeneration. As will be obsada regeneration will be prevented.

Below is given a detailed explanation on the preferred options for the implementation of elements constituting the clock generator circuit.

1. CLK CKE buffer and the buffer

In Fig. 6 presents a diagram CLK buffer 52, and Fig.7 diagram CKE buffer 54 in accordance with the present invention. In Fig.8 shows a time chart for a CLK buffer 52 and CKE buffer 54.

Let us consider Fig. 6. Differential amplifier 70 compares the external system clock pulse CLK from the reference voltage Vref(= 1.8 V) and thus converts the external signal CLK TTL level into the internal signal level CMOS, for example, high level 3 / low 0 Century. Instead of the differential amplifier 70 is possible to use other input buffers that can carry the TTL level signal at CMOS signal. As can be seen in Fig. 8, the clock pulse CLKA is obtained by inverting the system clock CLK by using the input buffer 70, such as a differential amplifier, and logic elements that is using inverters 76 and logic gate NAND (AND NOT) 78. The trigger or latch 80, which consists of logic elements NOP (OR NOT) 72 and 74, generates the system clock to the CMOS level, when the signal mask clock nestoit from the delay circuit 82 and a logical element AND-NOT 84. Although the delay circuit 82, for simplicity, shows only the inverters may be used in the schema that contains the inverter and the capacitor or other means of delay. Thus, when the signal is low from CLK buffer output internal system clock pulse as shown in Fig.8. However, when the signal is high, the signal at the output of the trigger 80 becomes low, in order to stop the generation of the sync pulse In Fig. 6, the inverter 89, p-channel MOS transistor 90 and the n-channel MOS transistors 91 and 94 are designed to allow installation of the initial state for the respective modes in response to the signal power from the known device power-up. The signal power is kept at a low level as long as the supply voltage Vccwill not reach the required level after the supply voltage.

Let us consider Fig. 7. The input buffer 70 converts the enable signal of the external clock CKE signal of CMOS level. To reduce the power consumption, the operation of the input buffer 70 is prohibited by operation of self-healing. The input buffer 70 generates inverted relative to the signal CKE, CMOS signal levels on the bus 90. The inverted signal CKE is served on shear reg is 86 connected to the signal output through trigger 88 on the items OR NOT and inverter. The output of the shift register 86 is connected to the signal output CKEBPU through inverters.

The enable signal of the clock CKE prohibits generate a system clock with a low level CKE to freeze the inner workings of the crystal. Refer again to Fig.8. Illustration made for signal CKE low pulse for masking the clock CLK 98. Using low level signal CKE input bus 90 shift register 86 maintains a high level signal. After clock pulse CLKA 100 goes low, the output of the shift register 86 goes to a high level. Thus CKEBPU become signals with high and low levels, respectively. Then, after the next clock pulse CLKA 102 goes low, the output of the shift register 86 is changed to low level, thus causing the signal CKEBPU move on to a higher level. At this time, since the output of the trigger 88 is kept at a low level, the signal is maintained at a high level. However, after the next clock pulse CLKA 104 goes to a high level, the signal goes to a low level. Thus, as discussed in connection with Fig.6, the sync pulse associated with a sync pulse t synchronously with the clock masking translates the internal operation in the idle state. Thus, to prevent unnecessary power consumption in the standby state, the signal CKEBPU is used to prevent synchronization of the input buffers the signal, Respectively, should be taken into account that the signal CKE must be submitted at least one cycle of the masked clock CLK to premasiroval, and must maintain a high level to perform a normal operation.

2. buffer

Synchronous DRAM includes two memory Bank 12 and 14 on the same chip to achieve high-speed data transfer. To achieve high performance synchronous DRAM required control device that selectively control the various operations in each Bank. Accordingly, the buffer is an input buffer that performs many functions in accordance with features of the present invention.

In Fig. 9 presents a diagram showing the multi-function input buffer pulse in accordance with the present invention. Please refer to Fig. 9. Similarly, as discussed above, the input buffer 70 translates the external gate signal line address in the internal signal of the CMOS level. The input buffer 70 is blocked key circuit 106 to switch maskirovany the first buffer 70 is connected to the input 110 of the synchronization device 108 to provide output 112 pulse which synchronizes the signal CMOS level with the internal system clock So as shown in Fig.10, in the moments of the signal are at a low level, and generates a pulse with a high level after a predetermined delay at the output 112.

In Fig. 9 the remainder of the device, excluding the input buffer 70, a synchronisation unit 108 and the core circuit 106, is a multifunctional control device 114, intended to control the respective banks. Since n-channel transistors 148 and 150 is enabled by the signal being at a low level at the time of turning on the supply voltage, the first clock pulse to the first Bank 12 and the second clock pulse for the second Bank 14 is fixed both in the initial conditions, i.e. at low levels using latches 154 and 156.

For activation of the first Bank 12 and simultaneous deactivation of the second Bank 14 at the time as shown in Fig.10, the external address signal ADD, together with the address of the A11, which is at a low level, is applied to the crystal. Then, the address buffer, as will be discussed below, generates an address signal SRA11 low level ( high level) to the address signal ADD. On the other hand, in the moment

time t1because both signals are kept at a high level, keep a low level, as will be discussed next. So Ob level. Then, the logical elements AND NOT 128 and 130 generate high and low level, respectively. When the pulse goes to a high level, the logical element AND-NOT 132 goes to a low level, and the logical elements AND NOT from 134 to 138 at a high level. Then p-channel transistor 140 is opened, and the p-channel transistor 144 and n-channel transistors 142 and 146 remain off. Thus, the latch 154 maintains a low level. On the other hand, when it goes to low level, all the logical elements AND NOT from 132 to 138 are transferred at a high level, thereby turning off the transistors 140 and 146. In the result, the first clock pulse goes to a high level, and the second clock pulse maintains a low level by the latch 156, which initially retains a high level. Thus, the first Bank 12 is activated by the sync pulse by performing normal operations, such as read or write. The second Bank 14 is active low pulse

On the other hand, to access synchronous DRAM with high-speed data transmission, the second Bank can be activated during activation of the first Bank. This can be done by activation of the second Bank, feeding AA high level (PA11 goes to the low level). In the same way as described above, the logical element AND-NOT 136 generates a low level, and all logical elements AND 132, 134 and 138 generates a high level. Thus is maintained in the previous state, i.e. at a high level, but goes to a high level. In the result both the first and second banks transformed into an active state.

During a read operation or write in the second Bank, the first Bank may also be regenerated. On or before issued by the regeneration team at the moment as shown in Fig.10, the external address signals A10 and A11 having a low level are fed to respective address terminals of the crystal. Then, the address signal SRA10 and SRA11 switched to the low level ( moves to the high level). After the command signals are transferred at a high level and at low level. Accordingly, when goes to a high level, the logical element AND-NOT 134 goes to a low level, and all elements AND NOT 132, 136 and 138 to hold a high level. Thus, the transistor 142 is opened and the transistors 140, 144 and 146 remain in the off state. The latch 154 retains a high level, but goes to a low level. However, is kept in the previous state at high pressure the time of making access to the data from the second Bank 14. Similarly, the regeneration operation of the second Bank may be performed by a team of regeneration, and the address signal A10 will be at a low level and the address signal A11 is at a high level.

On the other hand, the simultaneous regeneration operation of both the first and second banks 12 and 14 may be made by filing a team regeneration and low level address signal A10 regardless of the logic level of the address signal A11. Then, as described above, the logical elements AND 134 and 138 generates a low level, and the logical elements AND 132 and 136 generates a high level. Thus, the transistors 142 and 146 are included, and the transistors 140 and 144 are in the off state. As a result, the latches 154 and 156, while at a high level, respectively store information regeneration, and both signals are transferred to a lower level.

The restore command is published by the CBR signal being at a low level, and the signal being at a high level, as shown in Fig. 5a. Thus, a high signal and low level signal included in the multifunction control unit 114. In this case, the logical element AND-NOT 124 and logical-OR-NOT issue 126 low Nezavisimosty AND 134 and 138 generates a high level. Thus, transistors 140 and 144 is on, and the transistors 142 and 146 are turned off. Then, the signals become high level, but both of the Bank, thus, perform the restore operation CBR. On the other hand, the selective restore operation CBR for both banks can be accomplished by grounding one of the two inputs of the logical element AND-NOT 124. Then, also as discussed above, the signals can be selectively enabled in accordance with the logic state of the address A11. That is, the low level address A11 when the restore command CBR forces to recover only the first Bank.

3. The buffer line address

In Fig.12 shows a diagram of a device buffer line address 60 in accordance with the present invention. In the illustration, the input buffer 70 translates the input address signal AI (I= 0, 1, 2,..., 11) in the address signal of the CMOS level in the same manner as described in connection with the above input buffers. Logical device 158, designed to generate the control signal RABPU permission or prohibition of the operation of the input buffer 70, also shown in Fig.12. The control signal RABPU becomes high level when activated, both of the Bank or the transaction is authorized maskirovanija to prevent the power consumption. Between the output 161 of the input buffer and the node 162 is connected inverter with three-state 160. The inverter 160 takes the off state when a low level signal recovery during the recovery operation. In normal operation, such as read or write, the inverter 160 outputs a signal of row address, synchronized with the internal system clock Signal line addresses stored in the latch 164. Many devices issuance of row addresses, the number of which is determined by each Bank is connected to the node 166. From the fact that in the proposed implementation of the present invention uses two banks, it is necessary that the device issuing the string address 168 and 170 must be connected in parallel to node 166. The device issuing addresses 168 for the first Bank 12 consists of a logical element OR NOT 174, inverters 176 and 180, the transmit key 172, latches 178 and keys 182 and 184. The device issuing addresses 170 for the second Bank 14 has the same structure as the device issuing the string address 168. The device issuing addresses recovery 198 is connected to the devices 168 and 170 and serves to ensure that the device issuing addresses 168 and 170 value content RCN T1 counter recovery (not shown) in the operation vosstanovlena the progress of the operation read or write. In this case, the line clock pulse of the first Bank and a reset signal line of the address of the first Bank were at a low level, and the main clock pulse line address of the second Bank and a reset signal line of the second Bank at a high level. Suppose further that the first Bank is activated at the moment as shown in figure 10. Then, before the sync pulse will switch to a high level, string address t external contact AI stored in the latch 164, as discussed previously, and line address stored in latch 178, through the transmit key 172 opens the low level signals But in this case, since the sync pulse is continuously remains at a high level, the transmit key 172' is held in the previous off state, thereby preventing forward through it stored lowercase addresses. When clock pulse will switch to a high level, the device issuing the string address 168 is disconnected from the output latch 164 using the key 172. When a reset signal line of the address of the first BankRAR1go to a high level, logical elements AND NOT 182 and 184 will issue data on the row address stored in the latch 178, and their amendments, sootvetstvenno the note, what, when and are at a high level, the control signal RABPU goes to a high level using logic circuits 158, thus disabling the input buffer 70, in order to prevent power consumption due to the active or normal operations of all the banks.

On the other hand, when the recovery operation, such as CBR or repair, signal recovery is low, andQUESTION OF HOWat a high level. In the case of a restore operation, two banks, and will be at a high level, as was found previously, and will also be at a high level, as will be explained in detail below in connection with figure 19. The signals will also be at a high level. Thus, the input buffer 70 and the inverter tristate 160 will be in the off position and at the same time the keys of the transmission 172, 172' and 194 will also be in the off state, while the keys of the transmission 188 and 188' is in an enabled state. Thus, the counting signal address RCNTI known address counter (not shown), which were stored in the latch 192, through the transmit key 194 included were low before the restore operation, will be sent to stronomy the decoder corresponding to each Bank through the keys of the transmission 188 and are made of the operation of the selection vocabulary tires each line decoder and then restore the memory cells.

For use in the multifunctional buffer as addresses SRA10 and SRAII you can take the address RA10 and RA11 from the buffer line address 60. However, because the address RA10 and RA11 are generated with some time delays, for independent generating addresses SRA10 and SRA11 on the same crystal can be used separate buffers lowercase addresses that can work with greater speed.

4. The device operating mode setting

In the present invention, the synchronous DRAM is designed so that the system developers choose the desired operating mode from several in order to increase usability and to expand the scope.

In Fig. 13 shows the block diagram of the device installation operating mode 58. In the drawing, the control signal generator set 200 generates the setting signal mode in response to a signal generated as a result of issuing the command to set the working mode.

Register address code 202, in response to the signal power from the device power-203 and the signal mode setting remembers the codes address MDST0 on MDST6, depending on the address buffer row address, and outputs the codes with MDST0 on MDST2 and MDST4 on MDST6 and Sirmium logical combination code with MDST0 on MDST2, where n represents the packet length expressed by the number of cycles of the system clock. Logical delay device 206 outputs a signal CLjgenerated by a logical combination of codes with MDST4 on MDST6, where j represents the value of the delay expressed in number of cycles of the system clock.

Fig. 14 is a diagram of oscillator control signals set the device 200, and figure 20 is a timing diagram reflecting the programming or setting the operating mode.

In this implementation, programming operating modes is carried out by obtaining the set operating mode and simultaneously addresses A0 through A7 input contacts addresses in accordance with table 1.

delay j, relative to the maximum frequency of the system clock, are presented in table 2.

As will be noted, the delay value j in the above tables is expressed by the number of cycles of the system clock, and the values of the delays with respect to the maximum frequency of the clock can be changed in accordance with the operating speed of the synchronous DRAM.

For example, if the system designer wants boscastle 100 MHz, the minimum delay value j is equal to 3. If the selected delay value equal to 3, the addresses A0 through A7 to install the operating modes will be: 1, 1, 0, 0, 1, 1, 0 and 0, respectively. As already mentioned, to select one of the two banks used the address A11. The logic levels of the other addresses it does not matter.

After selecting the operating modes suitable for data transmission systems, and determining addresses for setting operational modes, program mode synchronous DRAM by issuing the set mode and the pre-defined addresses on the corresponding pins of the crystal. Consider figure 20. The installation command mode and the address ADD received at time t1. Then buffer and signals the buffer and buffer, as will be discussed below, moving to a high level. In the generator control signals to set 200 shown in Fig.14, the signals having all the high level translated signal at a low level. When a reset signal line of the address goes to a high level, the buffer line address issues lowercase address on RA0 RA7. Therefore, all three inputs of the logical element AND-NOT 208 are transferred at a high level, thereby causing the ena 202. The code register address 202 consists of the first registers to save the second logic level (low level) signals power and addresses RA0, RA2 on RA4 and RA6, in the operation mode setting after power-on in response to the setting signal mode and the second registers to save the first logic level (high level) signal power and addresses RA1 and RA5, in the operation mode setting after power-on in response to the alarm setup mode, Each first register consists of inverter 210, having three States and consisting of p-channel MOS transistors 212 and 214 and the n-channel MOS transistors 216 and 218, the latch 222 connected to the output of inverter 210, and a p-channel MOS transistor 220, the channel of which is connected between the supply voltage Vccand the output and gate signal power As the signal power is low until the supply voltage Vcchave not reached the minimum capacity to ensure the proper internal functioning after power-up, each first register generates the appropriate address code MDST1 or signal addressing mode set at a low level on the enable signal: the RA 210', having three States and consisting of p-channel MOS transistors 212' and 214' and n-channel MOS transistor 216' and 218', and n-channel MOS transistor 219, whose channel is connected between the output of the inverter 210' and the reference potential (ground potential) and whose gate is supplied inverted signal and latches 222', connected to the output terminal of the inverter 210'. Each second register address code issues MDST1 or MDST5 fixed at a high level on the signal power. However, when the operation mode setting after power, that is, after the supply voltage Vccreaches at least the minimum operating voltage, because at a high level, the inverter 210 and 210' are enabled in response to the high level signal and then latches 222 and 222' store string address PAI from the buffer line address 60, thus throwing codes address MDST1, having also the same address value as lowercase address RA1. Thus, if you are running the setup mode, each address code MDST1 has the value of the corresponding address. MDST3 corresponding to the signal RA3 is a signal which represents the addressing mode of the columns. If A3 = 0 (low level), the signal goes to a low level and schroven), the signal goes to a high level, pointing to the alternate mode.

In Fig.16 shows a diagram of a logical unit delay 206, which selects only one of the signal delay

with CL1 through CL4 for translation at a high level, using a logical combination codes address MDST4 on MDST6 associated with a delay. The signal power only CL2 goes to a high level, because MDST5 is high and MDST4 and MDST6 low.

In Fig. 17 shows a diagram of a logical unit packet length 204 for selecting one of signals each of which represents the length of the package by using logical combinations of codes address MDST0 on MDST2 associated with the packet length. For example, if all the codes address MDST0 on MDST2 are at a high level, only the signal 512 of the signals is at a high level, and all signals SL24 on SL512 - high. Thus, as will be explained below, in response to these signals through the output buffer data is displayed 512-word block (full page). The signal power, only the signal SL4 and have a high level, and MDST0 and MDST2 low level.

Therefore, the selected operating modes are defined stored in the latches 222 and 222' corresponding address of the corresponding latches 222 and 222', operation of the circuit in accordance with a characteristic feature of the present invention. When performing high-speed regeneration without any special commands regeneration, the regeneration time is reduced, and the next, an active operation is performed immediately, eliminating the wait state.

In Fig.18 shows a diagram of oscillator control signal of autoregeneration 223, to perform autoregeneration output self-healing or setup mode. The signal self is at a high level during the operation of self-healing and low in the rest of the time, excluding the time of healing. Thus, the output of the logical element AND-NOT 224 is at a high level in the setup mode. WhenRARireaches a high level, as shown in figure 20, the output of the logical element OR NOT goes to the high level. At this time is low. Then when it goes to a high level, the output of the logical element AND-NOT 226 changes from low to high after a delay time determined by delay circuit 230. Therefore, the control signal generator of autoregeneration 223 verbatime the donkey perform self-healing goes from high to low, and then unit 223 generates a pulse signal autogeneration low level. Please refer to Fig. 9, where the signal is fed to the logical element AND-NOT 152. Thus the logical element AND-NOT 152 produces a short pulse of a high level when a short pulse of low level, thus including n-channel transistors 148 and 150. Then the latches 154 and 156 memorize a high level, forcing the move to a low level. Because or goes to low level, moving consistently at a low level, and then performs the regeneration operation.

On the other hand, if the synchronous DRAM of the present invention is used without the setup mode, i.e. in the default mode, p-channel transistors 220 and n-channel transistors 219, shown in Fig.15, includes a signal power which is low at power-up. Thus the latch 222 is kept low, and 222' high level. Then the codes address MDST0, MDST2, MDST4 and MDST6 and switched to a low level, and codes MDST1 and MDST5 also switched to a high level. Therefore, in the default mode, the delay is 2, the mode binary address and the packet length is equal to 4, are automatically selected.

what's the word clock signal 62 to generate the main line sync pulse in response to the sync pulse buffer 56. As shown in Fig.10, if activated 1st Bank, goes to a high level, and then the main line clock pulse 1 Bank goes to a high level by logical element OR NOT 234 and inverters. However, if goes to a low level for regeneration,Rigoes to the low level after a time interval depending on each delay. Thus, when the delay value is equal to j, that is, CL1 has a high level, and CL2 and CL3 low, goes to a low level after the delay time generated by the delay circuits, mainly 236, 238 and 240. If the delay value of j has been set to 2, it goes to the low level after the delay time generated by the delay circuits, mainly, 238 and 240. If the delay value is programmed at the 3, goes to the low level after a delay time generated mainly by the circuit 240. Thus, the higher the frequency of the system clock CLK, the shorter the delay time, forcing to go to a low level. Such time delays enable signals to select the columns to have enough time to spare before the start of the regeneration cycle in a write operation that allows you to properly write data to the cells, and Takeuchi in read operations. In this implementation, for the case when j = 1, the delay time will be about 19 NS, and in the case of j = 2 and j = 3, respectively about 6 NS and 3 NS.

Generator lowercase control clock 64, shown in Fig.3, is a well-known logical unit for generating clock pulses, shown in the timing chart of Fig. 10. A reset signal line of the address goes to a high level after the leading edge and goes low after the trailing edge Dictionary bus, the control signal goes to a high level after the leading edge and returns to the low level after the trailing edge of the Signal generated by the signal activates the read amplifiers selected by the signal block of information of the BLS, which is formed by decoding lower addresses. Signal to permit operation of the address buffer column goes to a high level after the leading edge and at a low level after the trailing edge Signal to provide goes to a high level after the leading edgeSand goes to the low level after the trailing edge

In Fig.21 shows a diagram of a logic device for generating signals which allow liberalizimi as shown in Fig.10.

In Fig.11 shows a diagram of the high-frequency clock generator in accordance with the present invention, which serves to increase the frequency of the internal system clock pulses when the regeneration team. In this implementation as a low-frequency system clock is an external system clock pulse CLK frequency of 33 MHz or less. High-frequency master clock oscillator 68 consists of circuit 242 to generate momentum-dependent commands regeneration logic element 248 for logical summation of the generated pulse with the internal system clock to generate the system clock pulse high frequency, and the transmit key 252 to transmit system sync pulse high frequency, given the delay.

Let us consider Fig.22, which shows the timing diagram of a read operation and the regeneration when the system clock CLK frequency is 33 MHz and the length of the packet SZ4. The regeneration team for the Bank, which reads, issued at time t4. Then goes from high level to low, and the output of A pulse generator 242 thereby generates a pulse width, savinase what chromosom using keys 246 through 248, throwing in the system clock pulse high frequency through the logical element AND-NOT 248. A logical element OR NOT 254 generates a high level, as CL1 is at a high level, and is at a high level only during a write operation. Thus the output signal of the key 248 is transmitted through a public key transmission 252. At this time, the transmit key 250 is turned off. Thus, since the internal circuits work with internal system clock CNTCLK9 with increased operating frequency after the regeneration, the output data can be performed at high speed, and the regeneration operation can be completed in a shorter time after the filing of a team of regeneration. When the frequency of the system clock CLK above 33 MHz, C1 is at a low level. Thus the element OR NOT 254 generates a low level signal, and a transmit key 252 is closed; key transmission 250 is also turned off, and CNTCLK9 becomes equal to the clock

Routes data

Under the data paths are routes deployed for output data bit on the bus through the data output buffers in read operations, and submission of data through the input buffer data to bit bus, the write operation. The piano is rendered blocks on the route data, associated with two submatrices.

Let us consider Fig. 23. Device select 1/0 bus and regeneration 38 is connected to the first 1/0 line 26R associated with one of submetric in one matrix of memory cells is 20tl, 20BL, 20TR and 20BR, and the second 1/0 line 26L associated with another submatrices, as discussed in Fig.1. The device 38 receives the signal block of information BLS to denote submatrices, including dictionary bus, the selected string decoder 18, and in response to the information signal connects 1/0 to the trunk associated with this submatrices, P10 line 256. Also, during read operations, because the data is present on two of the four pairs 1/0 tires in selected 1/0 line, the device 38 regenerates the remaining two of the four pairs and their corresponding P10 tire pair.

In Fig. 24 shows a diagram of the device for 1/0 regeneration and sample 38. When the signal block of information from BLS row decoder 18 is at a low level, the key transmission 258 and 258' are turned off, and the regeneration device 260 is enabled, thereby regenerating 1/0 bus pair with 1/00, 1/03, to the level of VBL (= 1/2 Vcc). When the signal block of information BLS is at a high level, to send data, the trims, that 1/0 bus pair, the selected data is the second 1/0 bus pair 1/02, 1/03, then the signal regeneration 1/0 tire IOPRI - goes to the low level, and its complementary signal IOPRI goes to a high level. Thus enabled devices regeneration 262 and schema alignment 264 and then 1/0 bus pair 1/00, 1/01, consistently regenerated and are aligned to the threshold voltage below the voltage where the threshold voltage of n-channel MOS transistor. However, since the regeneration device 262' and schema alignment 264', associated with the 1/0 bus pairs, transmitting data, are in the off state, the data is transferred to the corresponding second P10 tire pair of P102 and P103, through the keys of the transmission 258' in read operations. Similarly, data on P10 bus pairs can be passed to the relevant 1/0 bus pairs in write operations.

Let us return to Fig. 23. 1/0 read amplifier 266 is activated to amplify the data P10 line 256 by means of the control signal which is generated in response to a signal block of information in a read operation. 1/0 read amplifier 266 is a known circuit, which may also include a latch for storing data on its output.


accordingly to P10 bus pairs with P100, P103, forming P10 line 256.

In Fig. 25 shows a diagram of the multiplexer data output 268, which consists of devices regeneration 263a and 263d, latches 270, buffers 272 having three States, the first latches with 274a to 274d separating keys 276, second latches with 278a on 278d and key data 280, all of these elements are connected in series between the respective pairs of data bus and the common bus pairs of data CDL and in the same way as explained earlier about regeneration 1/0 bus pairs 1/00, 1/03, device regeneration with 263a for 263d react to the signal regeneration D10 tire D10PRI and its complement in the read operation, thereby preventing the regeneration of two pairs of data bus transmitting data, and regenerating the remaining pairs of data bus. The latch 270 is connected respectively to the data bus D100, D103, to store the data. Buffers 272 having three States, respectively connected between the data bus D100, D103, and the e data bus, they are regenerated, off. The first latch 274a-274d connected respectively to the outputs of the buffers with three-state 272 for storing data transferred through the data bus and the buffer. Each of the second latches with 278a on 278d are connected in series with the corresponding first latch through the corresponding separating the key. The second latch 278a-278d connected to a pair of common data bus CDL and through the corresponding key data 280. The key data 280, are activated in response to data signals with RDTP0 on RDTP3, which represent the pulse of high level is generated sequentially by the signals of the column address, thereby sequentially outputting the data stored in the second latch, to a common data bus and CDL through the first latch. Thus, as will be explained in detail below, the data stored in consecutive registers 274 and 278, consisting of the first and second latches with 274a on 274d and 278a on 278d, are sequentially displayed on the common data bus and CDL in response to data signals with RDTP0 on RDTP3. In operation degeneration bus pairs of data D100, D103, because the buffers 272 tristate held in the off state, there will be destruction of data, will hanamigawa beginning of its transmission through the keys 280, that is, in the case of long delays, if the new data is transferred from bus pairs of data, the previous data stored in the second register 278, will be destroyed. Also, such data destruction can occur when using a system clock of a low frequency, since the data signals with RDTP0 on RDTP3 are generated synchronously with the system clock. This loss of data because of their race may significantly occur in the operation of reading the interrupt, that is, in such an operation, in which to complete a batch operation for reads serial data at the specified packet length, issued the interrupt request and then executes the next read operation serial data packets of a certain length without interruption or standby depending on the address signals column. Thus, in order to prevent erroneous operation due to a race condition data, separating the keys 276 is installed between the first and second latches. The control signal for controlling the separating keys is a high-level pulse signal on the interrupt request in case of delay values 3 or 4. Data bus and CDL connected with famous snaps in and to the multiplexer data output 268, the clerk to send to the contact input/output (not shown) serial data synchronously with the system clock, which is determined by the packet length in read operations. In Fig.26 shows a diagram of the output buffer data 284. The keys of the transmission 286 and 286' respectively transmit data on the buses D0 to tire 288 and 290 synchronously with the system clock frequency (above 33 MHz in the present embodiment, the embodiment), but asynchronously with the system clock specified or lower frequency. As will be explained below, the control signal is kept at a high level when the frequency of system clock 33 MHz or below, that is, when the delay value is equal to 1, and is held at a low level when the frequency of system clock higher than 33 MHz. Latches 92 are connected respectively to the tires 288 and 290 to store the data. A switching circuit 310 is composed of logic elements AND NOT from 294 to 296 and transistors 300 and 302 connected between the tire 288 and 290 and the control transistors 304 and 306. The source of p-channel MOS transistor 300 is connected to the auxiliary voltage Vppfrom the known circuit auxiliary voltage to control the transistor 304 without reducing its threshold. Key schemes is the CIO at a low level or at the end of the read operation of the service, or when the operation of the masking data output.

Let us return to Fig. 23. Buffered input data 312 connected between the data bus D1 and bus 308 for converting an external input data bus 308 to the data in the CMOS level and receiving the internal input data synchronously with the system clock Buffer input data 312 may consist of the previously mentioned input buffer (enabled by a signal which is high when a write operation), which converts the external input data into CMOS level, and the previously mentioned synchronization device to receive the converted input data from the input buffer and then forming the internal input data synchronously with the system clock Thus, every time when the clock pulse goes to a high level in a write operation, the buffer of the input data 312 may operate as a buffer device for sequential sampling sequentially input data and output the resulting serial data on the data bus D1.

The demultiplexer input 314 is used to sample the serial data bus output D1 of the input buffer data 312 for transmission signals of the write data sequentially generated Synchron is (in this implementation - 2-bit parallel data) and their submission to the appropriate bus pair.

In Fig. 27 shows a diagram of the demultiplexer input 314. The demultiplexer 314 contains the selector keys with 315a on 316d connected to the data bus D1, for sampling to convert serial data from the data bus D1 in parallel data in response to the transmission signals of the write data with WDTP0 on WDTP3. Each of the latches with 320a to 320d is connected to the corresponding selector key to store the selected data. Conclusions latches 320a with on 320d connected respectively to the data bus D100, D103, through the keys with 322a through 322d, each of which is a logical element AND-NOT open in read operations, and buffers with 324a on 324d. The unlocking signal logic elements AND NOT with 322a through 322d, is a signal of high level in a write operation. Each of the buffers with 324a on 324d is an inverter with three States consisting of p-channel and n-canapini transistors 326 and 328. P-channel transistors 318a on 318d, respectively connected between the selector keys with 316 on 318d and latches 320a with on 320d, allow, in response to the control signal WCA1 and its addition to transfer case of double-bit parallel dinnerware one group, yet another group transmits parallel data. That is, when the control signal WCA1 is at a high level in a write operation, the transistors 318c and 318d off. Thus, the data stored in the latches 320c and 320d, is transmitted, in response to signals WDTP2 and WDTP3, the second pair of data bus D102, and D103, through the keys 322c and 322d and buffers 324c and 324d. At this time, since the signal is low, transistors 318a and 318b is enabled and the buffer 324a and 324b off. Thus the first pair of data bus D100 and D101, regenerated to a voltage supply circuits regeneration 263a and 263b, as shown in Fig.25. When the signal WCA1 goes to low level, the transistors 318c and 318d are included, and buffers with three transistors 324c and 324d off. Thus, similarly regenerated second pair of data bus, and the first pair of tyres in the transfer case of double-bit parallel data.

Let us return to Fig.23. Data transmitted via the bidirectional line data DB1 from the input data demultiplexer 314, served on P10 tire pair 256 through the driver P10 tires 330.

In Fig. 28 shows a diagram of the device driver P10 tires 330, which consists of key 332, responsive to the selection signals of the Bank DTCPiand the select signal BLS unit, for transmitting data is program data, entered via the keys 332, for submission to the relevant P10 bus pair; and devices regeneration and alignment 336 connected between the two buses, components of each P10 bus pair for regeneration and alignment P10 tires. It should be noted that the buffers 334 and devices regeneration and alignment 336 have the same structure as the buffer 324a on 324d on figure 27 and devices regeneration and alignment 260, 262, 262', 264 and 264' of Fig.24 and their functioning are also interrelated with each other during read operations. Driver P10 tires 330 breaks the link between highway data DB1 and P10 bus 256 pairs using signal DTCPilocated at a low level in the read operation. However, in a write operation, data on P10 bus 256 pairs transmitted from highway data DB1 through the driver 330, proceed to the appropriate 1/0 bus couples the selected device 1/0 regeneration and selection 38. Because every two pairs of alternately busy transmitting data, if the first 1/0 bus pair 1/00, 1/01, left 1/0 line 26R, which are respectively connected with the first P10 bus pairs P100, P101, carry data, the second P10 tire pair of P102 and P103, and the second 1/0 bus pair 1/02, 1/03, left 1/0 line 26R will be regenerationand for generating control signals to control devices, associated with the route data.

In Fig. 4 presents a block diagram depicting the control unit columns in accordance with the present invention. In Fig.4 buffer 338 receives the external strobe signal, the column address and the internal system clock pulse and then generates pulse signals BITSET

The buffer receives the external signal recording resolution of the system clock pulse of the pulse signals of the buffer 338 and various control signals for generating control signals of a write-in write operations.

DQM buffer 342 receives the external signal OM and the internal clock pulse and then generates the signal masking inputoutput disable input and output data.

The buffer address column 344 receives an external column address with A0 through A9 synchronously with the system clock thus locking the column address in response to a pulse signal from the CA buffer 338, and then generates the address signals column ECA0 on ECA9.

The address generator column 346 is a counter with a specified number of digits or bits (nine bits in this implementation). The counter performs a counting operation or sequential addressing or in binary mode or in the mode tseregounis columns, received from buffer address column 344 in response to the pulse BITSET, and, thus,

low-order bits associated with the signal packet length SLn, perform counting on sync CNTCLK9, since the recorded signals of the address column, and then generate serial signals column address depending on the selected addressing mode. However, the remaining bits give fixed them in the original signals of the address column. The reset signal of the column address signal is reset after the end of the package, i.e. after the conclusion of the actual data.

Count packet length 350 is a generally accepted desyatirazryadnyh (or devyatiletnij) binary counter counting clock pulses after the reset pulse signal BITSET from the buffer. The counter 350 may also be reset by the reset signal address column As the signal BITSET is a pulse generated by the activation of the counter 350 counts the number of pulses of the clock after activation, however, the signal is a signal for stopping the counting operation of the counter 350. Thus, in the operation of the interrupt activation during output real data makes the operation of the counting to begin now the CSOs earlier device setup mode, 58 and then generates the signal COSP, denotes the end of the package.

The signal generator reset address column 354 serves to generate a signal to reset the address generator column 348 in response to signal the end of a batch COSP.

The counter control data 346 is a counter that receives the signals of the column addresses CA0, CA1, FCA0 and FCA1, and then generates the address signals column RCA0 and RCA1 synchronously with the system clock clock pulse CNTCLK9 is a clock pulse, artificially generated to reduce the time of regeneration, when the system clock pulse CLK with a frequency of 33 MHz or lower is used, as described above. Thus, in this case, the signals of the column addresses CA0 and CA1 are not signals, synchronized with the system clock That is counter 348 is selected from considerations of reducing the time of regeneration when the frequency of system clock 33 MHz and below. If it is not necessary, the generator column address 346 receives the signal instead of the signal CNTCLK9, and generators sync data when reading and writing 356 and 358 may receive signals of the column addresses CA0 and CA1 instead of the output signals of counter 348, i.e. signals PCA0 and PCA1.

The clock generator before lsom and then generates pulses of data when reading RDTPm to output serial data from the multiplexer output 268 in read operations.

Generator sync data when recording 358 receives signals RCA0 and RCA1 and then generates pulses of a data transfer when writing WDTPm to output the multiplexed time parallel data from the demultiplexer input data 314 in the recording operation.

1. and DQM buffers

In Fig. 29 shows a diagram of the device buffer 338, and Fig.33 shows the timing diagram of a write operation when the frequency of system clock of 66 MHz, the length of the package 4 and the delay

In Fig. 29 input buffer 70 is a device the operation of which is prohibited in the recovery operations and masking pulse and which converts the input signals to internal signals of the CMOS level reads and writes. A synchronisation unit 108 is connected to the input buffer 70 to synchronize the CMOS signal level from the input buffer with the system clockCLK. The pulse generator 360 is connected to the synchronisation unit 108 for generating control pulsesCA,CPand BITSET. Let us consider Fig.33. PulsesCA,CA,CPand BITSET are generated according to the pulse of the low level at time t3. The width of the high level pulseCapproximately one cycle Sirima as pulse width CPand BITSET about 5-6 NS.

In Fig.30 shows a diagram of a buffer device 340. In the drawing, the input buffer 70 is a device for converting an external signal write access internal signal of the CMOS level. A synchronisation unit 108 stores the signal of the level shift from the input buffer 70 in the latch 362 synchronously with the system clockCLK. The input latch 366 is connected to the output of latch 362 through the key data 364 enabled by the activation signal for maintaining a high level in a write operation. The logic circuitry 368 consists of logic elements connected to the output of the latch 366. The shift register 370 is connected to the logical unit 368 to delay for one cycle of the signal CLK after a write command. The pulse generator 378 generates a short pulse of high levelWRDregeneration to reset the shift register 370 and the latch 366. Please refer to Fig.33. When a signalCAis at a high level after issuing the write command at time t3the latch 366 remembers a high level. Because the signalCand at least one signalRCD1andACD2are also at a high level at this point, as described above, the logical elements is. Output low level from the logical element AND-NOT 372 is supplied to the shift register 370, thus bringing him low level signal, the delayed one cycleCLK. Then the logical element AND-NOT 374 outputs a high level, causing the control signalWRmove on to a higher level. Generating a control signalWRafter a delay of one cycle of the pulse CLK is necessary for receiving external input data at the next CLK cycle after the write command. Thus, for professionals obviously, for receiving external input data in the cycle of the write command shift register 370 is not required.

In Fig. 31 shows the circuit DQM buffer 342, and Fig.32 timing diagram illustrating operation DQM buffer.

Let us consider Fig.31. The input buffer 70 is a buffer for converting the external signal DQM signal CMO level. Shift register 382 is connected in the input buffer 70 to generate a signal dropout output data synchronously with the system clockCLK. Let us consider Fig. 32, in accordance with which the team of masking data output is issued at time t1. At this time, the latch 384 maintains a low level. WhenCLK387 then goes on vis captures a high level. Then whenCLK388 goes to a high level, the signal goes to a low level. Similarly, the signal goes to high level whenCLK389 is at a high level. Thus, there is a ban conclusions data from the buffer output data signalDOMlocated at a low level, on the leading edge of the second clock CLKafter issuing the command mask data output. Experts obviously, configure the inactivity time of the data output can be performed by varying the number of shear discharges.

2. The generator column address

The address generator column consists of a buffer address column 344 and the address counter column 346.

In Fig. 34 shows a diagram of the buffer address column 344. In the synchronous DRAM in this embodiment, the implementation uses ten buffers address columns that receive the external address of the columns of A0 through A9, respectively. In Fig.34 input buffer 70 is used to convert an external signal of the column address A1 to the address signal of the CMOS level. The input buffer 70 is enabled by a signalRALand its output connected to the latch 392 through the transmit key 390. UntilCAdo not go on high, Ural branch of the ora. To the control counter data 346 summed signals only FCA0 and FCA1. When CAis at a high level due to the activation of the transmit key 394 is enabled, remembering thus, the addition signal of the column address ECA1 in the latch 398. The output of the latch 398 is connected to the switching circuitry comprising logic elements AND NOT 400 and 402, which includes a signalCAL.. Include elements AND NOT 400 and 402 output of the column address CA1 and its complement, respectively. The signals of the column address CA1 is transferred and loaded into the address counter column 346, whereby generated sequential address signals column FCA1 using the account that runs the signal loaded in the address column. Signals PCA1 appear as signals of the column addresses CA1 and through the keys of the transfer 396, latch 398 and logical elements 400 and 402. Thus the keys 394 and 396, latch 398 and elements 400 and 402 form a circuit for issuing a start address column pulse CAgenerated when activating and outputting the serial signals of the address column, calculated from the start address column when pulseCAis at a low level.

Thus, after activation, serial ADRs columns, can be formed at high speed. It should be noted that in this implementation, the address buffers column related signals of the column addresses CA0 and CA9, do not receive signals PCA0 and PCA9. The signal CA9 is not associated with the column decoder, because it is used as a Bank select signal if the operation is interrupted. Signals CA0 and CA1 are also used to generate the clock of the transmission data to be read RDTPm and clock transmission of the write data WDTPm, which are used respectively to the multiplexer data output 268 and the demultiplexer input 314. Signals CA1 on CA8 used to decrypt columns.

In Fig.35 shows a diagram of the device of the address counter column 346, and figure 36 diagram of the device each digit of the address counter column. In accordance with Fig. 35 and 36, the address counter column 346 is a 9-bit counter consisting of 9 digits with ST1 in ST9, and composed of a first counting unit that includes a low-order bits with ST1 ST3, and logical elements And 404, and the second counting unit, including discharges from ST4 on ST9 and logical elements And 406. The first counting unit may perform a count operation in one of two modes: Eyad counting unit, that is, a 3-bit counter mode (binary or interleaved) is performed on the logical level of the signal addressing modeINTEL. In the youngest Sachsen discharge ST1 input signal transfer CAR1 and the input packet length SL is connected to the supply voltage Vcc. The output signal of the transfer CAR0 first class ST1 is input CAR1 second discharge ST2, and the logical element And 404 that corresponds to the second discharge ST2, Peremohy transfer outputs of the first and second bits ST1 and ST2. The logical element And 404 corresponding to the third category, ST3, logically multiplies the output of the transfer of the third discharge ST3 and the output of the logic element And corresponding to the second discharge ST2, which is connected to the carry-in input of the third discharge ST3. The output of the logic element And associated with the most senior meaningful discharge ST3 of the first counting unit connected to the signal input of the transfer CAR1 lower significant digit ST4 second counting unit. The input signal CAR1 each digit in the second calculating unit is connected with the output of the logic element And the previous discharge. For each logical element And 406 of the second counting unit is fed the output signal of the logic element And the previous discharge and the output signal according to the one mode (binary or interleaved) sequential addressing, with the aim of increasing the flexibility of design for designers of systems memory. The binary mode addressing is generating sequential addresses, increasing per unit from the specified starting address and the addressing mode interleaved consists in generating sequential addresses in a certain way. On table.3 presents the address sequence, represented as decimal numbers in the case of a packet length equal to 8.

In Fig.36a shows a diagram of each of the bits of the first counting unit. In the drawing, each of the discharge of the first counting unit includes a transfer structure 408 to generate the signal transfer and discharge circuit 410 to signal discharge. The transfer structure 408 consists of two latches 412 and 416, the transmit key 414 connected between the latches 412 and 416, inverter 418 and transmit key 411, connected in series between the output of latch 416 and input latch 412. Similarly, bit circuit 410 also includes a latch 412' and 416', keys transmission 411' and 414' and the inverter 418'. The keys of the transmission 411, 411', 414 and 414' are connected to the bus 419 and bus 415 through the inverter 413. The inputs of the latches 412 and 412' are connected to the bus 422 and 424, respectively. Scheme initialization 420 included between buses 422 and 424 to ensure that the initialization conditions, i.e. low-level enable signal picaninny respectively to sync CNTCLK9, the output of the logical element AND-NOT 428 and the signal BITSET. The logical element AND-NOT 428 receives the signal packet length SLn, a signalCACRand the signal transfer CAR1, which is the signal transfer of the previous discharge CAR0. The keys of the transmission 430 and 432 are included in response to the signal BITSET and transmit thus, the initial value of the signal transfer and the initial value of the column address (or the initial bit value) on the buses 422 and 424, respectively. The control signal modeINTELis at a high level in alternation and at a low level in binary mode, as shown above. Thus, the key transmission 430 and 432 that are included in mode interleaved transmit respectively a low level and the initial value bits CA1 and in binary mode, both transmit key initial value bits CA1.

In Fig.37 depicts a timing diagram illustrating the operation of the circuit of Fig. 36a. Refer to these figures. When any of the input signals SLn,CACRand CAR1 element AND-NOT 428 is at a low level, the logical element OR NOT 426 prevents the output pulse CNTCLK9, keeping a low level on the bus 419. Thus, the keys of the transmission 414 and 414' are in an enabled state, while the keys of the transmission 411 and 411' in via level, the output signal of the transfer CAR0 and bit output signal PCA1 are respectively the initial value of the signal transfer low levels, and the initial value of the discharge mode interleaved, while the output signal of the transfer CAR0 and output bit signal PCA1 both have an initial value of the discharge CA1 in binary mode. Then a low level signal BITSET off the keys of the transmission 430 and 432 and, thus, causes the preset initial values of signal transfer and discharge, which must be installed on them. Thus, the signal BITSET implements a preset respectively the initial values of signal transfer and discharge in the transfer structure 408 in the discharge circuit 410 in accordance with the control signal modeINTEL.

On the other hand, after setting initial values of the signal PE BITSFT when signals SLn,CACRand CAR1 all are at a high level, the logical element OR NOT 426 generates a pulse CNTCLK9. Then, the transfer structure 408 and discharge circuit 410, respectively, generates a binary sequential counter values, starting with preset initial values for each cycle of the pulse CNTCLK9. During this series of operations, if the element AND-NOT 428 served rings is and 408 and discharge circuit 410. That is because the keys of the transmission 411 and 411' are turned off, CAR0 and PCA1 fixed respectively to the opposite binary values stored in the latches 412 and 412'. Then when the signal CAP1 go to a high level, again begin a series of operations, starting with the saved values.

In Fig. 36b shows a diagram of the device, each category comprising a second counting unit shown in Fig.35. The structure of this category is identical to the structure of the discharge in Fig.36a except the schema migration 408 and device mode control 434. Its operation is also identical to the operation of the discharge circuit 410 in Fig.36a. Thus, a detailed description of each of the digits with the ST4 on ST9 will be omitted.

Let us return to Fig.35. Suppose that the packet length n is set in the program operation mode. Then, as the signal length of service associated with the packet length n or less, all are at a high level, include only the digits, the receiving signal packet length SLn high level. For example, if the packet length n = 512 (full page), the address counter column operates as a 9-bit counter. If the packet length is programmed equal to 32, the five least significant bits with ST1 through ST5 posledovatelyam initial input values of the digits, that is, the inputted address signals column CA5 by CA8. Thus, the first counting unit, consisting of the three least significant bits with ST1 ST3, outputs the serial signals of the addresses in binary mode or interleaved with PCA0 on PCA2 in accordance with the control signal modeINTELand counter consisting of digits ST4 and ST5, outputs the serial signals binary address PCA3 and PCA4, starting from the input column address CA3 and CA4, taking the signal transfer from the first counting unit.

3. The column decoder

As explained above, the address buffers column 344 output address columns on CA1 CA8 entering the column decoder to select columns.

In Fig. 38 shows a diagram of the column decoder in accordance with the present invention. In the drawing predelivery with 436 in 442 accept signals of the column addresses CA1 and CA2, CA3 and CA4, CA5 and CA6 and CA7 and CA8, respectively, and the signals lowercase addresses RA11 or the signal of the column address CA9. The signal line addresses PA11 is used as the select signal of the Bank in the case of interleaving the first and second banks or in the case of independent operation of both banks, for example, performing a read operation or write and operations of regeneracy the 1 is at a low level, selects the first Bank, and if RA11 at a high level, it selects the second Bank. On the other hand CA9 is used as the select signal of the Bank in case of operation interrupt. The first Bank is selected when CA9 is at a low level, and the second Bank when CA9 at a high level.

First predesignated 436 decodes the signals of the column addresses CA1 and CA2, generating, thus, the pre-decoded signals with DCA12 and signal DCA2 and its complement which are faster than signals with DCA12. Adjacent signals of the pre-decoded partially overlap by a specified amount. The output signals of the first predesignate 436' serves to the main decoders 444. Logical elements OR NOT 446 respectively received combination of signals, select one of the pre-decoded signals with DCA34 from predesignate 438, one of the pre-decoded signals with DCA56 from predesignate 440 and one of the pre-decoded signals in DCA78 from predesignate 442. Their outputs connected respectively to the main decoder 444 in order to generate the selection signals columns CSL0 on CSL255.

In Fig. 39a shows a diagram of the first paragraph the signals of the column addresses CA1 and CA2 and additions After activation of the short pulse CPlow level resets the elements 451 and 454, causing the transition of the output signals with DCA12 at a low level. WhenCPthen goes to a high level (at this timeYEiat a high level), includes logic elements AND 451 and 454. Suppose now that CA1 and CA2 were at a low level. Then the logical element 448a will give a low level, and the logical element AND-NOT 456a then go to a high level. So, go from low to high level, while and DCA12 will remain at a low level. Then when CA1 go to a high level and CA2 will remain at a low level, go, as a result, at a high level. However, the logical element AND-NOT 448a will generate a high level, forcing the move to a low level after a time delay through delay circuit 450a and 452a, logical elements, AND IS NOT 451a, 456a and 454a and the inverter. Thus the signal after the transition to a high level, goes to a low level with a time delay determined by the delay elements. Therefore, the overlapping part of the cause residues between successive pre-decoded signals. This overlap ensures that there are no errors during write operations. what Torah predesignated represents a logical circuit, include a low level, in which the selected pre-decoded signal is translated to a lower level.

In Fig. 40 shows a diagram of the first of the main decoders 444. In this drawing, the pre-decoded signals with DCA12 are fed respectively to the inputs of inverters with 458a on 458d, which are divided into the first group of inverters 458a and 458b and a second group of inverters 458c and 458d. Some conclusions of each of the inverters 458a and 458b, forming a first group connected to the drain of the first transistor 462 and some conclusions of each of the inverters 458c and 458d forming a second group connected to the drain of the second transistor 464. Other findings of each of the inverters with 458a on 458d connected to the supply voltage Vcc. The outputs of inverters respectively connected to the latches with 466a on 466d. The origins of the first and second transistors 462 and 464 are connected together to the drain of the third or separating transistor 466, whose source is connected to a reference voltage Vsshaving the ground potential and whose gate is connected to the output of the logical element OR NOT 446, to the inputs of which are fed pre-decoded signals from the second predesignation from 438 to 442. At the gates of the first and second transistor is but the decoded signals and DCA2, pre-decoded signals CA34, and overlapping pre-decoded signals c DCA12. Thus, after the transistor 462 or 464 and separating the transistor 466 is enabled inverters with 458a on 458d can be included. Suppose now that the address signals column CA1 on CA8 were at a low level. Then turns on the transistor 462, and then the transistor 466. Then turns on the inverter 458a-level signal and thus the signal of the column selection CSL0 goes to a high level. Then when the signal of the column address CA1 changes its level at a high, goes to a high level, forcing the move to a high level signal of the column selection CSL1. However, the signal of the column selection CSL0 moves from a high to a low level after a predetermined delay, as discussed above, because of the transition to a low-level signal in the same manner as discussed above, the selection signals of the column overlying a predetermined portion in response to the address signals column with CA1 on CA8, sequentially changed. Consider figure 33b, where the initial external column address A0 and A1 to A8 are respectively at high and low levels. It depicted a timing diagram illustrating time St is from a drawing, period of time to select columns duly guaranteed by the overlapping portions.

In Fig.41 presents a timing diagram illustrating a read operation when the frequency of system clock of 100 MHz, the length of the package 4 and the delay 3. As can be seen from the drawing, due to the overlap of signals CSL0 and CSL1, guaranteed sufficient reading time, where A0 and A1 through A8 is initially set at high and low levels, respectively.

4. The control unit data highway

It is very important to eliminate optional internal operations, in order to eliminate the energy consumption after the end of the packet length, that is, after the output or input of real data. This control device includes a counter packet length 350, the detector packet length 352 and the signal generator reset address column 354, shown in Fig.4.

Count packet length 350 stops the count operation when the reset signal address columnCARis set at a low level. The counter 350 is reset by a short pulse of high level BITSET, again starting the operation of the account. Thus, the counter length of the package 350 is a known 9-bit binary counter, pulse input which is which signal BITSET and the addition signal CAR. Value CNTI (I = 0, 1,... 8) counter 350 is supplied to the counter packet length 352.

In Fig. 42 and 43 shows a diagram of a detector, packet length. The detector packet length 352 includes a logic circuit, receiving the counter value CNTI and signals the length of the packet to generate a signal COS1, informing about the completion packet length after activating Consider figure 41. Once, for example, the pulse BITSET go from a high level to a low after the activation of the counter 350 begins to count the pulsesCLK, giving thereby the signals account CNT0 and CNT1. Because, in the case where the packet length is equal to 4, SL4= 1 (high level), the detector packet length 352 outputs the signals COS1, the width of the pulse in one cycleCLKwhen CNT0 and CNT1 are both at a high level. On the other hand, impulse Clocated at a high level after activation translates into low level output trigger signal consisting of logic elements OR NOT 468 and 470, as shown in Fig.43, thereby causing the signal COSR go to low level, as shown in Fig. 41b. Since COSI then goes to a high level, two inputs of the logical element AND-NOT 474 switched to the high level after a delay that is generated shift register 472 systemic seed, asCat a low level, the output of the element OR NOT 470 goes to high level, causing thus move on to a higher level signal COSR. Thus, as can be seen from Fig.41b, the signal COSR low level indicates the length of the package, there are four system clock CLK after the activation of the delay Circuit 476 to provide time delays, depending on the values of the delay signal is received from the PRPS and then outputs a signal COSDQ. Thus, it is seen that the signal COSDQ specifies the packet length with regard to CA delay. Let us consider Fig.41. Because the delay is equal to 3 (C 3 high level), the transmitting key 478 included, giving the signal thus COSDQ representing the signal COSR, detained for two cycle pulseCLK. As has been discussed, the signal COSDQ when high, disables the output buffer data.

In Fig.44 shows a diagram oscillator reset address column 354. Let us consider Fig.41 or 33, where a signalRALiswitched to the high level before activation . Then after activating logical elements AND 482 and 484 give a high level in response to a pulse of high levelC. Thus, the element AND NOT 480, forming the trigger is fixed at a low level, thereby RA COSR, transitioning to a low level whenCat a high level, either because YEC1orYEC2held at this time at a high level. SoCACRgoes to a high level. Then, as the COP turned to a high level,CARandCACRmoving to a low level. However, in the case of system clock of a low frequency, for example, 66 MHz or less, the signalsRALiandYE1orYE2rather than the signal COSR, go first to a low level, thereby causing a signalCARgo to a low level. Thus, the count packet length 350 and the address counter column 346 reset signalCARlow level, thus preventing the execution of optional operations.

5. The clock generator data

The clock generator data is a device for generating clock data through the multiplexer output and the demultiplexer input. The clock generator data includes a count of the transmission control data 348 and generators sync data when reading and writing 356 and 368.

The address generator column 346 is Troy regeneration when using a system clock frequency of 33 MHz or less, as discussed previously. In this case, since the data must be transmitted synchronously with the system clock CLK, the counter management of data 348 essential. However, if this method is optional, that is, when not used low-frequency system clock requires some changes. Such changes can be accompanied by the following explanation. The fact that the address counter column 346, shown in Fig. 35, uses the system clock pulseCLKinstead of impulse CNTCLK9 as synchronous counting pulse. As shown in Fig.34, scheme selection 391, respectively, received digit output signals PCA0 and PCA1 for generating signals of the column address CA0 and CA1. Generators sync data when reading and writing 356 and 358 directly receive signals CA0 and CA1 instead of the output signals PCA0 and PCA1 counter management of data 348.

In Fig. 45 shows a diagram of the counter control data transmission 348, which includes the digit counters 488 and 490 and scheme selection 492 and 494. Digit counter receives signals of the column addresses CA0 and CA1 from the address buffers column 344 for generating signals internal serial address is at to generate a stream of successive column address signals FCA0 and FCA1, coming from the address buffers column 344, and the internal signals of consecutive column addresses received from the digit counter. Discharges 488 and 490, forming a digit counter, its structure is identical to the corresponding bits shown in Fig.36a and 36b. The difference between them is the use of system clockCLKinstead of impulse CNTCLK9. Each of the circuits of choice 494 and 492 has a structure similar to the scheme of 391 in Fig.34. Input signals FCA1 key transmission 394 and input PCA1 replaced respectively by FCAI and the output of the corresponding digit of the counter (where I is 0 or 1). The signal COSR is also fed to the third input of the logical element AND-NOT 400 and 402. Use the signal COP in the schemes of choice 492 and 494 thereby makes an optional internal operation upon completion of the packet length. To explain the operation of digit counter and selection schemes, we refer to the units discussed in Fig.36a, 36b and 34. Output signals RCA0 and RCA1 counter management of data 348 and additions can serve as a signal with the required time delay according to the delay values or in accordance with a system clock to control the timing of data transmission is 56 for generating transmission signals to read data from RDTP0 on RDTP3, used in the multiplexer output. In the drawing, the generator 356 includes logic elements AND 498 for decoding address signals column RCA0 and RCA1 and their complements delay circuit 500 for receiving the decoded signal and a signal transmitting read data with different time delays in accordance with the values of delay and logical elements AND 496 to output the transmission signals of data read in the read operation and reset their output signals to a low level in the write operation.

The output signals of the logic elements 496 switched to the high level in response to a signalWEDClocated at a high level in a write operation. Each of the logical elements AND NOT 498 serves as a decoder that outputs a low level signal in response to two input signal of high level. Each delay circuit 500 includes a shift register 503, with many routes data and keys 497, 501 and 502, respectively connected to data paths, and serves to provide different time delays with selector key in accordance with signals latency CL3 and CL4. Let us consider Fig. 41b, where the initial external column address A0 and A1 are sootvetstvujushej data and signal transmission data to be read from RDTP0 on RDTP3. Because latency is 3, the keys 502 is enabled.

In Fig. 47 shows a diagram of a device for generating a signalCLused in the multiplexer output 268. Consider this drawing. After activation, a high level pulseCthrough the delay circuit 505 translates into a high level output trigger 504. On the other hand, if one of the signals latency CL3 or CL4 is at a high level, the output of the logical element AND-NOT 506 is held at a high level. Therefore, a signalCLgoes to a high level. Then, ifCgoes to low level, a signalCLgo to a low level after a delay of approximately one cycleCLKin case, if the signal CL3 at a high level; and a signalCLgo

on a low level with a delay of about two cyclesCLKin case, if the signal CL4 is at a high level. However, if and CL3 and CL4 are low, that is, the delay is equal to 1 or 2,CLKthere will always be at a low level because the output of the logical element AND-NOT 506 is at a low level.

In Fig. 49 shows the timing diagram for a read operation by an interrupt after the activation Operation is performed when the ass is Manda reading with external column addresses A0, A1, A2, . . ., A8= 1, 0, 0, ..., 0. At time t3issued read command to terminate with external column addresses A0, A1, A2, ... , A8= 0, 1, 0, . . . , 0. Then, in moments of t3and t4i.e. before and after issuing a read command to the interrupt, the address signals column RCA0 and PCA1 take the values of low and high level. Thus, the read data is sequentially transferred via a bus pairs of data D102, D102 at time t3and t4. As can be seen in Fig.49c, the read data at the high level interrupt, and immediately after the interruption at a low level. Then, as shown in the timing diagram D102 between t3and t5in Fig.49c, serial data, that is, 1, 0, are transmitted via the data bus D102. Thus, as shown in Fig.25, if the device 276 to split the serial registers 274 and 278 does not provide communication between the two serial data is sequentially recorded in consecutive registers 274 and 278 and are transferred sequentially to the output buffer of data through the transmit key 280, which is enabled by the signal transmission of the data to be read PDTP2. However, because the performance of semiconductor circuits varies according to the surrounding conditions, such as okrujayushaya performance of key transmission 280 or output buffer data. SignalCLis used to separate consecutive registers 274 and 278 to prevent this kind of competition data. It should be clear that the competition between two consecutive data portions can be prevented by using pulseCLhigh level, designated as P in Fig.49c.

In Fig. 48 shows a diagram of a generator transfer the recorded data to generate transmission signals of the write data with WDTP0 on WDTP3 for use in the demultiplexer input 314. Generator 358 includes logic elements AND NOT decoding the column addresses RCA0 and RCA1 and additions to the timing circuit 510 to synchronize output signals of the logic elements AND NOT on the system clockCLKand forming a synchronized transmission signals of the write data and the logical elements AND NOT 512 for switching the synchronized transmission signals of the write data. Bus 514 remains at a low level, in order to close all the keys 512 during read operations, interrupt or mask input/output data, forcing the move to low level signals with WDTP0 on WDTP3. Link 516 refers to the delay circuit. As shown in Fig.33 with the WDTP1 high level, and the next sequential address signals RCA0 and RCA1, which are respectively at low and high level, generate a pulse signal WDTP2 high level.

6. The regeneration device data bus

The regeneration device data bus is used to generate control signals for regeneration 1/0 tires, P10 tires and D10 tires. In accordance with the present invention data transmission and regeneration is carried out alternately in the tire data paths. To perform the operation of the regeneration signal is used for the column address CA1, generated from an external column address A1.

In Fig. 50 shows a diagram of a device for generating control signals for regeneration 1/0 tires and P10 tires. Signals RA11 and CA9 are the Bank select signals, as discussed above, and 1/0 bus and P10 tires are initialized for regeneration. Thus the signals PIOPR1 and IOPR1 and their additions are set at a high level. After activation as CPgoes from low to high level (YEiis held at a high level), permitted the logic elements AND 518. If CA1 at a low level ( high level), the signal regeneration PIOPR1 and IOPR1 remain high, while to the 1/0 bus pair 1/02, and 1/03, continuously regenerated. Pair 1/00, 1/01, stop regeneration, in order to be ready for data transfer. P10 tire pair of P102 and P103, as shown in Fig.28, regenerated in the same way. Then, if CA1 goes to a high level, the bus 1/00, 1/01, , P100, P101 and regenerated in reverse order. On the other hand, a short pulseCPlow level is generated after activation in the operation of interrupts, converts all signals regeneration PIOPR1, PIOPRO1, IOPR1 and IOPR1 in pulses of high level. Thus, before taking the address column on abortion, all 1/0 and P10 tire pair regenerated. With this regeneration internal operations can be performed at high speed without waiting. Link 520 refers to the delay circuit.

In Fig. 51 presents a diagram of the device for generating control signals for regeneration D10 tires. In the same way, as discussed above, becauseCPgoes to low level, the signal regeneration D10 tire IOPRI and its complement are transferred at a high level, and the signal WCA1 and its complement are transferred at low levels, regenerating thus all 10 tires, that is, in the case of a transaction abort. IfCPgoes to a high level, and CA1 low me how signals are transferred respectively to low and high levels. Thus, during a read operation or write device regeneration 263c and 263d in Fig.25 retain the enabled state, while the device 263a and 263b off. After that tire pair D102, and D103 are held in a state of regeneration, while the D100 and D101, ready for data transfer. In the case of a write operation, the transistors 318c and 318d in Fig.27 are held in the open state, and the transistors 318a and 318b are closed, which causes the buffers 324c and 324d to be in the off state, and the buffer 324a and 324b to transmit data, depending on the state of the data stored in the latches 320. Further, if CA1 goes to a high level, operations are performed in the reverse order of the above.

In Fig.52 shows a diagram of a device for generating selection signals by the Bank for use in P10 driver 330, shown in Fig.28. Let the received write command. ThenWRandCPmoving to a high level. At this time, when PA11 or CA9 are at a low level, the signal DTCP1 is fixed at a high level, and thus selects the first Bank. When the team regeneration is issued by first Bank,YEIgoes to low level, and thereby the signal selecting the first Bank DTCP1 then goes to low the CSOs Bank, the trigger output 522' is fixed at a low level, and thus the signal selecting the second Bank DTCP2 then goes to a high level. And DTCP1, and DTCP2 connected to P10 driver 330 associated with the relevant Bank. Let us consider Fig.28. When the select signal Bank DTCPi and a signal block of information are all at a high level, the key 332 is opened, thus allowing the transmission of data on the relevant D10 tires.

7. The device buffer output

The control device output buffer data is used to control the data outputs of the output buffer data 284, shown in Fig.26. You need to read operations of the output buffer of the data led data for each specified leading edge of the system clock CLK. Because synchronous DRAM must provide the information only for a given period of time set by the delay and the packet length, it is preferable that the output from it is not out of the scope of a specified period of time, in order on the one hand, to increase the productivity of the crystal, and on the other, to prevent excessive power consumption. Also, since one cycle of the system clock specified or lesser frequency (33 MHz in this Varian is SS="ptx2">

In Fig. 53 presents a diagram of a control device for generating control signals for inhibiting data output from the buffer output 284. The logical element AND-NOT 524 outputs a signal of low level in the write operation. The sync pulseCFremains at a high level for one pulse cycleCLKmaking the switch to a high level by the first leading edgeCLKafter activation SimilarlyWRCFremains at a high level during one cycle of the synchronizing pulseCLKafter activation When activated, the logical element AND-NOT 524 generates a low level signal, thus allowing a signalTRSTgo to a low level. Also, when you want the masking data output by the external signal DQM, DQM buffer 342, shown in Fig.31 generates a pulse signalDQMFlow level, as shown in Fig. 32. Thus the logical element AND-NOT 526 generates a pulse of a high level. This causes a pulseTRSTlow levels. Similarly, a signalTRSTalso goes to low level signals COSDQ located at a high level after a delay that depends on the delay j, following upon completion of the packet length. Thus the output of the output buffer is level. Therefore, the output buffer data 284 prevents the output on the leading edge of the system clock CLK, the next after issuing the command mask data output in response to a signal dropout output data DQM. Also, upon completion of the batch output data output buffer 284 goes into high-impedance state.

If you are using an external system clock frequency of 33 MHz or less, the control signalYEPcan be combined with the delayed signal CL1 to the output did not depend on the internal system clockCLK. Since the delayed signal CL1 is held at a high level in such a system sync signalYEPis at a high level. Thus in the output buffer data 284 in Fig.26 keys send 286 and 286' always

open and therefore are not under the control of the system clock CLK. However, when using the system clock pulse with a frequency above 33 MHz, the signal CL1 is at a low level and a signalYEPalso at a low level. Thus the keys of the transmission 286 and 286' are switched on and off under control of system clock CLK.

Operation

Now, explanation will be given f is nnye chart illustrating the read operation when the packet length is equal to 4, and the delay is equal to 3, using an external system clock frequency of 100 MHz. At time t1command activation. External addresses come together with activation Then the buffer 56 outputs a signal RPand then generates the select signal BankRCidefining one of the two banks 12 and 14 with the external address A11. The generator main line synchronizing pulses 62 in Fig.19 generates the main line clock pulseRiin response to a signalRCi. The buffer line address 60 responds to the main line pulseRiby generating signals lowercase addresses served by the line decoder 18 selected Bank. In response to the signals lowercase address line decoder 18 generates a signal block of information BLS representing the selected submatrices each, with the first quarter, the matrix of memory cells, and a signal that selects a dictionary bus in the selected submatrices. A read operation that manages dictionary tires selected by selection signals dictionary tires, and then transmit data to the corresponding bit bus, is performed in a known manner. After completing the sequence, the generator opravlyaushi the UB> issued read command and the column address are buffered column address 344. In response to the signal being at a low level at time t2buffer 344 generates pulse signalsC,CA,CPand BITSET. SignalCARto control the devices associated with the generation of address signals column is formed by the signal generator reset address column 354 in response to a pulse signalCand a signal YECithat is generated by the clock generator permissions column 66 in response to aRCDi. The buffer address column 344 sends signals to the address columns CA0 through CA9 in response to a pulse signal buffer and a signalCAR. Thus, since the signals column address supplied from the buffer address columns 344-sensitive signals enable/disable column addressCAPthat are generated by a signalRCDireflecting the completion of the RAS sequence, and a signalcreflecting the activation period of time from the moment of activation (t2) to output signals of the address column is much shorter. After switching signalCAPat a high level, the counter packet length 350 performs a counting system clock CLK, čtk 352 generates a signal of the end of a batch, COSI and the signal COSR, reflecting the length of the packet after activation Detector 352 generates the signal COSDQ, delayed by the specified number of pulses from the signal COSR, depending on the value of the pre-delay to control the output buffer data 284, in order to supply the necessary amount of data for a period of time of the output data specified by the packet length. Thus, since the delay is equal to 3, the signal COSDQ is delayed by approximately two cyclesCLKwith respect to the signal COSR. Thus, the signal COSDQ is at a low level for a period of time determined by the delay and the packet length (the length of time between the moments t3and t6).

The address counter column 346 loaded signals column address from the buffer address column 344 in response to a pulse signal BITSFT from the buffer and the signal address resolution columnsCACRand then generates the address signals column PCA0 on PCA8 sequentially counting the pulse CNTCLK9 taking into account length of service and addressing mode. The buffer address column 344 generates signals of consecutive addresses columns on CA0 CA8, consisting of an initial address and column address signals column PCA0 on PCA8.

In Fig.41 presents the temporary diagra is Aries, and other external column address A1 through A8 is low. Because the installed length of service was equal to 4, only the signal packet length SL4 is at a high level. Thus only the two LSB ST1 and ST2 of the first counting unit included in the address counter column 346 in Fig. 35, performs the binary operation of the account. Since the count operation is performed with a frequency of 100 MHz, the pulse CNTCLK9 identical to the system clockCLK. Thus, the output signals RCA0 and RCA1 counter management of data 348 identical outputs RCA0 and RCA1 the address counter column 346. Output signals RCA0 and RCA1 counter 348 is fed to the pulse generator transfer read data 356, thereby generating the pulse transmission data to be read from RDTP0 on RDTP3.

On the other hand, the address signals column on CA0 CA8 from buffer address column 344 served by the column decoder 24, and predesignated columns 436 in Fig.39a generates pre-decoded signals partially overlapping with the signals of consecutive column addresses CA1 and CA2. The main column decoder 444 on figure 40 receives the pre-decoded signals to generate the column selection signals CSL0 and CSL1. Because the SIG is couples 1/00, and 1/01, data on the first 1/0 bus pairs that appear on the first pulse 532 column selection signal CSL0, are entered in the 1/0 power reading through the appropriate device select 1/0 bus and the corresponding first P10 bus pair. In response to the activated signal 535, as shown in Fig.41c, 1/0 read amplifier amplifies the data on the first P10 bus pairs to give them to the corresponding first pair of data bus D100 and D101, At this time, since the signal regeneration D10 bus D10PR1 is at a high level, the second pair of data bus D102, and D103 are in a state of regeneration. The data transmitted through the first bus pair data stored in the register 278 multiplexer output 268 of Fig.25. The data transmitted through bus pair data D101, D101 first bus data pairs are selected by the pulse RDTRI and then entered in the input buffer data through a common bus a couple of CDL data, the latch output data 282 and tire a couple of input data D0, in the same way as described above, the parallel data to the second 1/0 bus pairs 1/02, 1/03, which are generated by the pulse 533 signal of the column selection modern office building, then entered sequentially into the output buffer data. Recent data on the 1/0 bus pairs 1/00, first 1/0 bus pairs, catechetically data represent 1,0,1,0, the buffer output is enabled by pulse TRSThigh level, and the output DOUT is as shown in Fig.41c. Thus, when a signalTRSTis low, the output buffer data 284 goes into high-impedance state, and thereby prevented from performing unnecessary operations. You can see that the first information is generated by the leading edge of the third pulse of the system clock CLK after the activation of CAS, and a continuous four-bit data is output synchronously with the system clock CLK.

In Fig. 33 presents a timing diagram illustrating a write operation when the delay is equal to 2, the packet length is equal to 4, and the frequency of system clock of 66 MHz. The time scale in Fig.33 is the same as in the case when the external addresses A0 and A1 to A8 are fed with high and low levels, in the same way as in the above-mentioned read operation, and the input data DIN supplied to the input buffer of data that represent a sequence 1,0,1,0. The operation sequence is the same as explained above, and the signal packet length PRPS formed signal the end of a batch COSI. Signals of consecutive column addresses RCA0 and RCA1 to generate the UNT t2issued the write command, and control signals writeWRandFWDCissued by the buffer 340 for low-level signal. In response to the signals RCA0 and RCA1 the pulse generator transfer recorded data 358 generates pulses transfer the recorded data from WDTP0 on WDTP3 to convert serial data to parallel. The input data DIN input via the input buffer data 312, are output on bus input D1 in the form of serial data synchronously withCLKas shown in Fig.33. The demultiplexer input 314 generates parallel data on the data bus D102, and D100 under the control of control signals WCAI and pulse transmission of the write data with WDTP0 on WDTP3 with the time scale shown in Fig.33. Parallel data shall be submitted to the appropriate 1/0 thoroughfare through P10 bus driver 330 under control of control signals IOPR1 and then written into the corresponding memory cell through bit bus is selected by the column selection signals.

In Fig.49 presents a timing diagram illustrating a read operation with interrupt delay equal to 3, the packet length is equal to 4, and the frequency of system clock of 66 MHz. When receiving a read command to at time t1 is NDI read with interrupt at time t3external addresses A1 and A0 and A2 through A8 are fed respectively with high and low levels. This read operation c interrupt is identical to that described for a read operation except that the last case of double-bit data from data that had to be read by the read command issued at time t1and , as can be read in the interrupt command issued at time t3. Let us consider Fig.49, the explanation of which will be brief. Team activation, i.e. the command activation is issued for two cycles of the CLK before time t1. Then, since the operation sequence with the lower address is identical similar to the operation discussed earlier, the explanation of this operation is omitted. The read command is issued at time t1and pre-decoded signal of the column from predesignate columns as shown in Fig.39a, then goes to a high level, while the signals CA1 and CA2 are low. Then, the signal of the column selection CSL0 forms a pulse 600 high level, as shown in Fig.49b, when the signals on CA2 CA8 are always at the low level. After the transition CA1

from low to high level of pre-decoded signal startoffset pulse 601 high level. Once at time t3issued read command with an interrupt buffer 338 generates a signal BITSET in the form of a pulse 602. Then count the length of the package 350 is reset by the pulse 602 and re-starts the operation of the binary account system clockCLK. After calculating the length of a packet is equal to 4, the counter 350 outputs a signal of the end of the package COSI in the form of a pulse 603. The detector then packet length 352 generates the signal COSR low level indicating the packet length, from the first command read pulseCand the signal COSI, and then outputs a signal COSDQ indicating the time interval of the read data by using the signal COSR and signal delay. Thus it is seen that can be read entirely selebihnya data. The buffer address column 344, shown in Fig.34, registers external address column, enter the interrupt (at time t3) using pulseCAhigh level buffer 338, and generates signals of four consecutive column addresses using the address counter column 346. Thus the signal of the column address CA1, which is fixed by the external address A1 high level received at time t3maintained at a high level about two cycles of the clock after the transition CAn is lku all signals with CA2 on CA8 at this time are low, the signal of the column selection modern office building appears in the form of a pulse of high level 604. After the transition on CA1 low level, CA1 and its addition remain at low and high levels for about two cycles of the synchronizing pulse. However, a signalCARlow level causes the signals CA1 and go to a low level. As a result, the signal of the column selection CSLO allowed to transition to a high level in the form of a pulse 605. On the other hand, if the column addresses A0 and A1 are in the time t1respectively high and low, and when the column addresses A0 and A1 are in the time t3respectively at low and high levels, pulses are generated transmission data to be read from RDTP0 on RDTP3, as shown in Fig.49b.

Data on bit bus pairs are passed to the first 1/0 bus couples the pulse 600 CSLO, and then transferred to the first bus couples the data D100 and D101 through the first P10 bus pair. In Fig.49c shows how data high and data low level, respectively, are transmitted in parallel on bus D100 and D101. These parallel data are stored in the latches 278a and 278b in the multiplexer output 268 of Fig.25, and then the pulse 606 RDTP1 causes to output the data stored in the latch 278b associated with the bus 101. With the modern office building 601, transmitted to the second pairs of data bus D102, and D103, through the second pair 1/0 tires and second pairs P10 tires. As you can see, data D102 and D103 are respectively high and low. Pulse 607 RDTP2 selects the data stored in the latch 278c, and then the buffer output data output data of the high level RD2. Similarly, the parallel data is selected in the pulse 604 CSL1, are transmitted on the data bus D102 and D103. In Fig.49c shows how data is low level and high level respectively transmitted on the data bus D102 and D103. The transmit key 276 in Fig.25 returns to the off state when a high level pulse PCL. However, after the data, which were recorded in the latch 278c via the bus D102 in the previous operations were transferred to the output buffer data pulse 607 RDTP2, the momentum P becomes low level. Then open the key 276. Thus, the data on the data bus D102 and D103 are stored respectively in the latch 278c and 278d. Then the data stored in the latch 278c, issued on impulse 607 RDTP2, and thereby the output buffer data 284 outputs the data RD3 low level. Then the data stored in the latch 278d, determined by a pulse 608 RDTP3, resulting in the output data RD4 high level of the output buffer deja, data low level and high level, respectively, are transmitted in parallel on the data bus D100 and D101. In the same way as explained above, these parallel data is selected sequentially according to the pulse 603 and 610 shown in Fig. 49b, and then the output buffer data 284 consistently produces an output of low level RD5 and high level RD6. The output buffer data 284 passes then in vysokoimpedansnye status signal COSDQ high level.

In Fig. 54 presents a time chart illustrating various operations at a delay equal to 2, the packet length is equal to 4, and when using only one of the selected Bank. Issued the following commands: command activation at time t1the read command with external column addresses CA0 at time t2the read command with the interruption with external column addresses CBO at time t3the write command c interrupt with external column addresses CO. at time t7the write command with the interruption with external column addresses CDO at time t10the team regeneration at time t12and command mask input/outputs data at time t6, t9, t12and t13. Data QA0 and QA1 are displayed respectively at the moments t are displayed at the moments t5and t6by command read is issued at time t3. At time t7the output data is prohibited and remains in the high impedance state due to the command of masking output output data at time t6. In moments of t8and t9the recorded data DC0 and DC1 are introduced respectively through the write command at time t7. Command mask data input at time t9interrupts the reception of the write data at time t10. Similarly, in the moments of t11and t12accordingly entered data DD0 and DD1 due to the write command at time t10. Command masking input data is given in moments of t12and t14after regeneration at time t12.

In Fig.55 presents a time chart illustrating various operations at a delay equal to 2, and the packet length is equal to 4, and when one of the selected Bank. The operations of reading, writing, and mask input/output data here are the same as in Fig.54. After issuing frozen commands at time t1prohibits the generation of the internal system clockCLKcorresponding to the pulse 536 system clock CLK. Thus the output at time t5
.

In Fig. 56 shows the timing diagram illustrating the read operation when the delay is equal to 2, the packet length is equal to 4, and two banks. On command the activation of the first Bank at time t1and the read command at time t2, serial data QA0 on QA3 displayed since t3. On command the activation of the second Bank at time t3and the read command at time t4, serial data QB0 on QB3 also displayed since t5. At time t6at the same time command is issued to the regeneration.

In Fig. 57 presents a timing diagram illustrating a read operation with alternating at a delay equal to 2, and the packet length is equal to 4. Team activation for the first Bank is issued at time t1and to activate the second Bank at time t2. Thus data QA0 on QA3 read from the first Bank since t3. At the same time command the activation of the second Bank is issued at time t3. At time t4issued read command for the second Bank is selected when the data QB0 and QB1 are output from the second Bank without delay. At time t5issued read command for the first Bank at low column address A9, causing the serial output read data QC0 and QC1 from the first Bank. Then issued read command for the second Bank at time t6causing the output read data QD0 and QD1. Then at time t7command is issued to the regeneration for the first Bank. Then at time t8issued read command for the second Bank, whereby outputs read data QE0 on QE3. At time t9command is issued to the regeneration for the second Bank when the external addresses A10 and A11.

All the explanations in connection with Fig. 54 through 57 about the various operating modes is made in the presence of one group of contacts I/o data. However, it should be noted that in this implementation, there are eight contact groups of input/output data, and possibly their various uses

Other embodiments of the

As discussed above, this synchronous DRAM was implemented with a pulse signal. However, the synchronous DRAM in the present invention can be implemented with the level signal. Various commands functioning level were considered. For that is and while others can be used without changes.

In Fig. 58 shows a diagram of the buffer, that level will Refer to the drawing. The input buffer 70 and the timing circuit 108, forming a layered buffer 538, have the same structure and operation as the buffer 56 to the pulse shown in Fig.9. The output of the clock circuit 108 is connected to the first signal generator 540 for the first Bank and the second signal generator 542 for the second Bank through the latch 550. The first signal generator 540 consists of a trigger 545 for storing the signal of the first Bank in response to the Bank select signal generated by the address A11. Trigger 545 type AND consists of logic elements AND 544 and 546. One input trigger 545 connected to the output of the element OR NOT 548, another input trigger 545 receives the synchronization signal 108. Logical-OR-NO 548 receives the Bank select signal on its first input and the second input signal remains at a high level during recovery, installation or testing. The device of the second signal generator coincides with the device of the first signal generator. Thus, upon activation if the external address signal A11 is at a low level, that is on high, the trigger 545 captures riskily OR 548' of the second signal generator 542 generates a high level, trigger 545' retains its previous state. That is, if the activation in the previous operation, A11 was at a high level, that is, at a high level, the signal of the second BankRC2is held at a high level. On the other hand, if switching from low to high, the latch 550 will record high level at the leading edge of the next system clock CLK. Thus the logical elements AND 546 and 546' receive low level signals, and thereby a signalRC1andRC2moving to a low level. That is, both the Bank pass into the state of regeneration. In addition, since it is at a low level during recovery, and is at a low level during a set operation mode, signalsRC1andRC2when such operations are at a high level. SignalsRL1andRL2 > are faster thanRC1andRC2.

In Fig. 59, a, b shows a diagram address buffers to generate a special address SRA10 and SRA11. These address buffers operate independently of the address buffers row and column. The buffer address 552 intended the date of issuance of the signal SRA10 in response to the address A10 is used when the pulse signal, but not at the level of the signal. The address buffer . dressy buffer 554 for forming SRA11 in response to the address A11 contains the transmit key 556, which is opened in response to signalsRC1andRC2formed in the case rownego the transmit Key 556 is turned off by activating either the first or the second Bank, and is also used to prevent changes to the logical level of the signal SRA11 when the system clockCLKafter activating one of the two banks. When the address buffer 554 is used for pulse

you can make such changes to the output latch 558 would signal SRA11.

In Fig. 60 shows a diagram of the device control level to generate a control signal setup mode and clock recovery in case the level In the control signal generator set 200 of Fig.14 used in pulsed keys transfer closed by a signal RP. However, in the case of level keys transfer closed by a signal generated by a signalRL1andRL2 > instead signalRP. This is done in order to generate signals with faster signals RL1andRL2 > thanRC1andRC2. These operations coincide with the operations discussed in connection with Fig.14.

1. Other operations are the same as when pulse

As explained above, the build system and use this synchronous DRAM were examined in detail. Although the embodiments of the present invention considered in connection with the synchronous DRAM, the specialists in this area should be clear that the present invention can also be applied in other types of semiconductor memories.

1. A semiconductor memory formed on a semiconductor chip, including a column decoder and a row decoder, and a matrix memory, characterized in that the matrix memory is divided into two memory Bank, each memory Bank consists of upper and lower matrix of memory cells, with the latter divided into the left and right matrix of memory cells, each of the last matrix of memory cells divided into eight submetric memory cells arranged in a matrix form of rows and columns, moreover, in each memory Bank line decoder connected dictionary tires with each submatrices memory cells and configured to one of the data buffer address string address, in addition, each memory Bank column decoder connected to the tires of the sample column, directed perpendicular to the dictionary tires, and is designed to fetch one of the tires of the columns in accordance with the column address, each memory Bank contains device choice of tires I / o and regeneration, United with bus drivers through highways, and device choice of tires I / o and regeneration connected to alternate backbones, comprising four pairs of tires I / o and intended to transmit data to the corresponding memory cell corresponding submatrices, moreover, each pair of tires I / o connected to the corresponding keys of the column selection and the corresponding read amplifiers consisting of a P-channel amplifier, reading, separating the transistors of the transmission and balancing schemes and regeneration, in addition, the semiconductor memory comprises upper and lower buffers I / o, each of which is appropriate tires I / o is connected with the corresponding multiplexer input-output data, which is connected to four lines of data from the read amplifiers tires I / o and bus drivers, each memory Bank contains CA and located between the left and right bottom, and left and upper right, respectively, matrices of memory cells, while the Central power reading tyres I / o is designed to gain data on the corresponding line I / o and communications data highway data in response to the control signal when performing read operations, the Central bus driver is designed for sending data highway data highway I / o in response to the control signal during the recording operation, between the first and second banks of memory installed in the control device is designed to generate control signals and control decoders and column line decoder, as well as the devices of choice of tires and regeneration amplifiers read and bus drivers, multiplexers I / o data buffers input-output data.

2. Memory under item 1, characterized in that the control device is designed to control the rows of memory cells of the matrix and contains the buffer clock that is designed to convert an external sync pulse CL in the internal system clock pulse CLK, the buffer resolution clock that is designed to generate a signal massirovannogo from buffer sync, RS buffer receiving an external signal RS, the address signals SR10 and SR11 and generates a signal RP to the device installation operating mode, responsive to external signals C, WRC, and the address signals R-R6 and intended for different operating modes, such as address mode INTEL mode packet length SZn and delay Sli passed to the generator main clock, which is also arranged to respond to the control signal RCi generated RS-buffer, and generating the main clock line Ri buffer row address and control signal generator, the string buffer address used to receive signals external addresses AO-AII and generating signals lowercase addresses R-R11 synchronously with the clock CLK, the control signal generator is intended for reception of a signal block of information from BLS row decoder for generating an additional control signal dictionary tires X, a starting signal read S, the reset signal line addresses RARi, intended to clear the buffer row address signal RAL, designed to enable buffer address columns and signal RCDi intended to inform about the completion signals, Amnesty reception signal of the main clock line Ri and generate a signal to enable operation of the device, associated with the columns, the control unit also contains a high-frequency clock generator designed to generate a clock NCL9 to prevent reduction of the period of regeneration.

3. Memory under item 2, characterized in that the device installation operating mode comprises a generator of control signals setup mode, generating a setting signal mode MRS in response to the signals C, RP and WRC, formed as a result of issuing the command to set the working mode, the register address code, the receiving signal power from the device power and signal installation mode MRS and executed with the possibility of storing codes of the addresses transmitted to the logical device, the length of the package issuing the signal packet length CZn, and logical delay device issuing a signal delay Lj and memorizing signal addressing mode columns INTEL.< / BR>
4. Memory under item 2, characterized in that the RAS buffer receiving an external signal RAS, contains an input buffer and a timing diagram, the output of which is connected to the first signal generator intended for the first memory Bank and the second generator RAS signal for the second memory Bank, United with him through SAS to a signal selecting a memory Bank SRA11, one input of the trigger is connected to the output of the element OR NOT, and to another input of the trigger signal from the clock circuit, the inputs of the element OR NOT signal selecting a memory Bank and a setting signal mode, the second signal generator includes another trigger to store the signal of the second memory Bank, one input of which is connected to the output of another element OR NOT, and the other input to the timing circuit.

 

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The invention relates to computing and can be used to control and record the information in field-programmable gate arrays, including permanent and reprogrammable storage device

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FIELD: digital memory technologies.

SUBSTANCE: board has rewritable power-independent memory and control circuit, means for storing address, pointing at limit between authentication area and non-authentication area, circuit for changing size of said areas. Reading device contains estimation means, reading information, pointing at number of times, for which digital data can be read, and playback means. Second device variant additionally has means for digital output of contents.

EFFECT: higher efficiency.

3 cl, 23 dwg

FIELD: computer science.

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EFFECT: broader functional capabilities.

4 cl, 5 dwg

FIELD: data carriers.

SUBSTANCE: device for reproduction of data from data carrier, program zone of which is used for recording a set of files, and control zone - for controlling copy protection data concerning the file, recorded in program zone, has computer for calculating copy protection information for each time file is reproduced, comparison means for comparing value, calculated on reproduction command, being prior to current one, to value, calculated on current reproduction command, and if these values coincide, the last value is stored as copy protection value, calculated on reproduction command , prior to current one and control means for allowing reproduction of file, appropriate for current command, if value, calculated as response to command, previous relatively to current command, coincides as a result of comparison to value, calculated as a response to current command.

EFFECT: higher reliability, higher efficiency.

4 cl, 46 dwg

FIELD: data carriers.

SUBSTANCE: device for reproduction of data from data carrier, program zone of which is used for recording a set of files, and control zone - for controlling copy protection data concerning the file, recorded in program zone, has computer for calculating copy protection information for each time file is reproduced, comparison means for comparing value, calculated on reproduction command, being prior to current one, to value, calculated on current reproduction command, and if these values coincide, the last value is stored as copy protection value, calculated on reproduction command , prior to current one and control means for allowing reproduction of file, appropriate for current command, if value, calculated as response to command, previous relatively to current command, coincides as a result of comparison to value, calculated as a response to current command.

EFFECT: higher reliability, higher efficiency.

4 cl, 46 dwg

FIELD: data carriers.

SUBSTANCE: board has protected area, wherein a series of encoding keys is stored, unprotected area, wherein at least one sound record is stored and control information. Reproduction device has reading means, decoding means and reproduction means. Recording device has encoding means and recording means. Methods describe operation of said devices. Data carriers contain software, which reflects operations of said methods.

EFFECT: broader functional capabilities.

10 cl, 109 dwg

FIELD: electric engineering.

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EFFECT: broader functional capabilities.

7 cl, 148 dwg

FIELD: electric engineering.

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EFFECT: simplified construction, higher precision, higher reliability.

2 dwg

FIELD: data carriers.

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EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

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EFFECT: higher efficiency.

3 cl, 46 dwg

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6 cl, 2 dwg

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