A sinusoidal signal generator

 

(57) Abstract:

The generator of sinusoidal signal refers to the measurement technique and can be used in conjunction with electromagnetic structurename for fault detection and structurele products. A sinusoidal signal generator comprises a generator of rectangular pulses of fixed frequency controlled frequency divider, the unit's permanent memory, digital to analog Converter, a filter of low frequencies, the flip-flop, JK triggers, schema migration, and the control unit. Technical result achieved - the extension of the frequency range of the generated sinusoidal signal while maintaining the quality sinusoidal signal. 1 Il.

The invention relates to measuring technique and can be used in conjunction with electromagnetic structurename for fault detection and structurele products, in particular, by the method of eddy currents.

Known sine wave signal generator of electromagnetic StructureMap containing series-connected generator of rectangular pulses of fixed frequency, variable frequency divider and counter series-connected unit's permanent memory, N 1000896, CL G 01 N 27/90, publ. 28.02.83, bull. N 8).

The disadvantage of the generator is the limited frequency range of the generated sinusoidal signal. In the case of a large number of sampling points for the period of a sinusoidal signal of a lower frequency of the generated sinusoidal signal is very low. It is obvious that the minimum sampling period TDMPcannot be less than the value of

TDMP= tC+tA+tDAC, (1),

where tCthe time switch counter (with submission to the counting input of the counter pulse from the output of the adjustable frequency divider to establish a new output code of the counter), tA- sampling time addresses a persistent storage device that is used as the unit's permanent memory; tDAC- time of the output signal of the digital to analogue Converter. Analysis of the temporal characteristics of modern element base shows that for common chip permanent storage devices sampling time address is 45 NS (CRT) 60 NS (CRRT), and relatively inexpensive high-speed digital to analog converters the conversion code in the current ranges from 5 NS (CPA) is clucene meter) ranges from 50 to 80 NS, which corresponds to the sampling frequency fdnot above 12.5 to 20 MHz. At the same time, the frequency of the generated sinusoidal signal fwithequal to the sampling frequency fddivided by the number of sampling points for the period of a sinusoidal signal of nd:

< / BR>
Therefore, when the number of sampling points nd= 512 and the sampling frequency fd12,5. . ..20 MHz maximum frequency of the generated sinusoidal signal fCmax= fd/nd24...39 kHz.

Therefore, the upper bound of the frequency range of the generated sinusoidal signal is for use with this device is limited by the size of the order of tens of kHz; at the same time for multi-frequency electromagnetic structuroscopes often required test sinusoidal signal with a frequency of one MHz. Thus, the described device (analog) is not wide enough frequency range of the generated sinusoidal signal. The extension of the frequency range of the generated sinusoidal signal is impossible, since at high frequencies, it is impossible to use a large number of sampling points for the period of the sinusoidal signal due to the limited speed decreases the accuracy of the generated sinusoidal signal (i.e., increases the harmonic content of the generated sinusoidal signal).

Closest to the proposed device is a generator of sinusoidal signals to electromagnetic multifrequency StructureMap containing connected in series generator of rectangular pulses of fixed frequency controlled frequency divider and counter series-connected unit's permanent memory, digital to analog Converter and filter, and a control unit connected to the controlled frequency divider, and the unit keys included between the outputs of the least significant bits of the counter and the inputs of the least significant bits of the unit's permanent memory.with. USSR N 1118908, CL G 01 N 27/90, publ. 15.10.84, bull. N 38).

The disadvantage of the prototype is also limited frequency range of the generated sinusoidal signals. Some extension of the frequency range of the generated sinusoidal signal achieved by reducing the number of sampling points for the period of the sinusoidal signal at high frequencies, what is the unit keys. The unit key is used for switching the inputs of the unit's permanent memory: by disabling the unit's permanent memory from the low midrange is tion of the low order counter from entering the unit's permanent memory is read from the unit's permanent memory code for each point of the second sampling rate, and the number of sampling points for the period of the sinusoidal signal is reduced by half; when disconnecting the two least significant bits of the counter from the input unit constant memory is read from the unit's permanent memory code every fourth point sampling, and the number of sampling points per period is reduced four times; when disconnecting the three least significant bits of the counter from the input unit constant memory is read from the unit's permanent memory code every eighth point sampling, and the number of sampling points for the period of the sinusoidal signal is reduced by 8 times and so on, i.e. when you are disconnected from the inputs of the unit's permanent memory m least significant bits of the counter (where m is a positive number, the maximum value of which is determined by the ratio of the maximum number of sampling points for the period of a sinusoidal signal of nDmahto the minimum number of sampling points for the period of a sinusoidal signal of nDmah) the number of sampling points in the period decreases in the 2mtime. The reduced number of sampling points for the period increase is achieved the maximum frequency of the generated sinusoidal signal fCmax; however, at low frequencies is the maximum (for annealing signal the number of sampling points for the period, if necessary, reduced. The decrease in the number of sampling points for the period of the sinusoidal signal leads to the deterioration of the quality of the generated sinusoidal signal. Frequency side of the spectrum components of the generated signal is determined by the formula

fm=fC(inD1) = fDifC(3),

where fCthe frequency of the generated sinusoidal signal (the frequency of the main harmonic generated signal), nD- the number of sampling points for the period of the sinusoidal signal; i - number harmonics (nonnegative number): the minimum value of i is 0 and corresponds to the fundamental harmonic of the generated signal; other (positive) values of i correspond to the side constituting the spectrum of the generated signal. As can be seen from (3), reducing the number of sampling points for the period of the sinusoidal signal causes the frequency of adverse components are drawn to the undamental that hampers their suppression nepertraukiamam filter low frequency. However, for high frequencies generated sinusoidal signal the deterioration of its quality by reducing the number of sampling points for the period of the sinusoidal signal is lower than that for low frequencies (because, as can be seen from the AET suppression side of the spectrum components of the generated signal).

For the case when all inputs to the unit's permanent memory connected to respective outputs of the counter,

< / BR>
where fCthe frequency of the generated sinusoidal signal; fg- frequency square wave generated by the oscillator square wave of fixed frequency; nd- the number of sampling points for the period of the sinusoidal signal; kdthe division ratio of the frequency of the controlled frequency divider. As for the case when all inputs to the unit's permanent memory connected to respective outputs of the counter, the relation is valid:

< / BR>
where fd- sampling rate; fg- frequency square wave generated by the oscillator square wave of fixed frequency; kdthe division ratio of the frequency of the controlled frequency divider; the expression (4) can be converted to the form:

< / BR>
Expression (6) applies to cases where one or more least significant bits of the counter is disconnected from the outputs of the unit's permanent memory. From (4) and (6) shows that the decrease in the number of sampling points for the period of the sinusoidal signal should lead to an increase in the frequency of the generated sinusoidal signal. However, the trail is off the least significant bits of the counter from the unit's permanent memory, the counting frequency of the counter remains unchanged. From here it is easy to determine that disabling the m least significant bits of the counter from the unit's permanent memory reduces the sampling rate to 2mtime. Indeed, the sampling frequency is determined by the switching frequency of the LSB of the counter is connected to the input of the unit's permanent memory. For the LSB counter switching frequency equal to the frequency of the output signal of the controlled frequency divider, i.e., is determined by the ratio fg/kdwhere fg- frequency rectangular pulses generated by the generator of rectangular pulses of fixed frequency; kdthe division ratio of the frequency of the controlled frequency divider. For the next digit counter switching frequency 2 times lower than the switching frequency of the LSB, and so on: the switching frequency of each of the next (older) level 2 times lower than the switching frequency of the previous (lower) level. It follows that when disabling the m least significant bits of the counter from the unit's permanent memory sampling frequency fddecreases in the 2mtime.

Therefore, according to (6) when the number of sampling points on the periods of the frequency of the generated sinusoidal signal does not change, since the number of sampling points for the period of a sinusoidal signal of ndand the sampling frequency fddecrease in equal number (2m) times, and therefore, the ratio of fd/kdremains constant.

Thus, reducing the number of sampling points for the period of the sinusoidal signal by disconnecting the least significant bits of the counter from the unit's permanent memory does not increase the frequency of the generated sinusoidal signal. To increase the frequency of the generated sinusoidal signal, it is necessary to disconnect the m least significant bits of the counter decrease, respectively, in the 2monce the division ratio of the frequency of the controlled frequency divider kd, thereby increasing the output frequency of the controlled frequency divider 2mtime. Thus, the sampling frequency fdremains constant, but the frequency fSCrunning counter increases by 2mtime. Therefore, for the prototype while maintaining the sampling frequency is a constant frequency at which the counter is increasing. Obviously, compared with the equivalent for the prototype the number of sampling points for the period can be changed from the nDmahx to nDMPwhere n is aigaleo signal, when maintaining a constant sampling rate reduces the requirements to the performance of digital to analogue Converter and the unit's permanent memory, however, because the frequency at which the counter is not reduced to the base of the counter, generator of rectangular pulses of fixed frequency and a controlled frequency divider still are overly stringent requirements. Thus the operating frequency of the generator of rectangular pulses of fixed frequency and a controlled frequency divider (fg) may be higher than the operating frequency of the counter fSCthat depends on the range of variation of the division ratio of the frequency of the controlled frequency divider: with a minimum division ratio of the frequency of the controlled frequency divider, equal to kDMPthe working frequency fggenerator of rectangular pulses of fixed frequency and a controlled frequency divider in kDMPtimes greater than the frequency fSCrunning counter, and kDMP2mtimes the sampling frequency (in the particular case when kDMP= 1, the working frequency of the square wave pulser fgfixed frequency and a controlled frequency divider is equal to the Noah database counter, the controlled frequency divider and generator of rectangular pulses of fixed frequency, are overly stringent requirements. Assume that the maximum number of sampling points for the period of a sinusoidal signal of nDmah= 512, and the minimum number of sampling points for the period of a sinusoidal signal of nDMP= 8 (nDMP< 8 the quality of the generated sinusoidal signal is poor due to the significant growth of the amplitudes side of the spectrum components of the output signal of the prototype, whose frequencies are close to the frequency of the generated signal, resulting in difficulty suppressing side of the spectrum components of the output signal of the prototype and increasing the harmonic content of the generated sinusoidal signal). In this case, when the maximum frequency of the generated signal frequency fSCrunning counter exceeds the sampling rate in nDmah/nDMP= 512/8 = 64 times (the smallest number of sampling points for the period of a sinusoidal signal of nDMPcorresponds to the maximum frequency of the generated sinusoidal signal, and therefore, the maximum number of disconnected from the least significant bits of the counter inputs of the block postoli; fcthe frequency of the generated sinusoidal signal; nd- the number of sampling points for the period of the sinusoidal signal. Thus, when the frequency of the generated sinusoidal signal fC= 1 MHz and the number of sampling points for the period of a sinusoidal signal of nd= 8, the sampling rate is

fd= fWITHnd= 8 1 = 8 MHz,

as the operating frequency of the counter fSCexceeding the sampling frequency fdin nDmah/nDMP= 64 times:

fSC= fd(nDmah/nDMP) = 8 64 = 512 MHz.

Accordingly, the frequency fgwhere are controlled frequency divider and generator of rectangular pulses of fixed frequency should be at least 512 MHz. At the same time, even switching frequency triggers a fast series of logic circuits is not more than 1500 300 MHz (for other common series of logic circuits, such as 555, 1533 and even 500 and 1554, the switching frequency of triggers does not exceed the specified value, and is often even less). It is obvious that the maximum switching frequency of the trigger determines the maximum operating frequency counter circuits of the above series, which will be what about the sinusoidal signal is significantly limited temporal characteristics (performance) of the element base, moreover, if similar obstacle to increase the upper frequency of the generated signal is the limited performance of the unit's permanent memory and digital to analogue Converter, for prototype obstacle to a greater extent are the parameters of the element base generator of rectangular pulses of fixed frequency of the controlled frequency divider and counter. The prototype allows to reduce the requirements only to the temporary parameters (speed) of the unit's permanent memory and digital to analogue Converter, which is not enough to build broadband sinusoidal signal generator.

An object of the invention is the extension of the frequency range of the generated sinusoidal signal while maintaining the quality sinusoidal signal.

The technical problem is solved by the fact that the sinusoidal signal generator (hereinafter referred to as the device) containing series-connected generator of rectangular pulses of fixed frequency controlled frequency divider, and connected in series unit's permanent memory, digital to analog Converter, a filter of low frequencies, and the control unit, the connection, the rich inputs J and K of each of the JK-flip-flop integrated, and inputs the synchronization of all the JK-flip-flops and T-flip-flop combined and connected to the output of the controlled frequency divider; input setup T-flip-flop and JK-flip-flops are connected to the outputs of the control unit, the output of the T flip-flop is connected to the inputs J and K of the first JK-flip-flop; the outputs of the T flip-flop and the first JK-flip-flop is connected to the inputs of the first circuit transfer, the output of which is connected to the inputs J and K of the second JK-flip-flop; the outputs of the T flip-flop the first JK-flip-flop and the second JK-flip-flop is connected to the inputs of the second circuit transfer, the output of which is connected to the inputs J and K of the third JK flip-flop; the outputs of the T flip-flop of the first JK-flip-flop, the second JK-flip-flop and the third JK flip-flop is connected to the inputs of the third circuit transfer, the output of which is connected to the inputs J and K of the fourth JK-flip-flop and so on, i.e., the outputs of the T flip-flop of the first JK-flip-flop, the second JK-flip-flop, and JK-flip-flops with 3-th and i-th connected with the inputs of the i-th circuit transfer, the output of which is connected to the inputs J and K (i + 1)-th JK-flip-flop; the outputs of the T flip-flop and JK-flip-flops are connected to inputs of the unit's permanent memory so that the output of the T flip-flop connected to the input of the youngest of the address input unit's permanent memory, the output of the first JK-flip-flop - come in for the period of the sinusoidal signal and is equal to n = log2(nDmah), where nDmah- the maximum number of sampling points for the period of the sinusoidal signal; number of schemes for the transfer to one less than the number of JK-flip-flops.

The invention is illustrated in the drawing, which presents a block diagram of the device. The device comprises a generator of rectangular pulses of fixed frequency 1, the controlled frequency divider 2, the flip-flop 7, JK-triggers T1, T2, T3- Tn, schema migration, C1C2C3- Cn-1the unit's permanent memory 3, a d / a Converter 4, the LPF 5, the control unit 6.

The device operates as follows. The generator of rectangular pulses of fixed frequency 1 generates rectangular pulses of fixed frequency fgthat arrives at the input of the controlled frequency divider 2. The division ratio of the frequency of kdthe controlled frequency divider 2 are held by the control unit 6 installation control code to the second inputs of the controlled frequency divider 2 is connected to the control unit 6. Pulses with a frequency fg/kdfrom the output of the controlled frequency divider 2 arrive simultaneously at the inputs of the sync T-flip-flop 7 and all JK-flip-flops transfer C1C2,..., Cn-1form a binary synchronous counter with parallel transfer. The number of JK-flip-flops n is the maximum number of sampling points for the period of the sinusoidal signal; thus, if the maximum number of sampling points for the period of a sinusoidal signal of nDmahthe number of JK-flip-flops should be n = log2(nDmah- number of schemes for the transfer of mSP- one less: mSP= n-1= log2(nDmah) - 1. At the same time, the low order binary synchronous counter with parallel transfer, formed by the T-trigger 7, JK-triggers T1, T2, . .., Tn-1, Tnand transfer schemes C1C2,..., Cn-1, (bit 0) corresponds to the flip-flop 7, the next digit (digit 1) - the first JK flip-flop T1, level 2 is the second JK flip-flop T2the digit 3 is the third JK flip-flop T3and so on : the category (i - 1) corresponds to the JK flip-flop Ti-1that is the category i corresponds to the JK flip-flop T1(i-number JK-flip-flop: a positive integer, i= 1, 2, 3,. .., n-1, n, where n is the number of JK - flip-flops).

T-trigger 7, as well as all JK-triggers can be either in a static mode or in the mode of account (in static mode on the input setup T-flip-flop 7 is active utitsa in state "installed" (and held in this state by an active signal on the input set); in the counting mode on the input setup T-flip-flop 7 is a passive level, and the condition of the T-flip-flop 7 is changed by each output pulse of the controlled frequency divider 2). The level on the input set T-flip-flop 7 is set by the control unit 6, thereby controlling the operation of T-flip-flop 7, and hence the state of the LSB of the output code binary counter with parallel transfer, formed by the T-flip-flop, JK-triggers T1, T2,..., Tn-1, Tnand transfer schemes C1C2C3,..., Cn-2Cn-1carried out by the control unit 6.

Switching any of the JK-flip-flops T1, T2,..., Tn-1, Tnon the clock signal from the output of the controlled frequency divider 2, occurs only in the case when the inputs J and K of this JK flip-flop is active level, and at the entrance install this JK-flip-flop - passive level. Thus, when the active state of the inputs J and K and the passive state of the input set JK-triggers T1, T2,..., Tn-1, Tnwork similarly to T trigger 7 (i.e., change its state whenever it receives a pulse on input synchronization with the output controlled de is aemula frequency divider 2 switches only those of the JK-flip-flops, have the inputs J and K there is an active level when the passive level on the input set.

The state of the inputs J and K of the JK-flip-flop T1category 1 is determined by the output state of the T-flip-flop; the state of the inputs J and K of the JK-flip-flop T2category 2 is determined by the output state of the T-flip-flop 7 and the output state of the JK flip-flop T1category 1 with schema migration C1(high level at the output of the circuit transfer C1takes place only if all its inputs is high); the status of the inputs J and K of the JK-flip-flop T3category 3 is determined by the output state of the T-flip-flop 7, the output state of the JK flip-flop T1category 1 and the exit status of the JK-flip-flop T2discharge 2 with schema migration C2(high level at the output of the circuit transfer C2takes place only if all its inputs is high); for the rest of the JK-flip-flops T4, T5, T6,..., Tn-1, Tnthe state of the inputs J and K is defined by the schema migration C3C4C5,..., Cn-2Cn-1respectively. The output of the circuit transfer Ci(where i = 1, 2, 3,..., n-2, n-1) becomes active, if all inputs schema migration Ciare active Dada in the active state.

The input status of the installation JK-flip-flops T1, T2, T3,..., Tn-1, Tnas T-flip-flop 7, controlled by the control unit 6. If the signal on the input set JK-flip-flop Tiactive, the state of the JK flip-flop Tiremains unchanged regardless of the status of the inputs J, K and synchronization input (output of the JK-flip-flop T1constantly present active level). Thus, the corresponding JK-trigger Tithe digit counter is blocked, and the output of this JK flip-flop T1set in the active state (and held in the active state as long as the input set of this JK flip-flop is active). Similarly, by setting the active state of the input set T-flip-flop 7, the output of the T-flip-flop 7 is also set to the active state (and held in the active state as long as the input set T-trigger active).

If all the outputs of the control unit 6 connected to the inputs of the installation JK-flip-flops are in a passive state, binary synchronous counter with parallel transfer of the formed T-trigger 7, JK-triggers Ti, T2,... , Tn-1, Tnand transfer schemes C1C2C3,..., Cn-1works as a normal dvoc the ode of the controlled frequency divider 2, in the parallel code, then arriving at the inputs of the unit's permanent memory 3. The state of the T-flip-flop 7 is changed by each output pulse of the controlled frequency divider. The state of the JK flip-flop T1the next digit counter is changed by the output pulse of the controlled frequency divider whenever the output of the T-flip-flop 7 is an active signal. Since the output of the T-flip-flop 7 is set to the active state once during the two periods of the output signal of the controlled frequency divider 2, respectively, the switching JK-flip-flop T1will occur with a frequency 2 times less than the frequency at which switches T-trigger 7. Accordingly, the switching JK-flip-flop T2category 2 is the pulse received from the output of the controlled frequency divider 2, if the output of the circuit transfer C1is active, i.e. if the outputs of the T-flip-flop 7 and the JK-flip-flops T1are in an active state; switching frequency of the JK-flip-flop T2thus, it appears 2 times lower than the switching frequency of the JK-flip-flop T1that is 4 times smaller than the frequency at which switches T-flip-flop 7, and 8 times smaller than the frequency of the pulse the pulse of the controlled frequency divider will occur if the outputs of all of the JK-flip-flops T1-Ti-1and T-flip-flop 7 are in an active state; switching frequency trigger T12i+1times less than the frequency of the pulses at the output of the controlled frequency divider 2.

Thus, if all the outputs of the control unit 6, the control inputs installation JK-flip-flops are in a passive state, with each pulse received from the output of the controlled frequency divider 2 output code binary synchronous counter with parallel transfer, formed by the T-trigger 7, JK-triggers T1, T2, T3,..., Tn-1, Tnand transfer schemes C1C2C3,..., Cn-1changes to 1. The output code of the counter formed by the T-trigger 7, JK-triggers T1, T2, T3,..., Tn-1, Tnand transfer schemes C1C2C3,..., Cn-1converted unit's permanent memory 3 in the code sample sinusoidal signal. The sequence of codes of sampling a sinusoidal signal is converted to an analog signal by the d / a Converter 4. Side components (harmonics) that are present in the spectrum of the output signal digital to analogue Converter 4, suppressed the fen, the output of the T-flip-flop 7 is held in the active state. Therefore, the state of the JK flip-flop T1category 1 is changed for each pulse received from the output of the controlled frequency divider 2 to the clock input of the JK-flip-flop T1(not by each second pulse received from the output of the controlled frequency divider 2, as is the case when all inputs setup triggers, including T-trigger, present passive level). Considering next the operation of the counter formed by T-trigger 7, JK-triggers T1, T2, T3,..., Tn-1, Tnand transfer schemes C1C2C3,..., Cn-1it is not difficult to conclude that the switching frequency of each of the JK-flip-flops also increased in 2 times in comparison with the regime, when the input set T-flip-flop 7 is a passive level. Now binary synchronous counter formed by the T-trigger 7, JK-triggers T1, T2, T3,..., Tn-1, Tnand transfer schemes C1C2C3,..., Cn-1that generates a sequence of codes, the low-order which has a constant value. The values of high-order bits (i.e., all bits of the output code, except the youngest, or discharges from the underwater counter code from category 0 to category (n-1) in the passive state of all outputs of the control unit 6, connected with the inputs of the installation of the T-flip-flop and JK flipflops. If the least significant bit of the counter is blocked (i.e., T-trigger 7 is held in state "installed"), codes of sampling a sinusoidal signal read from the unit's permanent memory 3 is not in a row, and after one (i.e. from a block of constant memory is read every second code sample sinusoidal signal). At the same time, the sampling frequency remains the same, and as reduced by half the number of sampling points on the period of the generated sinusoidal signal, the frequency of the generated sinusoidal signal, on the contrary, increases twice.

Similarly, when applying the active level at the inputs of pre-installed T-flip-flop 7 and the JK-flip-flop of the next discharge (discharge 1) the state of the two least significant bits of the output code binary synchronous counter formed by the T-trigger 7, JK-triggers T1, T2,..., Tn-1, Tnand transfer schemes C1C2C3,..., Cn-1to remain unchanged. Now change only the status bits of the output code from category 2 to category n inclusive, the sampling frequency remains unchanged from the unit's permanent memory 3 will be considered for the period of the sinusoidal signal will be reduced by 4 times. Since the sampling rate remains constant, the decrease in the number of sampling points 4 times leads to an increase in the frequency of the generated sinusoidal signal 4 times.

Similarly, in the General case, when the stop of the m least significant bits of the binary synchronous counter, built on T-trigger 7, JK-triggers T1, T2, T3, . . . , Tn-1, Tnand schemes of transfer of C1C2C3,..., Cn-1(i.e., when applying to the inputs set the appropriate trigger active level, which forces the installation of triggers in the state when the output triggers an active level; after that these triggers are held in state "installed", while their inputs installation will remain active), the number of sampling points for the period of the sinusoidal signal is reduced in the 2magain, while the sampling rate remains constant and equal to the frequency at which the binary synchronous counter, built on T-trigger 7, JK-triggers T1, T2,..., Tn-1, Tnand schemes of transfer of C1C2C3, . .., Cn-1(i.e., the output frequency of the controlled frequency divider 2); the same frequency generated Shin is changing the number of sampling points for the period of the sinusoidal signal by reading from the unit's permanent memory 3 codes each second, the fourth, eighth, sixteenth, etc. points of sampling. However, if the prototype frequency, which is operated by the generator square wave of fixed frequency, a controlled frequency divider and counter, the maximum frequency of the generated sinusoidal signal exceeds the sampling frequency in the 2mtimes, where m is the number of disconnected bits of the counter from the unit's permanent memory, for the proposed device all the circuit elements operate at a frequency lower than the sampling frequency. Thus, requirements for the performance of the element base of the device is substantially less rigid (the maximum rate at which binary synchronous counter formed by the T-trigger 7, JK-flip-flops, T1, T2,.., Tn-1, Tnand transfer schemes C1C2C3, . .., Cn-1decreases in nDmah/nDMPtimes), therefore, the maximum frequency generated by the device sinusoidal signal may be correspondingly increased, and the frequency range of the generated sinusoidal signal is expanded in the direction of higher frequencies. The quality of the device-generated sinusoidal signal is yuandong signal frequency of the generated sinusoidal signal is adjusted by changing the division ratio of the frequency of the controlled frequency divider 2; the number of sampling points ndthis is defined as the maximum (nDmahto improve the quality of the generated sinusoidal signal (the maximum number of sampling points nDmahfor the period of the sinusoidal signal in practice is determined by the capacity of the unit's permanent memory, which in practice is limited). By increasing the frequency of the generated sinusoidal signal, the sampling frequency fdincreases, reaching the limit of fDmahat which further increase the sampling frequency cannot be made, due to the limited frequency characteristics of the components of the device. To further increase the frequency of the generated signal is used reducing the number of sampling points ndfor the period of the sinusoidal signal. Thus, the number of sampling points ndreduced only in the upper part of the range of the generated sinusoidal signal and a maximum frequency at which the working elements of the device does not exceed the sampling frequency fdthat allows for a tradeoff between the width of the frequency range of the generated sinusoidal signal, as generated sinusoidally the value of the number of sampling points for the period of a sinusoidal signal of nDMPdepends on the quality of the generated sinusoidal signal. The minimum number of sampling points for the period of a sinusoidal signal of nDMPmay not be less than 2 (and consequently trigger the senior level Tnnot be forced to install the control unit 6 in state "installed" at any frequency generated by the device sinusoidal signal). In the case of nDMP= 2 the output signal of the analog-to-digital Converter 4 has the shape of a meander. Using filter low frequency of the square wave can also be obtained sinusoidal signal, but in this case, the parameters of the LPF 5 meet very stringent requirements, since the amplitude of the side components (i.e., high-frequency harmonics) in this case is great. Consequently, in practice, the minimum value of nDMPas a General rule, made 2 more. In the General case should not be blocked at work N JK-flip-flops corresponding to the higher digits of the binary counter formed by T-trigger 7, JK-triggers T1, T2,..., Tn-1, Tnand transfer schemes C1C2,..., Cn-1where N = log2(nDMP), i.e., triggers Tn, Tn-1, Tn-2

Generator sinusoidal signal containing series-connected generator of rectangular pulses of fixed frequency controlled frequency divider, and connected in series unit's permanent memory, digital to analog Converter, a filter of low frequencies, and a control unit connected to the second inputs of the controlled frequency divider, characterized in that it is provided with a T-flip-flop, JK-triggers and schema migration, and J and K each JK flip-flop are combined, and inputs the synchronization of all the JK-flip-flops and T-flip-flop combined and connected to the output of the controlled frequency divider, the input setup T-flip-flop and JK-flip-flops are connected to the outputs of the control unit, the output of the T flip-flop is connected to the inputs J and K of the first JK-flip-flop, the outputs of the T flip-flop and the first JK-flip-flop is connected to the inputs of the first circuit transfer, the output of which is connected to the inputs J and K of the second JK-flip-flop, the outputs of the T flip-flop of the first JK-flip-flop and the second JK-flip-flop is connected to the inputs of the second circuit transfer, the output of which is connected to the inputs J and K of the third JK flip-flop, the outputs of the T flip-flop the first JK-flip-flop, the second JK-flip-flop and the third JK flip-flop is connected to the inputs of the third circuit transfer, the output of which is connected to the riggers from the 3rd to the i-th connected with the inputs of the i-th schema migration the output of which is connected to the inputs J and K (i+1)-th JK-flip-flop, the outputs of the T flip-flop and JK-flip-flops are connected to inputs of the unit's permanent memory so that the output of the T flip-flop connected to the input of the youngest of the address input unit's permanent memory, the output of the first JK-flip-flop - with the input of the next address entry, and so on, the number n JK-flip-flops is determined by the maximum number of sampling points for the period of the sinusoidal signal and is equal to n = log2(nDmah), where nDmah- the maximum number of sampling points for the period of a sinusoidal signal, a number of schemes for the transfer to one less than the number of JK-flip-flops.

 

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Pulser // 2150783
The invention relates to a pulse technique and can be used in automatic control systems and measuring devices

The invention relates to a pulse technique, the technique of automatic control and regulation and can be used for selection of pulses in sign

D-to-trigger // 2147787
The invention relates to switching devices and may find application in systems management, control, communication devices, computing devices and other devices in different industries

The invention relates to electrical engineering, can be used in converters with changing load, for example in converters with capacitive drive

The invention relates to the field of radio electronics and can be used in devices for various purposes, such as managed lo or sensors discrete set of frequencies

The invention relates to electronics and can find application in devices for generating a voltage sine wave, for example, as local oscillators for frequency converters or frequency synthesizers kalogiratou and low-frequency ranges

Frequency divider // 2292630

FIELD: electrical and radio engineering; locked-mode sources for transceivers.

SUBSTANCE: proposed frequency divided has transformer, capacitor, inductance coil, semiconductor diode, transistor, integrating circuit, and bias circuit incorporating series-connected bias voltage supply and resistor.

EFFECT: extended operating frequency range toward higher frequencies, facilitated manufacture.

1 cl, 2 dwg

FIELD: physics, radiotechnics.

SUBSTANCE: the synthesiser contains a frequency selection device, the outputs of which are connected to the first input of the first N-bit adder and the second input of the second N-bit adder, as well as a clock oscillator and a frequency halver connected in series, the outputs of which are connected to the third and second inputs of the first, second, and third shift registers, respectively. The output of the first register is connected to the first input of the second adder, the output of which is connected to the first input of the second register, to the first input of the third shift register, and the second input of the first adder, the output of which is connected to the first input of the first register. The output of the third register, through the first read-only memory (ROM) device, and the output of the second register, through the second ROM, are connected, respectively, to the first and second inputs of the multiplexer, the output of which is connected to a digital-to-analogue converter. The frequency halver output is connected to the third input of the multiplexer.

EFFECT: increase in maximum sine wave signal frequency by two.

4 dwg

FIELD: measurement equipment.

SUBSTANCE: generator of a sinusoidal signal comprises an N-digit summator, N-digit phase accumulator, a permanent memory, a digital-analogue converter, a device to generate a code of frequency of a generated signal F with capacity (N+M), a clock pulse oscillator, a device for conversion of a code of frequency of a generated signal F into a code of phase increment Δφ and into a code of clock frequency K in accordance with specified mathematical ratios of parameters.

EFFECT: expansion of a frequency range with preservation of summator and phase accumulator capacity and volume of permanent memory.

1 dwg

FIELD: measurement technology; pulse stream generators.

SUBSTANCE: proposed Poisson pulse stream generator has k + 1 memory devices, comparison unit, k digital-to-analog converters, control circuit, register, counter, selector, k bell-shaped pulse generators, adder, voltage-to-current converter, and clock generator.

EFFECT: enlarged generation range of pulses adequate to ionization chamber signals.

1 cl, 2 dwg

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.

EFFECT: enlarged functional capabilities of device.

1 cl, 1 dwg

Flip-flop device // 2248662

FIELD: pulse engineering, computer engineering, and control systems.

SUBSTANCE: proposed device has RS flip-flop 1, two NAND gates 2, 3, EXCLUSIVE OR gate 4, inverter 5, four resistors 6 through 9, capacitor 10, memory item 11 built around magnetic core with rectangular hysteresis loop that carries write and read coils, two diodes 12, 13, control input 14, and common bus 15.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248663

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248663

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248664

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flops 3, 16, EXCLUSIVE OR gates 1, 2, NAND gates 5, 6, NOR gates 10, 11, resistors 4, 7, 12, 13, capacitors 14, 15, memory items 8, 9 built around magnetic core with rectangular hysteresis loop and single center-tapped coil, input bus 21, and common bus 22. Combining read and write coils of memory items 8, 9 makes it possible to increase turn number in read and write coils by 1.5 times, in each of half-coils of memory items 8 and 9, which reduces magnetizing current through cores of memory items 8 and 9 approximately by 1.5 times due to enhancing ratings of limiting resistors 4 and 7.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

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