The design of the memory cell with vertically spaced one above the other intersections

 

(57) Abstract:

The invention relates to digital computing technology, specifically to the structure of the memory cell with vertically spaced one above the other intersections. The memory cell according to the invention contains a first transistor inverter having a first input and first output and the second inverter having a second input and the second output. The first and second transistors connected with the first and second intersecting connections. The first cross-connection connects the first input with the second output. The second cross-connection connects the second input with the first output. Two overlapping compounds contain different conductive layers in the manufacturing process of the semiconductor. This invention performs the intersection of different materials in different layers of the device. Therefore, the intersection can be placed vertically one above the other, thereby reducing the area of the memory cell. Effect: reduce costs by reducing the element size, improve reliability of the memory cells in memory devices. 3 C. and 22 C.p. f-crystals, 8 ill.

The technical field of this invention relates to the structure of the memory cell. More specifically, d is the values.

Static storage device with random access (STOPV) are often used in integrated circuit devices. For example, the matrix of cells STOPV used as a cache memory for high-speed microprocessors. One of the applications of STOPV - Level 2 (L2) cache memory for processor "Pentium-Pro", which is produced by Intel Corp., Santa Clara, Calif.

Matrix cells STOPV usually consists of several identical cells STOPV for each category of memory. For example, to implement the cache, 256K L2 processor, the Pentium-Pro requires millions of cells STOPV. With increasing matrix size STOPV remains unused valuable space and increases production cost. Therefore, it is necessary to reduce to a minimum the size of one cell STOPV to the size of the matrix STOPV was not too large that there is no unused space and the cost of its production was not increased.

One example of a design STOPV shown in Fig.1. 6-transistor cell STOPV 10 includes two inverter with complementary structure of metal-oxide-semiconductor (CMOS). The first inverter comprises transistors 110 and 111. The second inverter consists of Tr write.

For writing into the cell 10 corresponding to the record data (DATA) is placed at bit bus (BIT), and additions (DATA#) is placed on the bus (RANK#). Then numerical bus (SH) argue gate transistors 114 and 115, and DATA is written in the cell 10. To read the cell DISCHARGE and the DISCHARGE# pre-load. After this SH argue, and with the help of transistors 112 and 111, respectively, discharge or DISCHARGE, or DISCHARGE#. Or to eliminate the need for pre-charging to the tires of the DISCHARGE and the DISCHARGE# can use the static stress increase (not illustrated).

According to another variant, known from the prior art, the cell STOPV design similar to the cell 10 - except that the MOS transistors with a channel of p-type 110 and 113 should be replaced by other well-known devices increase voltage, such as operating in the depletion mode transistor operating in the mode of enrichment transistor, or resistor. Also the prior art cell STOPV, which contains one transistor instead of two transistor that controls the DISCHARGE signals and SH. In addition, a similar cell STOPV known from the prior art, contains two ports, or two numeric the design and engineering of the prior art, similar in the sense that they require the use of overlapping connections, such as intersecting connections 120 and 121 in the memory cell 10. The overlapping connection 120 connects the input of the first inverter, which includes transistors 110 and 111, with the output of the second inverter, which includes transistors 112 and 113. In addition, the overlapping connection 121 connects the input of the second inverter, containing transistors 112 and 113, with the output of the first inverter, which includes transistors 110 and 111.

Typical circuit element layer STOPV known from the prior art, perform both of the intersection in the same material using the same mask layer. Therefore, the cell circuit STOPV may be similar to the cell 20 in Fig. 2. Crossing 220 and 221 do in the first metal layer scheme. The disadvantage of this scheme 20 cells is that the intersection of 220 and 221 should be placed next to each other, thereby increasing the cell size STOPV.

Fig. 3 depicts another circuit element layer STOPV known from the prior art, in which the two intersections are made in the layer of gate, which is typically made of polysilicon. In this case also, since the intersection 320 and 321 perform on the od of the mu element-layer cell 40 STOPV, known from the prior art, which use a layer of gate along with a layer of local interconnects. Crossing 420 and 421 to be concentrated in the layer of gate, and a connection layer of the gate with the source or drain of the transistor layers perform local interconnects 420 and a-century Layer local interconnects different from the typical metal layer of the first or second level so that the local interconnect precipitated directly on top of the open polysilicon and diffusion plots transistor element. Even in the case of a layer of local interconnects crossing 420 and 421 should be placed next to Each other, thereby increasing the amount of space required for cell STOPV.

From the foregoing description schemes cells STOPV known from the prior art, it can be concluded that it is necessary to provide such a circuit cell STOPV, in which the cell size can be minimized.

In addition, to reduce the manufacturing cost, it is desirable to provide a cell STOPV minimum size that can be constructed using available technological materials, parameters and design rules. Therefore, to implement the desired con is ity of the invention

Below is a description of a semiconductor memory cell with vertically spaced one above the other intersections. The memory cell includes a first transistor inverter having a first input and first output and the second inverter having a second input and the second output. The first and second transistors connected with the first and second intersecting connections. The first cross-connection connects the first input with the second output. The second cross-connection connects the second input with the first output. Two overlapping compounds contain different conductive layers in the manufacturing process of the semiconductor. Two intersecting connection so link vertically one above the other to reduce the space diagram of a memory cell.

Brief description of drawings

This invention is illustrated as an example, but not limitation, in the accompanying drawings, in which

Fig. 1 depicts restarunthealing cell STOPV known from the prior art.

Fig. 2 is a diagram known from the prior art cell STOPV with metal intersections.

Fig. 3 is a diagram known from the prior art cell STOPV with intersections of interconnects "gate-level".

Fig. 4 - zhestkogo interconnects.

Fig. 5 is a construction diagram of one of the embodiments of the present invention.

Fig. 6 is a cross section structure diagram of Fig. 3.

Fig. 7 is a construction diagram of a second variant implementation of the invention.

Fig. 8 is a cross section structure diagram of Fig. 7.

Detailed description

What follows is a description of the structure of a memory cell with vertically spaced one above the other intersections. In this description to ensure full understanding sets out such numerous specific details such as materials, process parameters and the technology of the integrated circuit. But for the person skilled in the art it will be obvious that the implementation of the present invention there is no need to use these specific details. In other cases, in order not to overload the description of the present invention, well-known technological methods or materials not described in detail.

One of the realizations of the memory cell according to this invention contains the design of a 6-transistor cell STOPV with vertically spaced one above the other intersections in the circuit cell. In other words, the main part of one of the intersecting so, the memory cell may contain more or less than 6 transistors, depending on the specific design, and may contain other well-known logic elements, and not the inverter. In addition, the memory cell may include a cell dynamic memory with random access (ZUPU). It is only important that in the memory cell using the crossing, and the crossing to some extent overlap each other vertically.

Fig. 5 illustrates a first variant implementation of the invention. The memory cell 50 includes MOS transistors with a channel of p-type 510 and 513 and the MOS transistors of n-type 511 and 512. The intersection of 520 perform in a metal layer of the interconnect, and the intersection 521 perform in the layer of gate. This arrangement is more clearly shown in cross section in Fig. 6 on line 530 memory cell 50.

Fig.6 depicts the various layers of the memory cell 50. In accordance with the image of Fig. 6 part of the intersection of 620 is located on the intersection 621, i.e., they are "vertically stacked". This vertical arrangement one above the other is possible, because the intersection of 620 is executed in the second metal layer of the interconnect, and the intersection 621 is made in the layer of gate. It should be noted, which transistor elements 510-513 in Fig. 6 is not shown. Methods of designing and manufacturing the MOS transistors are well known in the prior art and described in detail here will not be.

The first layer 600 of Fig. 6 includes a semiconductor substrate. For carrying out this invention, the substrate contains silicon (Si). Or the substrate may contain other well-known semiconductor materials such as gallium arsenide (GaAs).

Top elements 510 - 513 and a semiconductor substrate 600 is protective dielectric layer 601. In one of the embodiments of the dielectric layer 601 contains silicon dioxide (SiO2and formed on the substrate 600 using one of several well known processes chemical vapour deposition (CVD). Or dielectric layer 601 can be formed by a thermal growing.

The top dielectric layer 601 is the intersection 621 containing layer of the shutter. In the layer of gate is the interconnect 622, which connects the gates of transistors 512 and 513. In one embodiment, the implementation of the intersection 621 contains polysilicon, which may be alloyed or unalloyed. Or the intersection 621 contains the sushestvennee crossing 621 also includes a layer of titanium silicide (TiSi2), or another metal or metal silicide having a low resistance layer.

Crossing 621 form a first deposition material of the gate (i.e., polysilicon) according to the method of deposition of the polysilicon, such as one from some well-known CVD methods. After this, a layer of photoresist or other suitable masking material, centrifuged on polikremnii. The photoresist exhibit and manifest to determine items such as the intersection of 621. Polysilicon is etched to create the desired items, and then the photoresist is removed.

The dielectric layer 670 is formed on top of the intersection 621. For one of the embodiments the dielectric layer 670 contains borophosphosilicate glass (BFSS). Or dielectric layer 670 may include a layer phosphorothioates glass (PSG). In addition, the dielectric layer 670 may include a diffusion barrier layer, such as silicon nitride (Si3N4). For one of the embodiments of the dielectric layer 670 is formed by the CVD process. Or dielectric layer 670 is formed by a thermal growing, methods, ion sputtering or deposition by centrifugation on the glass.

The masking material IR then etched according to a well-known etching process, such as reactive ion etching (RIT).

Contacts 630 and b then fill a conductive material. For one of the embodiments the conductive material includes tungsten (W) deposited by the CVD process. Any conductive material may contain other well known contact material, such as aluminum. In addition, the conductive material may be deposited by other methods of deposition, such as sputtering or evaporation. Conductive material may also contain one or more layers of titanium (Ti) or titanium nitride (TiN) to improve the adhesion of the contact material and to provide a diffusion barrier.

For one of the embodiments of the present invention the substrate is polished by chemical-mechanical polishing system to create a smooth surface tungsten or dielectric before performing the following steps.

The first metal layer of the interconnect is then precipitated on the substrate. The first metal layer of the interconnect contains metal conductive paths a, b and C. Conductive track a connects the intersection of 620 with a layer of gate 622, which is the input transistors 512 and 513. Conductive track W Conn is an increase of 620 with the output transistors 510 and 511. One of the first metal layer of the interconnect contains aluminum (A1). Or the metal layer of the interconnect contains aluminum alloy and copper (Cu). As another option, the first metal layer contain one or more layers of titanium (Ti) or titanium nitride (TiN). It should be noted that for the first metal layer interconnects, while remaining within the scope of this invention, it is possible to use other conductive materials having the desired properties (e.g. , low resistivity, convenient formiruemoi and protravlivateli, resistance to mechanical stress and handling).

The first metal layer interconnects formed by one of several well-known deposition methods, including, but not limited to CVD, evaporation or sputtering. After that, the metal wire 640-a-C define the overlay layer of masking material (e.g., photoresist), the creation of the figure and its manifestation, and performing etching of the metal according to well known methods of metal etching. For example, you can use the methods of reactive plasma etching or reactive ion etching. After etching, the photoresist is removed.

ZAT Is) 680. In one embodiment, the implementation layer DSRU 680 contains silicon dioxide (SiO2) and is formed by CVD method. On the dielectric layer 680 then form a picture, and it is etched in accordance with the above, to form holes for through holes a and b. In one embodiment, the implementation layer DSRU 680 then leveled with a method of chemical-mechanical polishing. A through hole a used to connect the intersection of 620 with a metallic conductive track a, thereby connecting the intersection of 620 with a metallic conductive track a, and thereby connecting the intersection of 620 to the input of the inverter, containing transistors 512 and 513. A through hole 6506 connects the intersection of 620 with a metallic conductive track C, thereby connecting the intersection of 620 with the inverter output, containing the transistors 510 and 511.

Through holes a and 650V fill a conductive material such as tungsten (W). Or through holes additionally fill one or more layers of titanium (Ti) or titanium nitride (TiM).It should be noted that for filling through holes a and 650V, while remaining within the scope of this invention, it is possible to use other appropriate method described plating, such as CVD, evaporation or sputtering. For one of the embodiments in order to align the conductive material before performing the following steps apply chemical - mechanical polishing method.

Then in the material interconnects the second level form the intersection of 620. Material interconnects the second level form similar material interconnects the first level. In one embodiment, the implementation of the intersection of 620 contains aluminum (Al). Or the intersection 620 also contain one or more layers of titanium (Ti) or titanium nitride (TiN). It should be noted that for the second metal layer interconnects, while remaining within the scope of this invention, it is possible to use one of several well-known conductive materials. In yet another embodiment, the second metal layer of the interconnect contains a thicker layer of metal than the first metal layer of the interconnect, in order to reduce the resistance of the second metal layer.

A dielectric layer formed above the second metal layer interconnects in accordance with the above methods of deposition of the dielectric. The third metal layer of the interconnect can precipitate SW implementation of the present invention. Fig. 7 - circuit design testiclesstories cell STOPV, similar to the cell 50 of Fig. 5. The memory cell 70 is different from the memory cell 50 so that the intersection 720 in the first metal layer of the interconnect, and the intersection 721 performed in two interconnect and the first interconnect layer contains shutter, and the second interconnect layer contains local interconnect. Interconnect a crossing 721 connects the inverter output, containing the transistors 712 and 713, interconnect W crossing 721. Interconnect W crossing 721 terminates the connection with the input of the inverter, containing transistors 710 and 711.

Fig. 8 depicts a cross section of the memory cell of Fig. 7 on line 730. The substrate 800 and the dielectric layer 801 is similar to the substrate 600 and the dielectric layer 601, and therefore they are formed according to methods described in detail above with reference to Fig. 6.

Crossing 820 contains the first metal layer of the interconnect. Crossing 821 contains two interconnects a and b. Interconnect a contains a layer of local interconnects described in more detail below. Interconnect V form a layer of gate, similar to the intersection 621 Fig. 6. Interconnect V therefore carried out according to the methods, the cat is isoamylene. Layer for local interconnect consists of a conductive material, which is directly on top of a layer of a gate, such as interconnect V, and also on top of the diffusion regions, such as the source and drain of transistors 713 and 712. In one embodiment, the implementation layer for local interconnect contains titanium (Ti). Or layer for local interconnect contains a titanium nitride (TiN) or tungsten (W). Layer local interconnects can comprise one of many well-known conductive materials suitable for use as interconnects devices. The local layer interconnects formed by deposition of conductive material according to a known deposition method, such as ZAPF, evaporation or sputtering. On the conductive material and then create the image (i.e., using the above steps, the photoresist or etching) to create interconnect W.

Interconnect 822 are formed from the material of the bolt and is used to connect the gates of transistors 713 and 714. For one of the options for implementing the interconnect 822 includes polysilicon, and it is formed in accordance with the methods described together with the intersection 621 and interconnect 622 of Fig. 6.

A layer of dielectric material is Odom inverter, containing transistors 712 and 713. Crossing 820 contains the first metal layer of the interconnect, which precipitated and coated according to the methods described above with reference to the first metal layer of the interconnect of Fig. 6. Crossing 820 connects the input of the inverter, containing transistors 713 and 712, the output of the inverter containing transistors 710 and 711. Another dielectric layer precipitated on top of the intersection 820, and can be formed of a metal layer of the second interconnect level (not illustrated). Then you can alternate layers of dielectric and metal. In accordance with the image of Fig. 8 two interconnects a and b contain a third layer of metal interconnects, which can be used to communicate with other circuits (not illustrated).

In the above detailed description describes the design of a memory cell with vertically spaced one above the other intersections. The design of the memory according to this invention is described with reference to specific materials, techniques and design options of the scheme. It should be noted that in the framework of this invention it is possible to produce a variety of replacement and modification.

For example, one is crossed is inane. Many design options depend on the specific technological process of the memory cell. The description and drawings are, accordingly, should be considered rather as an illustration, and not limitation.

1. A semiconductor memory cell containing a first inverter having a first input and first output; a second inverter having a second input and second output, the first intersecting compound containing the first conductive layer, and the specified intersecting the first connection connects the first input with the specified second output and second intersecting the compound containing the second conductive layer, such second cross-connection links the specified second entry with the specified first output and the specified second intersecting connection vertically placed on top of part of the first intersecting connections.

2. A semiconductor memory cell according to p. 1, wherein said first inverter includes a transistor metal - oxide - semiconductor with n-type channel (n-MOS) and the transistor metal - oxide - semiconductor channel p-type (p-MOS).

3. A semiconductor memory cell according to p. 1, great channel of n-type (n-MOS) and the transistor metal - the oxide semiconductor channel p-type (p-MOS).

4. A semiconductor memory cell according to p. 1, characterized in that the said intersecting the first connection includes a first interconnect that includes a layer for local interconnect and a second interconnect that includes a polysilicon layer.

5. A semiconductor memory cell according to p. 1, characterized in that the second conductive layer precipitated on the dielectric layer and the second conductive layer contains metal layer.

6. A semiconductor memory cell according to p. 1, wherein said first conductive layer includes a layer of gate.

7. A semiconductor memory cell according to p. 1, wherein said first conductive layer includes the first metal layer and the second conductive layer contains a second metal layer, and these first and second metal layers have a dielectric layer located between them.

8. Semiconductor cell under item 1, characterized in that the first cross-connection contains a material selected from the group consisting of polysilicon, titanium, titanium silicide, titanium nitride and tungsten is titanium nitride.

9. A semiconductor memory cell that contains a first logic element having a first input and first output, the second logic element having a second input and second output, the first cross-connection connecting said first input with the specified second output, with the specified intersecting the first connection includes a first conductive layer specified semiconductor memory cell and the second cross-connection connecting the specified second entry with the specified first output and the specified second intersecting connection includes a second conductive layer specified semiconductor memory cell, and the main part of the specified second intersecting connections vertically overlaps the specified intersecting the first connection.

10. A semiconductor memory cell according to p. 9, characterized in that said first logical element contains the inverter with complementary structure of metal - oxide - semiconductor (CMOS).

11. A semiconductor memory cell according to p. 9, characterized in that the second logical element contains the inverter with complementary structure of metal - oxide - semiconductor (CMOS).

12. Semiconductor cell provaznikova the memory cell under item 9, characterized in that said first conductive layer contains an element of local interconnects and the element interconnects the gate.

14. A semiconductor memory cell according to p. 9, characterized in that the second conductive layer precipitated on the dielectric layer and the second conductive layer contains metal layer.

15. A semiconductor memory cell according to p. 9, wherein said first conductive layer includes the first metal layer and the second conductive layer contains a second metal layer, and these first and second metal layers have a dielectric layer located between them.

16. A semiconductor memory cell according to p. 12, wherein said first conductive layer includes polysilicon.

17. A semiconductor memory cell according to p. 13, wherein the specified element of the local interconnect contains a material selected from the group consisting of titanium, titanium nitride and tungsten.

18. A semiconductor memory cell according to p. 14, characterized in that the said first and second conductive layers contain aluminum.

19. The schema element is the layer of semiconductor memory cells, soderzhashchii output, scheme intersecting the first connection for connecting the specified first input and the second output and the scheme of the second intersecting connection to connect to the specified second input and the first output, and the main part of the scheme of the second intersecting connection is located at the top of the scheme intersecting the first connection.

20. The circuit element layer under item 19, characterized in that the above scheme of the first inverter includes transistors with complementary structure of metal - oxide - semiconductor (CMOS).

21. The circuit element layer under item 19, characterized in that the above scheme of the second inverter includes transistors with complementary structure of metal - oxide - semiconductor (CMOS).

22. The circuit element layer under item 19, characterized in that the above scheme intersecting the first connection includes a layer of gate.

23. The circuit element layer under item 19, characterized in that the above scheme intersecting the first connection layer contains local interconnect layer and the gate.

24. The circuit element layer under item 19, characterized in that the above scheme of the second intersecting compound contains metal layer.


 

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