Restore device synchronization for synchronous digital hierarchical data transmission system

 

(57) Abstract:

Restore device synchronization is intended for use in the separation device in the transmission system SDH data and uses the data bit alignment, not the pointer to modify the recovered clock signal and generating a sync signal to restore synchronization. The invention achieves the technical result consists in ensuring the ability of users of a third party, using its own clock source for the main speed data transfer sync fundamental frequency in SDH networks. 3 C. p. F.-ly, 2 Il.

The present invention relates to a device restore synchronization for use in a synchronous digital hierarchy SDH) the data transmission system. In particular, the invention concerns a device by which third parties wishing to use SDH communication line, which is under the control of another operator can transmit a signal of self-synchronization and other information in such a network.

Sync third party set when the signals synchronisation source, used to synchronize SDH networks. Synchronization of a third party is therefore plesiochronous with respect to the clock signal of broadband data transmission channel.

In SDH networks, the signals of the fundamental frequency are displayed in the synchronous transfer modules (STM-N) with high bit rate at the insertion point network using virtual drives (VC) and subordinate units (TU), the size and type of which depends on the data rate of the transmitted signal. Many of these subordinate units are combined together in a single module synchronous transfer. At the point selection module synchronous transfer demultiplexed and displayed back to the main signals transmission speed. However, the signals are subject to phase and frequency distortions that affect the quality of the signal, which is used to transmit clock information. A key component in SDH systems used to reduce these distortions, is the so-called desynchronization, or restore device synchronization.

The present invention is directed to improvement of the system disclosed in the patent application in the UK 91148411 published under N GB 2257603A 13 January 1993. Saracastic synchronization to the primary transfer rate, to transmit synchronization information on the SDH network used by the first party. Currently this is not possible and, as shown in Fig. 1B the above document requires a separate channel for the transmission of synchronizing information.

In the above-mentioned document to restore synchronization is used as a data pointer and data alignment bits or none of such data, and synchronization is provided at the output of the main transmission rate under the assumption that the main signal transmission speed synchronized with the broadband data transmission channel. The applicant has found that if the data alignment bits are used without a data pointer, the SDH network can be adapted to the transfer of such synchronizing information with third parties without providing a separate channel.

The invention proposes a device restore synchronization for synchronous digital hierarchy SDH) transmission system data, providing the opportunity for third parties to use SDH channel containing the input (5) for receiving multiplexed signal module synchronous transmission scheme (20) restore synchronization to vosstanovleniya signal module simultaneous transmission of many signals subordinate units, the processor pointer (25) to read the data pointer from the signal of the subordinate units, the device address bits alignment (28) to read data alignment bits from the signal of the subordinate units, the buffer storage device (30) with a monitor (34) of the storage device. In the specified storage device (30) are temporarily stored data processor subordinate units, before they are synchronized with the recovered clock, and the specified device recovery synchronization differs in that it includes means (32) to generate a restored signal synchronization (31), which includes three input phase adjustment (1,2,3), which are connected with the CPU (25) pointer device address bits alignment (28) and monitor storage device (34), respectively, using only a few data fix bits alignment generated by the device address bits alignment (28) (input 2 phase adjustment) for modification of the recovered clock signal (23) and generating the recovered clock signal (31).

A variant embodiment of the invention will be described using the example can be used by the user as a third party, and

Fig. 2 is a block diagram illustrating restore device synchronization performed in accordance with the invention.

SDH-network (Fig. 1) contains a synchronization source 1 network, which sends a signal, for example, a frequency of 2 MHz, the device exchange PBX 2. Exchange device 2 sends a signal with a speed of 2 Mbit/s on the N signal outputs 3 (there are two) associated with SDH multiplexer 4. Multiplexed STM-N signal is then passed through a broadband SDH channel 5 in SDH demultiplexer 6. Exchange device 2 is also connected to the SDH multiplexer 4 via the control line 7, which synchronizes broadband SDH-5 channel with synchronization frequency 2 MHz. In the demultiplexer 6, the signal is converted back to the format of the main transmission speed of 2 Mbit/sec and fed through line 8 in exchange device 9. Line 10 corresponding to the line 7, is used to obtain synchronization information from the broadband channel.

In addition, using the restore device synchronization, which will be described, the user of the third party can use the SDH network for the transmission of synchronization information and other data from the private network 11. The synchronization source 10 castasegna main transmission rate of 1.544 Mbit/s or 2.048 Mbit/sec on channel 12 in SDH multiplexer 4. After demuxing clock signals are transmitted through the channel 13 in the private network 14. You can see by comparing Fig. 1 with Fig. 1B in the above-mentioned patent application in the UK that synchronization information from a third party device prior to the present invention, was transmitted on a separate channel.

In Fig. 2 more shows demultiplexer 6 together with the device in timing or restore device synchronization. Multiplexed STM-N signal is first supplied to the circuit recovery synchronization 20, in which the so-called clock signal THAT is fed to the line 23. Then the combined signal is sent to the demultiplexer 21, where it is divided into N signals of low order are designated as data TU-11 or TU-12 depending on the repetition rate of the bits of the signals of the main speed (1.544 Mbit/s or 2.048 Mbit/s, respectively). Each of the N signals, base speed 22 then goes on restore device synchronization. Although shown only one such device for one demultiplexer, in practice there must be a separate device for each of the N channels 22. Data TU subordinate unit is of high order, and its function is to interpret the differences in phase and frequency between the synchronization signals at the entry point and the exit point of the SDH network, which is encoded by the index of subordinate units. "Pointers" are described in more detail in the above-mentioned patent application in the UK. Essentially, each virtual drive or VC signal has the opportunity to be in the merged stream of bytes, so the starting point of the virtual drive in General SDH signal can be changed for successive frames. The value of the pointer determines the starting point of a specific virtual drive. The processor 25 of the pointer, in addition, receives the enable signal on line 26, which functions as a dynamic flag to indicate whether the data in any specific TU-signal is true or valid data, or refer to the service (unproductive) data.

After processor pointer obtained data of the virtual storage device is transmitted to the device address bits alignment 28, which forms part of the service channel data low order.

Bit alignment defined by the CCITT standards. In essence, the data alignment bits provide the medium is the point of entry into the system may be more data traffic, than it can be placed in the byte space designed for this purpose. Any data overflow can be accommodated in an additional byte alignment. Alignment bits are used to obtain the indication that the data traffic is accommodated in an additional byte alignment, and that they must look before the signal could be sent for further processing. After removing bits of the alignment of the remaining data is provided in the "elastic" storage device 30, which are absorbed temporary phase transients due to gaps caused by the selection official (optional) byte and byte alignment. The main signal speed 29 with the recovered synchronization tool, which will be described, and then read from the "elastic" storage devices along the lines of 8 or 13 (Fig. 1).

Scheme phase-locked loop (PLL) 32 receives as input the reference signal synchronization THE broadband channel, restored device 20, and outputs a modified clock signal readout for the use of data from the recovered synchronization of the "elastic" storage device detuning frequency 32 has three input phase adjustment 1, 2 and 3. They are connected to the CPU 25 of the pointer device correct alignment bits 28 and the monitor 34 of the storage device, respectively. The choice of a particular combination for use is controlled through the mode selector 36, which controls the corresponding switches for each of the inputs of the phase adjustment.

The operation of the circuit will first be described in normal operation, i.e. without the involvement of a third party. In the first mode select input 1, and monitor the storage device 34 is adjusted to ensure that the "elastic" storage device 30 remains half full, so the speed output data from the storage device, was equal to the speed at which they are received by the memory device. Thus, the clock signal for the main transmission speed can be reproduced exactly.

In the second mode are selected inputs 1 and 2, and input 3 is blocked. In this mode, the signal recovered synchronization broadband on the line 23 is used directly with the phase adjustment performed by the CPU 25 of the pointer and device address bit alignment 28.

When shown RETA hand, none of the above modes can not be used. The operation of the above-mentioned device of de-produces adjustment of the pointer subordinate units, leading to a phase transition, is approximately equal to 3.5 μs for one pointer, the output of SDH network. With proper design desynchronization be the speed limit "care" of this phase due to the restrictions of the corresponding frequency shift device PLL of desynchronization. This restriction phase usually takes the form of a narrow bandwidth PLL, resulting in close proximity to the settings of the pointer opposite polarity, mutually kompensiruetsja and not providing the resulting impact on the final output signal. However, setting the pointer to the opposite polarity, not separated by a large gap (greater than the time constant RC PLL) will not be mutually compensated.

In synchronized SDH networks changes of pointer TU-1 will take place in the slowly changing factors such as temperature effects in optical fibers and in the multiplexer.

Although the equipment basically allows such phase jumps, the input signals (PDH) transmission, using only the alignments of bits, with a permissible deviation of less than 1 μs. The invention provides means by which the effects of changes of pointer TU-1 can be eliminated, resulting in the output of the phase response of desynchronization comparable with the phase response of the device to correct the alignment bits.

In the third mode of operation for use when restoring synchronization for base speed for third parties, the selector 36 mode is that in the normal operation mode, a third party uses only input 2, so only use these address bits equalization for frequency synchronization. Although in the drawing the input 1 is shown as off, in an alternative embodiment, the PLL can operate in response to signals from configuration 1, but compensating for each occurrence signal settings equal magnitude and opposite polarity. Thus, the operation similar to the PDH-demultiplexer. As a precaution input 3 can also be used, but the monitor 34 of the storage device and the "elastic" storage device are different, as will be described below.

Until SDH Ciu, performed for the main signal speed. In fact, any temporary loss of synchronization or large values of drift in the SDH network will be resolved in the "elastic" storage device 30. Permitted in a relatively wide limits, usually more than 40 μs, for the settlement of the maximum allowable drift in SDH channel. If synchronization of SDH network is lost for a long period of time, the result may be failure to complete or overflow "elastic" storage device 30. The monitor 34 of the storage device will then initiate the "maintenance" phase to restore capacity "elastic" storage device 32. Thus, the monitor 34 of the storage device works excellent method compared to the method described for the normal mode, or without the use of a third party. Alternatively, the capacity can be restored through a temporary replacement the operation of the timing on one of the first two modes, i.e., using only monitor memory device input 3 or setup using 1 and 2 for a limited period of time.

1. Restore device synchronization for singhroy channel synchronous digital hierarchy system, contains the input for receiving the multiplexed signal module synchronous transmission scheme of the recovery clock signal for recovering the synchronization signal from the signal module synchronous transfer, a demultiplexer for de-multiplex signal module simultaneous transmission of many signals subordinate units, the processor pointer to read the data pointer from the signal of the slave device address bits alignment for the read data bit alignment signal from the slave unit, a buffer memory device with a monitor, a storage device, and a storage device that temporarily stores data processor before they are synchronized with the recovered clock, characterized in that it contains a means of generating, designed to generate a restored signal synchronization, and a means of generating includes three input phase adjustment, which are connected respectively with the processor pointer device address bits alignment and monitor storage devices, and only the read data bits of the alignment generated by the device strangeness and are used to signal changes of the recovered synchronization and generate a restored signal synchronization.

2. Restore device sync p. 1, wherein the storage device is "elastic" storage device, and restore device synchronization device phase-locked loop having an input from a monitor memory for test conditions neosupreme and overflow of the storage device and to perform adjustments to the signal recovered synchronization so as to maintain storage capacity.

3. Restore device synchronization under item 1 or 2, characterized in that the signal recovered synchronization is modified in the second mode, using as data bit alignment and pointer data to generate a restored signal synchronization.

4. Restore device sync p. 2, characterized in that the monitor storage device configured to verify that the storage device is filled about half full and to adjust the signal transfer rate of the recovered synchronization to maintain the condition of half-filling.

 

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