Digital frequency synthesizer

 

(57) Abstract:

The device relates to radio engineering, in particular to techniques for digital frequency synthesis, and can be used for meshing frequencies in radio transmitting and radio receiving devices, and sync devices for various applications. The technical result is a simplification of the device while maintaining the range of synthesized frequencies, while reducing requirements for the performance of the phase-shifting adder. The device comprises a storage device 1 of the code, the memory unit 2 amplitudes, d / a Converter 3, a filter 4 low frequency output bus 5 device, reference generator 6, block 7 synchronization, the switch 8, the multiplier 9, the phase-shifting the adder 10, the input bus 11 installation code frequency, the input bus 12 of the code of forming photomanipulating signal, N-1 blocks of the phase shift, N registers 16 and the register 17 of the memory. 1 Il.

The invention relates to radio engineering, in particular to techniques for digital frequency synthesis, and can be used for meshing frequencies in radio transmitting and radio receiving devices, and the devices synchronize different note which contains one United drive code an information input connected to the input bus bar code to set the frequency, clock input - bus reference signal, the phase-shifting adder, a first input connected to the output drive of the code, the second input from the input bus bar code setup phase, a persistent storage device, an input connected to the output of the phase-shifting adder, digital to analog Converter, whose input is connected to the output of a persistent storage device and a low pass filter, whose input is connected to the output of the digital to analogue Converter, and the output from the output bus of the device.

The disadvantage of this digital frequency synthesizer is limited by a high frequency range of the synthesized oscillations. In the famous synthesizer frequency maximum output frequency is limited by the speed of the drive code, because the code at the output of the drive is changed with a frequency equal to the frequency of the reference (clock) generator f0.

Closest to the proposed invention is a digital frequency synthesizer (RF patent N 1689937) containing the drive code, the memory block amplitudes, d / a Converter, low pass filter, the output bus is ha N registers and N phase-shifting adders, where N is the number of channels of the synthesizer, the input bus installation code frequency and the input bus of the formation photomanipulating signal, and the input bus bar code to set the frequency synthesizer connected to the inputs of the code frequency setting N-1 blocks of the phase shift and the input of the multiplier, the output of which is connected to the input of the drive codes, the output of which is connected to the information input register of the first channel and to the inputs of the code phase N-1 blocks of the phase shift, the outputs of N-1 blocks of the phase shift is connected to the corresponding information input registers with the second to N-th, the outputs of the registers 1 through N-th connected to the second inputs of the respective phase-shifting adders, the input bus bar code formation photomanipulating signal synthesizer connected to the first input of the phase-shifting adders whose outputs are connected to the corresponding information to the inputs of the switch, the output of the reference oscillator is connected to the input of the synchronization unit, the first output of which is connected to the synchronization input of the drive code and inputs the synchronization of registers and a group of outputs of the synchronization unit connected to the control inputs of the switch, the output of which is connected to the WMO is estore possible to ensure the formation of codes in each channel of the device, equal NT0(T0=1/f0), and the clock speed of the drive codes decreases in N and is equal to f0/N. Therefore, the output frequency of the synthesizer can be increased N times by increasing the frequency synchronization device f0while maintaining the clock frequency drive operation codes and pitch adjustment of the output frequency fin= f0/R (R is the capacity of codes equal to 2mwhere m is the number of binary bits of memory codes).

However, the disadvantage of this synthesizer is a significant complication of the circuit due to the presence of N multi-digit fusedlogic adders and, as a consequence, a large amount of radio electronic elements for its implementation.

In addition, the performance of this device depends on the performance of the phase-shifting adders, as the time limit for phase-shifting the adders to generate an output code received at the inputs of the switch, of the different channels and varies from T0for the first phase-shifting adder to N-T0for the N-th phase shifting adder. Thus, the efficiency of the device as a whole can only be ensured if the time summation of the first vazodilatatia range of synthesized frequencies while reducing requirements for the performance of the phase-shifting adder.

To achieve this technical result in a digital frequency synthesizer that contains the memory code memory block amplitudes, d / a Converter, low pass filter, the output bus of the device; reference generator block synchronization device, the switch, the multiplier, the phase-shifting adder input bus code frequency setting input bus code of forming photomanipulating signal, N-1 blocks of the phase shift, and N registers, where N is the number of channels of the synthesizer, and the input bus bar code to set the frequency synthesizer connected to the inputs of the code frequency setting N-1 blocks of the phase shift and the input of the multiplier, the output of which is connected to the input of the drive code, and outputs N-1 blocks of the phase shift is connected to the corresponding information input registers with the second through N-th input bus code of forming photomanipulating signal synthesizer connected to the first input of the phase-shifting adder, the output of the reference oscillator is connected to the input of the synchronization unit, the first output of which is connected to the synchronization input of the drive code and inputs the synchronization registers from the first to the N-th and the group of outputs of the synchronization unit connected to the control inputs of the switch, you is entrusted the entered memory register, the synchronization input of which is connected to the first output of the synchronization unit, an information input connected to the output of the first phase-shifting of the adder, and the output connected to the inputs of the code phase N-1 blocks of the phase shift and the information input of the first register, the second input of the first phase-shifting adder connected to the output of the drive code, and the outputs of the registers from 1 to N inclusive are connected to the corresponding information to the inputs of the switch.

Distinctive features of the present invention from the specified prototype are additionally introduced in his memory register, the output of which is connected to the inputs of the code phase N-1 blocks of the phase shift and the information input of the first register, a synchronization input connected to the first output of the synchronization unit of the device, an information input connected to the output of the phase-shifting adder, the second input is connected to the output of the drive code, and the outputs of the registers 1 through N-th connected to the corresponding information to the inputs of the switch.

Due to the presence of these signs code of forming photomanipulating signal (setup code phase) is added to the code memory in each step of his work that poser, and setting it after the drive code. With this construction the device time summation of the phase-shifting adder must not exceed the period of operation of the drive code, i.e., NT0.

The drawing shows a structural diagram of a digital frequency synthesizer.

Digital frequency synthesizer includes a memory 1 of the code, the memory unit 2 amplitudes, d / a Converter 3, the low pass filter 4, the output bus 5 device, reference generator 6, the synchronization unit of the device 7, the switch 8, the multiplier 9, the phase-shifting the adder 10, the input bus 11 installation code frequency, the input bus 12 of the code of forming photomanipulating signal, N-1 blocks 13 of the phase shift, each of which contains a shaper 14 weight shift and adder-calculator 15, N registers 16 and the register 17 of the memory.

The principle of the proposed digital frequency synthesizer as device prototype based on the simultaneous formation of codes of the N points of reference phase synthesized oscillations, discretely shifted relative to each other by a certain amount, and then select the codes of these points of reference phases in a certain sequence at fixed moments of time is et as follows.

On the input bus 11 code frequency setting is set to the encoded value of the synthesized frequency K (code frequency setting). This number is fed to the input of the multiplier 9, the output of which is formed code number equal to KN, where N is the number of channels of the device. When the number of channels N = 2n(n = 1, 2, 3 ...), the multiplier 9 is a shift register that performs the shift operation code K on n discharges in the direction of increasing the code. Drive 1 code with a clock frequency ft= f0/N, where f0the frequency of the reference oscillator 6, accumulates code CP, resulting in its output in every clock time tt= iTt= i/ftwhere i= 0, 1, 2, 3 ... - integers generated code quantity that is proportional to the phase of the synthesized fluctuation. Output drive 1 code code number is supplied to the second input of the phase-shifting of the adder 10. At the output of the adder 10 is formed code number corresponding to the phase of the synthesized fluctuations taking into account the phase shift specified by the code forming photomanipulating of the signal received at the first input of the phase-shifting of the adder 10 to the input bus 12 of the code of forming photomanipulating signal. The output code of the phase-shifting adder 10 receives information on the register 17 from the first output unit 7, the synchronization device, with frequency ft= f0/N corresponds to the output of the register 17. Resulting at the output of the register 17 memory at each clock time ttgenerated code number corresponding to the phase of the synthesized fluctuations taking into account the phase shift of .

Code K frequency setting simultaneously fed to the input of the shaper 14 weight shift N-1 blocks 13 of the phase shift. Shaper 14 weight shift multiplies the code K set the frequency by a constant factor equal to the block number of the phase shift, resulting in his exit codes are formed of the numbers are equal, for each channel, respectively, K, 2K ... (N-1)To that in the adders-solvers 15 are added to the output code phase additional register 17 memory. Thus, at the output of block 13 of the phase shift in the clock time ttformed N-1 code numbers proportional to the phase of the synthesized fluctuations taking into account the phase shift , but shifted relative to output additional code register 17 memory respectively on K, 2K ... (N-1)K

The additional output of the register 17 of the memory and outputs of N-1 blocks 13 of the phase shift is connected to the information inputs of the registers 16. Registries comes to the information inputs of the switch 8 of the N in one.

The switch 8 with the synchronization frequency f0in the sequence specified by the block 7 synchronization, transmits to the output codes in such a way that at time Tt=NT0(the time of one cycle of the drive 1) at its output is formed by a sequence of code numbers corresponding to phase points of the synthesized fluctuation: 0+, K+, 2K+,...(N-1)K+ in the first cycle of the drive, NK+, (N+1)K+, (N+2)K+,...(2N-1)K+ in the second stage, 2NK+, (2N+1)+,...(3N-1)+ - in the third stage and so on, i.e. at the output of the switch 8 in the clock every time t0=iT0, i = 0, 1, 2, 3 ... code output phase synthesized oscillation is changed by an amount equal to the code frequency K, while at the outputs of the drive code 1, the phase-shifting adder blocks 10 and 13 of the phase shift information is changed to the value of NK and only for the time tt= iTt, Tt= T0N

Thus, the clock frequency drive operation 1 of the code blocks of the phase shift of the synthesizer of the proposed devices, and the prototype are the same, and the clock frequency of the phase-shifting adder 10 N times lower than the clock frequency of the phase-shifting the first adder channel device prototype.

From the output of the switch 8 code number, properley fascinosa Converter and makes the transition from counts of the code phase of the code samples synthesized amplitude oscillations, who in the d / a Converter 3 is converted into an analog value, i.e. the voltage corresponding to input codes. Speed signal output from the DAC 3 is smoothed by the filter 4.

In the device-prototype N times reduces the requirement for performance units phase shift. Thus the operating speed of the device is determined by the performance of the phase-shifting adders, because the time limit for phase-shifting the adders to generate an output code received at the inputs of the switch, of the different channels and varies from T0for the first phase-shifting adder to NT0for the N-th phase shifting adder. As a result, the device performance of the prototype is limited by the performance of the phase-shifting adder of the first channel, i.e., its performance can only be ensured if the time summation of the first phase-shifting adder is less than or equal to T0.

The introduction of an additional register 17 memory, connected to the output of the phase-shifting adder 10, reduces the requirement for performance of the phase-shifting adder 10 as compared with the device-prototype N times. Phase-shifting the adder 10 in predlagaet), working on the synchronization frequency ft= f0/N, the summation of the phase-shifting adder 10 becomes equal to the period of clock pulses of the drive code Tt= NT0. In the device-prototype time summation of the phase-shifting adder of the first channel should not exceed T0- period of reference (clock) signal of the reference oscillator 6.

Connection of series-connected phase-shifting adder and additional memory register between the output of the drive code and the input code set the frequency blocks of the phase shift makes it possible to eliminate the need to correct the code phase to phase shift in each of the N channels, and thereby to reduce the number of phase-shifting adders to one, i.e., to reduce N times (N-1) in comparison with the device prototype.

A digital frequency synthesizer that contains the memory code memory block of amplitudes output bus of the device, reference oscillator, the synchronization unit, the switch, the multiplier, the phase-shifting adder input bus code frequency setting input bus code of forming photomanipulating signal, N - 1 blocks of the phase shift, and N registers, where N is the number of channels of the synthesizer, and the input bus is the input of the multiplier, the output of which is connected to the input of the drive code, and outputs N - 1 blocks of the phase shift corresponding to the information inputs of the registers with the second through N-th input bus code of forming photomanipulating signal synthesizer connected to the first input of the phase-shifting adder, the output of the reference oscillator to the input of the synchronization unit, the first output of which is connected to the synchronization input of the drive code and inputs the synchronization registers from the first to the N-th and the group of outputs of the synchronization unit connected to the control inputs of the switch, the output of which is connected to the input of the memory unit amplitude, the output of which is connected to the output of the synthesizer, characterized in that it additionally introduced a memory register, the synchronization input of which is connected to the first output of the synchronization unit, the information input to the output of the phase-shifting adder, and the output to the inputs of the code phase N - 1 blocks of the phase shift and the information input of the first register, the second input of the phase-shifting adder connected to the output of the drive code, and the outputs of the registers from the first to the N-th inclusive are connected to the corresponding information to the inputs of the switch.

 

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