Synthesizer with variable frequency, the method of synthesis frequency signal synthesizer and the phone

 

(57) Abstract:

The invention relates to the field of frequency synthesis and can be used in the frequency synthesizer with a fractional value of the division factor. Technical result achieved is to reduce the level of spurious signals. Synthesizer with variable frequency contains many accumulative adders latching means for differentiation and the frequency divider. In the method of synthesis frequency signal to an adjustable frequency synthesizer to form multiple integrated alarms, migrate, differentiate signals transfer, combine the differentiated signals and signal transfer for signal variable voltage divider which is fed to the frequency divider. The phone contains a radio receiver for receiving radio frequency signals, a radio transmitter for transmitting radio frequency signals, a controller, means for generating a signal of the local oscillator for a radio receiver and signal transmission for a radio transmitter, means for generating a timing signal, an oscillator with variable frequency to generate the output signal, frequency divider, phase comparator, the network accumulative adders, online is atorm frequency, and more specifically, to the frequency synthesizer with a fractional value coefficient dividing N, using many accumulative adders in a configuration pins and sequential recombination. This configuration accumulative adders with stoppers operates synchronously and allows the system to operate at higher frequencies than the system with ripple, thereby reducing the level of spurious signals.

Prior art

Frequency synthesis using phase automatic frequency control) is a well-known method of generating one of the many related signals using a controlled voltage oscillator (VCO). In a separate system control output signal from the VCO is fed to a programmable frequency divider.

This programmable frequency divider provides the division on the selected integer, giving the signal of divided frequency to the phase detector. The phase detector compares the signal of the divided frequency with the reference frequency signal from another oscillator fixed frequency.

Any phase difference between the divided signal frequency and a reference signal outputted from the phase detector chere is that so to the phase error between the frequency divided signal and the frequency of the reference signal was minimal. As a programmable frequency divider divides only at integer time step size output frequency is limited to a value equal to the frequency of the reference signal. When a single system of control necessary to achieve a compromise between the conflicting requirements of the time synchronization system, the step size, the noise characteristics and the generation of spurious signals.

To overcome these limitations of a single scheme of the HRA have been developed programmable frequency dividers capable of division, not integer. The resulting step sizes output frequency, which are shares of the reference frequency signal while maintaining a high reference frequency and wide bandwidth of this circuit.

Analysis of the synthesis frequency with a fractional value of the division factor N can be found in U.S. patent No. 4 816 774. In the solution according to this patent uses two accumulating adder for modeling characteristics of the synthesis with a fractional value of the division factor of the frequency. This modeling involves switching between the various goals of divisors without concomitantly the two accumulative adders reduces unwanted spurious signals due to their mutual destruction and troubleshoot network filter.

Therefore, the frequency of the reference signal for the synthesizer with a fractional value of the division factor of the frequency N is determined by the step size output frequency VCO, multiplied by the denominator of the divisor of this programmable frequency divider.

Synthesis frequency with a fractional value of N allows the use of the reference frequency, which is much longer than the actual distance between the channels, and allows you to use in the construction of wider bandwidth by reducing the low-frequency spurious signals. Wider strips allow you to have a little time synchronization and the possibility of application of the broadband modulation to the input reference signal or to the schema of the fractional division.

However, this system is not perfect and generates some spurious signals at the frequency corresponding to the distance between the channels. The frequency of the desired output signal is higher than that in the system with netralnym division factor, but still not sufficient for some high-quality systems.

To minimize the effect of spurious output was developed synthesis system with fractional value of N consisting of a set of accumulative adders. Systems carry these parasit the systems, having more than two accumulative adders, this advantage can be greatly increased.

The example proposed in US patent N 5070310. The US patent N 5070310 offers the transmitter, use a synthesizer with a fractional value of the division factor N, which receives a digital number from the set of bits from the controller to select the frequency of the working signal. Synthesizer with a fractional value of the division factor N divides the frequency of the working signal using a divider automatic frequency control system. The divider automatic frequency control system has a variable divisor controlled managing input signal to generate a feedback signal for comparison with a reference signal.

Some of these systems with many accumulative adders require to accumulate adders implemented "pulsation" of the data.

In particular, each time a synchronizing pulse these data shall act on all digital network. As a result, this leads to a relatively low upper frequency limit of operation for mnogosolitonnykh systems, determined by the propagation delays in digital circuits are used to build the system. Finally, some known mnogomotornye system still skoleni to be reduced for the correct operation of many systems.

Disclosure of the invention

The present invention relates to a variable frequency synthesizer containing at least two network accumulative adders in combination with clamps, which recombine consistently. These networks accumulative adders in combination with clamps take a digital number that is used to form the modified divisor.

The oscillation frequency of the oscillator with a variable frequency controlled by the frequency division of the output signal at a variable divider network frequency divider that generates the intermediate signal. This intermediate signal is compared with a reference signal, generating a first error signal indicating the phase difference between the two signals. This first error signal is input to the variable frequency oscillator as the control signal of the variable frequency oscillator.

The first network accumulative adders generates passing through the latch output signal and the output signal of the first transfer, representing the integral of this digital number.

The second network of cumulative adders generates second through latches the output signal and the output signal of the second transfer cableways adders in combination with latches generates a third, passed through latches the output signal and the output signal of the third transfer, which represents the integral of the second transmitted through the latch output signal.

These three output signal of the transfer is then combined to form signal AC motor. The third output signal transfer differentiated and combined with the output signal of the second transfer, forming the fifth output signal. This fifth output signal is then differentiated and combined with the output signal of the first transfer, forming the signal of the variable divider. Signal of the variable divider is input to the network frequency divider.

Brief description of drawings

The invention is further illustrated by examples of its implementation with reference to the drawings, in which:

Fig. 1 depicts a block diagram of a variable frequency synthesizer.

Fig. 2 is a General block diagram of the network accumulative adders (with sequential recombination) synthesizer with a fractional value N in accordance with the present invention.

Fig. 3 - network accumulative adders in combination with the holders in accordance with the present invention.

Fig. 4 - network accumulate summatory brakes with dual delayed in accordance with the present invention.

Fig. 6 - network accumulative adders in combination with the clamps with a single delay in accordance with the present invention.

Fig. 7 - network accumulative adders in combination with clamps with double delay, with correction of residual errors in accordance with the present invention.

Fig. 8 - network accumulate batteries in combination with the clamps with a single delay in an alternative form in accordance with the present invention.

Fig. 9 is a block diagram of radiopropagation, which can be applied to the present invention.

Fig. 10 is a diagram of a typical accumulating adder, coupled with the latch in accordance with the present invention.

Fig. 11 is a graph of curves illustrating the dependence of attenuation on frequency in each term of the transfer function of the system in accordance with the present invention.

The best option of carrying out the invention

The preferred embodiment of relates to the use of the synthesizer in radiopropagation. The specified synthesizer refers to the type of synthesizer with a fractional value N. In the synthesizer uses multiple accumulate adders in combination with fixedratio combined sequentially to generate an output data signal, which is used as a variable divider of the synthesizer.

The basic block diagram of apparatus 901 containing radiopropagation shown in Fig. 9. Preferably, this phone was a digital radio telephone used in a radiotelephone system. The output signal of the synthesizer 903 is used by the receiver 905 and transmitter 907 to generate the local oscillator and signal transmission, respectively.

Control functions the transceiver 900, such as the signal transmission operating frequency, are the control logic circuit 909, which delivers it to the input of the first accumulating adder with fractional value of N is contained in the synthesizer 903.

Fig. 1 is a generic block diagram of a variable frequency synthesizer with a fractional value N. Oscillator with variable frequency or VCO 113 provides a signal 119 with the desired input frequency, and supplies it to the input circuit 111 divisor variable digital frequency. The output signal 125 scheme divider variable digital frequency is input to the comparator 109 phases.

The second input of the comparator 109 phase is a signal 115 of the reference oscillator. The output signal 121 of the phase comparator is fed to the control input of the VCO 113 so, chcemy 111 of the frequency divider, to align this frequency with the frequency of the reference oscillator 107.

In the prior embodiment, the division ratio N of the circuit 111 dividing the frequency varies in a periodic sequence so that the signal 119 to the output frequency of the VCO 113 can be adjusted by steps of frequency equal to the frequency of the reference oscillator 107. This periodic sequence generated by the network 101 many accumulative adders and is controlled by the signal 103 input data.

In a preferred embodiment, the configuration accumulative adders in combination with the clamps, as shown in Fig. 10, used in all networks accumulative adders. Another, equally sufficient configuration accumulative adders can be applied by any person skilled in the technical field.

Here, the signal 1001 output of each accumulating adder is a trigger output conventional trigger circuit 1003. A cascade connection of such accumulative adders will give a delay of one adder for each cycle synchronization clock signal 1005.

This structure allows to delay the output posledovatelnoy sequence accumulating adder of the next lower order.

In other embodiments, execution can be used to accumulate the adders in combination with the clamps that secure the output signal 1011 transfer and output signal 1001 data.

Fig. 2 is an illustration of the type of network accumulative adders used in the present system. In this network uses many accumulative adders with stoppers and sequential recombination, which provides simplicity of design and the ability to directly add the bias frequency DC to the exit 229 (D0) of data.

The output signal of the frequency offset or the input data 215 (D1) is input from the pattern selection frequency contained in the logic 909 control in Fig. 9, and is applied to the first running of the adder 201 (Fig. 2). Said first accumulating adder generates input signals 217, 235, which represent the integral of the signal 215 of the input data.

The output signal 217 data is input to the second accumulating adder 203. The output signal 235 transfer directly summed with the signal of the differentiator 213, resulting in an output signal 229 data. This output signal 235 transfer can directly transfer bias CSF adder 203 is input to the third accumulating adder 205, similarly, the output signal 221 of this third accumulating adder 205 is input to the fourth accumulating adder 207.

The output signal 223 transfer of the fourth accumulating adder 207 is differentiated and combined with the output signal 231 transfer from the third accumulating adder 205, creating a signal 225. Signal 225 is fed to the input of the second differentiator 211, this resulting signal is combined with the output signal 233 of the second transfer from the second accumulating adder 203. The resulting signal 227 is input to the third differentiator 213.

The scheme shown in Fig. 2, is used as a generic description of the synthesis frequency fractional-N value and sequential recombination. Forms of execution of this General method is illustrated in the following drawings in Fig. 3, 4, 5, 6, 7 and 8. Fig. 2 given without fixed output signals or digital delays, has limited practical value.

Fig. 3 is an implementation of the synthesis frequency fractional-N value and sequential recombination, illustrated in Fig. 2. This implementation contains the delay signals and accumulate the adders in the op is accumulating adder to the next running the adder only for one cycle synchronization.

These data will never be released from the first accumulating adder the third running of the adder during one synchronization cycle, thanks to eliminating the problem of "ripple" through all accumulate adders within one heartbeat. These accumulate adders included in combination with clamps, provide synchronization to the network 101.

The effect of "ripple" is an accumulation of delays inherent in the circuits used to implement a particular design. Pulsating accumulate adders limit the possible number of accumulative adders in a given network accumulative adders, creating a fixed frequency synchronization and digital delay circuits.

In a synchronized system, each function has a fixed delay in one synchronization period. This synchronized system captures data of each function, so the data is delayed by one function during each synchronization period. Thus, the system of accumulating many adders can operate as fast as the system consisting of only one accumulating adder.

Online, proil Rica three adders 309, 311, 313 due to internal digital delay. Specified cumulative delay of three adders 309, 311, 313 missing in variants of execution according to Fig. 5 due to the summation of fixed delays between these adders.

In a preferred embodiment, the clock signal is generated from the output signal 125 network 111 of the frequency divider, and Vice versa, this clock signal may be generated from the output signal of the reference oscillator 107.

In a preferred embodiment, the adders are used with the clamps, because the system is digital. However, according to the present invention can be designed analog equivalent system containing analog integrators.

First accumulating adder 301 performs a digital integration of the input signal 333 data. The output signal 335 is fixed at the first appearance of the synchronization signal. Second accumulating adder 303 performs a digital integration of content recorded accumulating adder 301, effectively creating a double integral of the input data 333.

When the second occurrence of the specified trigger the output of the second accumulating adder Casanova output of the second accumulating adder 303, in fact, creating a triple integral of the input data 333.

The fourth fixed accumulating adder 307 performs a digital integration of the contents of the fixed output of the third accumulating adder 305, actually creating a fourth integral of the input data 333.

The output signal 351 transfer of the first accumulating adder 301 is the fact that the output frequency (PO) VCO 113 has acquired 360ophase error versus frequency of the output signal of the reference oscillator 107. To correct this output signal 229 data is incremented during the next synchronization interval, and the contents of the first accumulating adder 303 is reduced by its own capacity.

This action effectively eliminates one cycle of the frequency of the input signal 125 of the phase comparator, the result of performing the correction phase in 360 degrees in the output signal (PO) 119 from the VCO.

Derivatives 209, 211 and 213 in Fig. 2 is shown in Fig. 3 the combination of the digital delay element and an adder, for example 315 and 309. The derivative is implemented digitally by deducting the previous sample signal and subtracting it from the present sennoga accumulating adder 347 with the output derived from the fourth fixed accumulating adder. The resulting signal 343 is passed through two further means of differentiation.

These digital delay elements allow you to synchronize recombinant output signals of the transfer with the appropriate synchronization cycle. The output signal 351 transfer is delayed by three successive cycles of delay before reaching the adder 313. The output signal of the transfer from the second fixed accumulating adder 349 is delayed by two cycles synchronization before reaching the adder 311.

Off delay one cycle synchronization, introduced the first fixed-storing the adder 301, the output signal of the transfer reaches the adder 311 on the third cycle synchronization. The output of the transfer from the third fixed accumulating adder 347 is delayed by one cycle synchronization since its creation before it is summed in the adder 309. This is one delay occurs after two delays from the first and second fixed accumulative adders, thereby achieving this adder on the third cycle synchronization.

Therefore, the signal of the variable divider 229 has a three cycle delay plus the influence due to polisistem allows you to work with much higher sync speed, followed at a much faster change in periodic sequence, using input 333 of the data.

Sequential recombination of the output signals of these accumulative adders reduces the number of required differentiation network accumulative adders.

In addition to delays, which are shown in Fig. 4, the system can be added additional fixed delay without any associated problems, however, these additional delays do not give any effective advantages of this system accumulative adders.

In Fig. 4 presents a block diagram of the frequency synthesis with a fractional value of N fixed accumulating the adders and sequential recombination. This form of perform network accumulative adders synthesizer similar to that shown in Fig. 3, except for the added delays 423, 429, 437, which are introduced into the circuit output signal 455, 457, 459 transfer the first three fixed accumulative adders.

These elements additional delay added to storing the adders lower order with the purpose of obtaining supramuscular characteristics for the input data and the purpose of receiving the IU to convert the digit (D) - analog (A) and applications to the network filter. One example of the correction patterns of the residual noise is shown in Fig. 7.

In Fig. 7 shows a block diagram chetyrekhsektornoi system such as shown in Fig. 4, in which the information accumulated in a fixed nakaplivaya the adder 407 of the highest order and second order the adder 405, is used for subtraction of a term residual noise in the network filter 711.

This is an internal fixed content accumulating adder 405 once lingers on the element 725 delay and then subtracted from the internal content of a fixed accumulating adder 407 of the highest order in the conventional functions 723 addition. The result is term equivalent to Z-1Q4 output of the adder 723. Where Q4 is term of quantization noise. Elements 721 delay and adder 719 form a chain of digital derivative. The output of the adder 719 will be equal to - Z-1(1 - Z-1)Q4. Delay element 717 and the adder 715 form the circuit of the second digital derivative.

At the output of the adder 715 is the expression - Z-1(1 - Z-1)2Q4. Known d / a Converter 713 then converts this output signal 735 in analog form, predloga filter. The capacitor 729 is used as a circuit for sampling an analog of the derivative to convert the output voltage of the inverter 713 figure is similar to the current, convenient for application to the network filter 711, for which the drive from the phase comparator is a current source. (The current through the capacitor is the time derivative of the voltage).

Therm 733 correction has additional latency compared with the output signal 453 data. This delay is compensated by adding delay 707 to the path of the output data of the divider 703 variable frequency. Therefore, this sequence data divider 703 variable frequency is:

DO = Z-5D1 + Z-1(1 - Z-1)4Q4,

where

DO signal Data Out;

DI signal Data In;

Z-xrepresents the delay period x synchronization in the range of Z-transform.

Since the phase detector 705 compares the phase, not frequency, this signal is actually integrates when passing through the phase detector 705. Therefore, this term phases of the output of the phase detector can be represented in the transformation as:

FCorr= Kf{DIZ-5/ (1 - Z-1) + Q4Z-1(1 - Z-1)3}

where K0there is m 713 figure is similar and the capacitor 729, can be represented in Z-transform as:

FCorr= AD/ACQ4Z-1(1-Z-1)3< / BR>
where AD/Ais the gain of the Converter figure (D) is similar to (A), and C is the capacitance of the capacitor 729.

If the value of the capacitor 729 chosen to be equal to the gain of the phase detector, divided by the gain conversion D/A, is achieved mutual destruction of any of the terms of residual noise. Additional elements 423, 429, 437 added to the output signals of the transfer of the first three accumulative adders 401, 403, 405 to term sequence noise output is dependent only on the fourth accumulating adder 407.

This allows you to easily convert a sequence of noise for use in the Converter of figure-analogue, which corrects the errors on the input axis of the filter. Without these elements of the delay term output noise would include multipliers from all accumulative adders. And it would be difficult to obtain curve correction for this type of output.

The capacitor 729 may be replaced by another form of derivative. For example, additional digital delay and adder placed before the specified Converter figure/resummation 715. For mutual destruction of the gains of the gain of the inverter 713 digit/analog must be equal to the gain of the phase detector 105.

Fig. 5 is a variation of the complete network accumulative adders correction and synthesis, illustrated in Fig. 4. It adds additional delay 523 and 521 on the outputs of the adders 509, 511, respectively. The purpose of these additional delays is to eliminate the effect of "ripple" caused by digital delays within the supply chains of these adders.

As noted above, the output signal of the fourth fixed accumulating adder 507 is input to adder 509 without these digital delay 523 and 521 signal 557 variable divider would have a ripple effect. Adding these delays, eliminates the ripple effect. During the fifth cycle synchronization data will move from the adder 509 to the adder 511. During the sixth cycle synchronization, the data will move from the adder 511 in the adder 513. Thus, only one digital delay will take place during each synchronization cycle. This modification provides faster synchronization cycle.

In Fig. 6 shows a form of execution that contains e is s accumulative adders. An embodiment illustrated in Fig. 6 is similar to the variant according to Fig. 3, with the addition of synchronous sequential recombination.

In a preferred embodiment, the information modulation is applied to mnogokollektornoi digital network 400 accumulative adders synthesis frequency with a fractional value N. This information modulation is the lowest 16 bits of the 24-bit number, the input data 439. Because the transceiver in which the present invention is applied, can be used effectively in a digital radiotelephone system of CSM Pan European Digital Radiotelephone Syctem, rapid changes of frequency modulation, and low-level signals and noises are implemented using a frequency synthesizer with a fractional value n

To modulate the specified synthesizer with a fractional value N use the reference table in order to convert the data stream to be transmitted, in a mixing frequency for the synthesizer with a fractional value N. the Circuit dividing this synthesizer is controlled in accordance with the input data stream for tracking the instantaneous frequency offset that is required for the simulated signal CMSK. This operation can be performed at a frequency of cm the adders locking works with large accumulating the adders to eliminate spurious signals, ensure correction of the converted digit/analog, reduce the level of discrete spurious signals and provide direct digital modulation circuit PLL.

In the CSM system data rate is 270,8333 kbit work with BT, equal to 0.3. Where T is the bit period equal to 1/270,8333 kHz, and B is the base width of the Gaussian filter used to generate the data base strip. The result is the base width of the strip 81 kHz, which should be bypassed with low distortion through the chain of PLL as frequency modulation.

The real parts of the frequency offset signal CMSK changed in the range from 10 Hz to approximately 70 kHz. This range determines the bitness of the accumulative adders, since it is necessary to synthesize the steps with a smaller width than 10 Hz in the preferred embodiment, the system CSM. For the reference frequency of 26 MHz is required accumulating adder with a width of at least 22 bits; in this case were selected 24 bits for ease of use commercially available components.

It is obvious that the desired instantaneous frequency offset in terms of the modulation should be much lower than the cut-off frequency of the top is stuudy fundamental transmitted frequency, resulting from the modulation.

However, when using mnogokollektornoi system solves this problem.

The overall transfer function of the system was previously defined as the following:

DO = Z-5D1 + Z-1(1 - Z-1)4Q4

This expression can be converted back into the frequency range by replacing eiv= Z. as a result we get the following expression for DO. Here we have used the expression for the amplitude term for term.

D0= D1+(2-2cosv)2Q4

In the previous expression, V is the frequency normalized frequency convolution. This frequency convolution equal to half the speed, with which synchronization is accumulating adder.

The curve of the dependence of attenuation on frequency is illustrated in Fig. 11 and shows each term of this expression. DI goes without distortion relative to DO, and each of the terms (Q) quantization noise is passed through a high pass filter.

It is possible and preferable to increase the degree of separation so that all spurious outputs shifted to very low frequencies. The combined effect of using many accumulative adders at high speed synchronization Mae which reduces the frequency of spurious signals, so they are lower than creditibility the level of the upper frequency band-pass filter, formed mnogokollektornoi structure.

Many accumulative adders increases the slope of the curve of the filter of the band pass filter, increasing the speed, move the upper limit frequency of the filter up the frequency scale.

In General, the network 101 accumulative adders generates a time varying the division factor N. for a given N-th order system with a fractional value N accumulate these adders can be used with a recording signal, which leads to a synchronous system in which the pulsation data do not pass through more than one accumulating adder per cycle synchronization.

In the system with a single delay the output of the first or accumulating adder lowest level to the variable divider circuit is delayed by N - 1 units of synchronization, the output of the accumulating adder of the next lower level or second accumulating adder is delayed by N - 2 units, and so on up until the next latest accumulating adder will not be delayed by one unit synchronization, and poses two delays, one unit of additional delay is added to the output of all accumulative adders except the last is accumulating adder or accumulating adder of the highest level.

Due to the synchronous nature of this system it is able to operate at higher frequencies and because of this allows you to have a wider strip of PLL. This provides the quickest time synchronization and broadband digital modulation such fractional divider while maintaining excellent and predictable characteristics of spurious signals.

The digital representation of the remaining errors is obtained in the form convenient for use in the circuit digital to analog conversion. The analog output of this transform is applied to the output of the phase detector for mutual destruction of any residual noise.

Sequential recombination in the circuit 101 accumulative adders, recording the signal provides the opportunity to directly apply phase correction constant current to the output data signal. In addition, such a sequential recombination reduces the number of components required to perform recombination, compared to systems of Pascal's triangle and the like.

Fig. 8 illustrates the implementation of the network accumulative adders with fractional value of N, as illustrated in Fig. 3. This scheme responderit accumulating adder 833, the latch 841, digital delay, 825, 827, a device for combining signals 809 and the differentiator 813. All of this can be shown in the block diagram in Fig. 3.

Additional network accumulative adders can be added in addition to the network 849 to create a network accumulative adders N-th order. When the number of delays in the system with a minimal number of delay between the first accumulating the adder 831 and the adder 807, is equal to N - 1, and the first network accumulative adders having N - 1, the second network accumulative adders having N - 2, and a third network having N - 3, and so on up until there will be no delay, as illustrated in Fig. 8.

In a system with dual delay network accumulative adders will have one additional delay except the last network or networks of higher order.

1. Adjustable frequency synthesizer for frequency synthesizer using frequency synthesis using phase system of automatic frequency and having a diagram of the frequency divider containing the first accumulating adder is latched to integrate the input digital signal to form a first integrated signalin storing the adder latching, to integrate the first integrated signal to form a second integrated signal and the second output signal of the transfer, the third accumulating adder latching associated with the second accumulating the adder latching, for integrating the second integrated signal to form a third integrated signal and the third output signal transfer, characterized in that it contains the first tool of differentiation that includes a delay element and an adder connected to the third running the adder is latched, for differentiation of the third output signal transfer with the aim of forming the first differential signal, moreover, the adder is connected also to the second running the adder is latched to the second summation output signal transferred from the first differentiated signal to form an intermediate output signal, and second means of differentiation, containing a delay element and an adder associated with the first means of differentiation to differentiate the intermediate output signal to form a second differentially is the transformer latching for summing the first output signal transfer with the second differential signal to form a signal of variable divider and connected to the frequency divider.

2. Adjustable frequency synthesizer under item 1, characterized in that the first accumulating adder latching connected with the second means of differentiation through the first delay element for delaying the first output signal of the transfer to the first specified period.

3. Adjustable frequency synthesizer under item 1 or 2, characterized in that the second accumulating adder latching connected to the first means of differentiation via a second delay element for delaying the second output signal of the transfer to the second specified period.

4. Adjustable frequency synthesizer according to any one of paragraphs.1 to 3, characterized in that it contains the fourth accumulating adder latching connected to the first accumulating the adder latching, for integrating the input signal to form a more integrated signal and an output signal of the transfer, a third means of differentiation that includes a delay element and an adder connected to the second means of differentiation, and an adder connected to the fourth running the adder is latched to summarize additional visitor frequencies under item 1, characterized in that it further comprises an adder, connected to the third and second accumulating the adders latching for combining the third and second integrated signals to form a signal correction residual error, and the connection for the signal correction residual errors oscillator with variable frequency.

6. The method of frequency synthesis signal for the controlled frequency synthesizer containing a frequency divider, which is formed from a first integrated signal and the first output signal transfer by integrating the input digital signal, generate a second integrated signal and the second output signal transfer by integrating the first integrated signal, forming a third integrated signal and the third output signal transfer by integrating the second integrated signal, wherein forming the modified signal of the divider, and the phase signal of variable divider to produce the differentiation of the third output signal transfer for the formation of the first differential signal, combine the first differential signal with the second output signage output signal for forming a second differentiated signal, combine the second differential signal with the first output signal transfer for signal conditioning variable divider and a signal of variable divider the frequency divider.

7. The phone contains a radio receiver for receiving radio frequency signals, a radio transmitter for transmitting radio frequency signals, a controller connected to the radio receiver and radio transmitter, to control the radio receiver and a radio transmitter, means for generating a signal of the local oscillator for a radio receiver and signal transmission to a radio transmitter connected to a radio receiver, a radio transmitter and controller means for generating a timing signal, an oscillator with variable frequency to generate an output signal having a selectable output frequency that is a multiple of the frequency of the reference signal, the frequency divider associated with the specified oscillator with variable frequency, to generate an intermediate signal having a frequency equal to the frequency of the output signal divided by the magnitude of the control signal of variable divider, phase comparator, associated with the reference frequency generator and a frequency divider, for comparing the phase of the intermediate signal is al errors are served on the control input of the oscillator with variable frequency, characterized in that it contains the first network accumulative adders for the formation of the first modulation signal for periodic time variations of the control signal of variable divider so that the frequency divider had given average rational value of the divider, and the first network accumulative adders includes a first integrator for integrating the control signal to form a first integrated signal and the first output signal of the transfer, the first circuit latching associated with the first integrator for fixing the first integrated signal at the first appearance of the clock signal and the first delay element associated with the first integrator, to delay the first output signal of the transfer to the third occurrence of the clock signal, the second network accumulative adders associated with the first network accumulative adders to generate a second modulation signal to modify the control signal of variable divider, and the second network accumulative adders includes a second integrator for integrating the first integrated signal to form a second integrated signal is La fixation of the second integrated signal when the second clock signal, the second delay element associated with the second integrator, for delaying the second output signal of the transfer to the third occurrence of the clock signal, the third network accumulative adders associated with the second network accumulative adders to form a third modulation signal to modify the control signal of variable divider, and the third network accumulative adders includes a third integrator for receiving the second integrated signal to form a third integrated signal and the third output signal of the transfer, the third circuit latching associated with the third integrator, for fixation of the third integrated signal when the third occurrence of the clock signal, the first differentiator, associated with the third integrator, for differentiation of the third output signal of the transfer and pooling of third differential output signal transfer with the second detainees output signal transfer with the aim of forming an intermediate output signal, the second differentiator associated with the first differentiator for differentiating the intermediate output signal and combining the differentiated human control variable divider.

 

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EFFECT: reduced rate of call failure in multibeam communication system.

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FIELD: automatic adaptive high frequency packet radio communications.

SUBSTANCE: each high frequency ground station contains at least one additional high frequency receiver for "surface to surface" communication and at least one additional "surface to surface" demodulator of one-tone multi-positional phase-manipulated signal, output of which is connected to additional information input of high frequency controller of ground station, and input is connected to output of additional high frequency "surface to surface" receiver, information input of which is connected to common high frequency receiving antenna, while control input is connected to additional control output of high frequency controller of ground station.

EFFECT: prevented disconnection from "air to surface" data exchange system of technically operable high frequency ground stations which became inaccessible for ground communications sub-system for due to various reasons, and also provision of possible connection to high frequency "air to surface" data exchange system of high frequency ground stations, having no access to ground communication network due to absence of ground communication infrastructure at remote locations, where these high frequency ground stations are positioned.

2 cl, 12 dwg, 2 tbl

FIELD: planning data transfer in wireless communication systems.

SUBSTANCE: proposed method used for planning data transfer over incoming communication line for definite terminals of wireless communication system includes formation of definite set of terminals for probable data transfer, each set incorporating unique combination of terminals and complies with estimate-designed hypothesis. Capacity of each hypothesis is evaluated and one of evaluated hypotheses is chosen on capacity basis.

EFFECT: enhanced system capacity.

39 cl, 12 dwg

FIELD: mobile communication systems.

SUBSTANCE: system contains closed contour, thus expanding similar system with open contour and made with possible use of distancing technology during transfer with four antennas, and method for transferring signal in aforementioned system. Method for transferring signal in system for spatial-temporal distancing during transfer with closed contour, having several transferring antennas, includes: spatial-temporal encoding of symbols, meant for transfer; classification of encoded symbols in appropriate groups; and multiplication by different weight values of each group of transferred symbols and their transmission.

EFFECT: improved quality of communication.

5 cl, 5 dwg

FIELD: radio communications, possible use in space and ground communication systems, using noise-like signals.

SUBSTANCE: at transmitting side device features: first and second transmitter decoders, transmitter counter, first and second transmitter keys, transmitter phase inverter, OR circuit of transmitter, at receiving side device features: first and second receiver decoders, receiver counter, first and second receiver keys, receiver phase-inverter, OR circuit of receiver, first and second gates.

EFFECT: increased concealment of information being transferred.

4 dwg

FIELD: mobile communication system which uses adaptive antenna array circuit with a set of inputs and a set of outputs.

SUBSTANCE: in accordance to the invention, first receiver computes receipt value with usage of compressed signal received from receipt signal, to generate receipt beam of first receiver and computes weight value of transmission with usage of computed weight value of receipt to generate transmission beam of second transmitter, generating check connection information, which includes weight value of transmission. First transmitter transmits check connection information to second receiver. Second receiver receives check connection information, and second transmitter determines weight value of transmission from check connection information received in second receiver, and generates transmission beam which corresponds to weight transmission value, to transmit the signal by applying transmission beam to the signal.

EFFECT: provision of system and method for transmitting/receiving in mobile communication system using two-stage method for creating a weight value.

6 cl, 12 dwg

FIELD: onboard radio-systems for exchanging data, possible use for information exchange between aerial vessels and ground-based complexes in radio communication channels.

SUBSTANCE: complex of onboard digital communication instruments contains two receiver-transmitters of very high frequency broadcasting range, two receiver-transmitters of high frequency range, interface switching block, control block, modulator-demodulator (modem), control and indication panel, frequency-separation device of high frequency range and frequency-separation device of very high frequency range.

EFFECT: increased interference resistance of data, reduced level of collateral radio emissions and fulfilled electromagnetic compatibility requirements.

1 dwg

FIELD: method and device for receiving data in mobile communication system using a circuit for adaptive generation of receiving beam weight.

SUBSTANCE: in accordance to the invention, mobile communications system receives a compressed signal, produced from received signal, and determines first value of error, using first circuit in clock point, and second value of error, using second circuit, which is different from first circuit in clock point. The system determines weight of application of first circuit in accordance to difference between first value of error and second value of error and generates third value of error, using the circuit which combines first circuit and second circuit, and determines the weight of the receiving beam, using compressed signal, third error value and output signal.

EFFECT: realization of the device and method for generation of receiving beam with minimal error value in mobile communications system.

2 cl, 9 dwg

FIELD: information technologies.

SUBSTANCE: invention relates to the radio communications and can be used in wireless communications system. Signals are transmitted with party check code usage with low density. Raise supporting party check matrix with low density is formed with the help of elements value extension in party check matrix with low density with the help of submatrix, which conforms a number of transmitting aerials. Specific transmitting signals are coded with usage of supporting raise party check matrix with low density. After that, coded signals are conversed seria/parallel and transmitted through transmission aerials.

EFFECT: improvement of data jam resistance in channel with noises while high-speed transmission.

36 cl, 16 dwg

FIELD: communication technologies.

SUBSTANCE: detecting techniques for close components of multi-beam distribution are described. The techniques are aimed at prevention of channel merging without relative position monitoring between each of diversity channel set. Displacement limits are defined for each diversity channel. Temporary tracing commands are suppressed. Such commands may displace diversity channels beyond their displacement limits. Displacement limits are dynamically updated, with displacement limits for each diversity channel defined according to displacement limits of adjacent diversity channels.

EFFECT: prevention of diversity channel merging; increase in system efficiency and capacity and decreased improper use of system resources.

12 cl, 10 dwg, 1 tbl

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