A dynamic memory cell

 

(57) Abstract:

The invention of "Dynamic cell" relates to the field of electronics and can be used, in particular, when creating operational and permanent storage devices with high performance. In the cell, the applied induction principle account and there are no clock signals, which increases the reliability of its work in a dynamic random access memory devices and provides technical result achieved. The invention can be used in other discrete logic devices. The cell contains a bipolar transistor, two resistors and a capacitor. 6 Il.

The present invention relates to microelectronics and can be used to create a memory and logic devices of computers.

Known electric circuit of a dynamic memory cell containing a MOS transistor, the source of which is connected respectively to the input bit bus and a storage capacitor connected to the shared bus.

This memory cell is not possible to achieve maximum performance in widely used at the present time dynamic storage devices (DOSE) that structure with biopolar and low specific capacitance of MOS capacitor.

This disadvantage is partially eliminated in the circuit dynamic memory cell containing biopolar dvuhkamernyi the transistor is in saturation or cutoff, the collector through a resistor connected to the power bus, the base to the input bus, and the emitters to the input and clock buses, respectively.

This scheme has a limited speed of ~310-9and reliability requires synchronous clock signal on the clock bus and matches the relaxation time of the charge in the duration of the clock pulse.

The technical effect of this invention is to improve the reliability and speed of the dynamic memory to the level of ~10-10C.

This effect is achieved by the fact that in the scheme of dynamic memory cells containing biopolar transistor, the collector of which is connected to an output bus, the emitter to a common bus, and the base through a capacitor to the input bus and through the additional resistor to a common bus.

To further improve performance, the emitter connected to the common bus via a second additional resistor.

For performance reasons, the emitter connected to the common bus through add the Roux and the additional resistor through the third resistor.

To improve the processability of the capacitor is a diode, the anode of which is connected to the base of the transistor, and the cathode to the input bus.

Below is a description of the present invention with reference to the drawing, on which:

in Fig. 1 shows a diagram of a dynamic memory cell (DAP);

in Fig. 2 shows a diagram of a dynamic memory cell with a second additional resistor in the emitter;

in Fig. 3 shows a diagram DEP with additional source of power;

in Fig. 4 shows a diagram GAP with the third additional resistor on the base;

in Fig. 5 shows a diagram DAP with a diode as a capacitor.

Scheme DAP shown in figure 1, it contains biopolar transistor 1, the collector of which is connected through a resistor 2 to the power bus-3, connected to an output bus with 4 base through the condenser-5 to the input bus-6 and via an additional resistor 7 to the shared bus-8.

In Fig. 2 shows a schematic GAP with the second additional resistor 9 in the emitter.

In Fig. 3 shows a diagram DEP with additional power source-10.

In Fig. 4 shows a diagram DAP with an additional resistor in the base 11.

In Fig. 5 shows a diagram DAP with diode-12 as the condensate is tion of the input pulse (UI) on the input bus-6, as shown in Fig. 6a, is its differentiation using R-C chain, formed by the elements 5 and 7, respectively. The result is two short of the pulse at the base of the transistor (UEB) (see Fig. 6b).

This positive pulse opens the bipolar transistor 1, which is prior to that in the closed state and the open state exceeds the duration of the input pulse (tthemby the amount of time saturation (tusas it can be seen from Fig. 6c.

As you know, tusapproximately determined by the ratio

< / BR>
whereothe lifetime of minority carriers in the transistor;

Ib,Ito- current base, and collector, respectively;

hEthe amplification factor of current in the circuit in a common emitter.

Thus, long dynamic memory cell will "remember" the input pulse during the time tusafter which you want it to repeat (regeneration). The retention time of the information in this case, as in the prototype [2] , is determined by the recombination time of minority carriers, and not the relaxation time as a MOS-capacitor dynamic cell [1].

More the first case uses a MOS transistor, having a high internal resistance compared to bipolar, allowing greater time constant capacity bit bus with a small amount of charge in the information capacitor;

in the second case, the performance GAP is mainly determined by "swinging" tires, which represents a significant capacity, resulting in real VLSI RAM clock speed usually does not exceed 200 MHz.

However, more important is the greater reliability in the present invention, since a significant discrepancy between the clock frequency with a value of Tusin DAP can lead to loss of its health.

The schema shown in Fig. 2, 3, 4, are aimed at further improving the performance GAP by reducing the depth of saturation of the transistor in the circuit of Fig. 3 through the use of resistance negative feedback-9, in the circuit of Fig. 3 due to the additional power source-10, in the circuit of Fig. 4 due to the base resistance-11.

The diagram shown in Fig. 5 shows that DAP able to function in a constructive realization of the capacitor differentiating the chain on the basis of the p-n junction, which greatly simplifies the manufacturing technology GAP, upominalsja (dram) consisting of 12 cells DAP. Each cell contained a discrete circuit elements: transistor - CT-315, resistors ALT-l com%, capacitor K4D9-100 pF.

The device demonstrated its functionality in an unusually wide range of changes in the parameters of circuit elements:

- has a 7 - base transistor in the range of 1 kω to 10 Mω

- capacity-5 - in the range of 10 pF to 200 pF when values of capacitance amiterno and collector transitions transistor CT-315-6 pF and 8 pF, respectively.

the resistor is a 2 - manifold in the range from 1 kω to 10 Mω

- temperature range from -90oC to +250oC

- change the lifetime of minority charge carriers from about 0.5 NS to 10 µs

- gain RE=10 - 300

- supply voltage from 3.5 - 10th Century

A dynamic memory cell, containing the General and the input bus and the transistor, wherein the transistor is made bipolar, its collector connected to an output bus and through a resistor to the power bus, the emitter is connected to the shared bus, and the base is connected through another resistor to the common bus and through a capacitor to the input bus, and the data storage time is determined by the time of recombination of minority carriers, which

< / BR>
where tnector and base, respectively;

hEthe amplification factor of current in the circuit with a common EMR

 

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