Improvemerit generator voltage in a nonvolatile semiconductor memory, the nonvolatile semiconductor memory and method someprogram.exe generate a voltage in it

 

(57) Abstract:

The invention relates to nonvolatile semiconductor memory devices. Improvemerit generator voltage in a nonvolatile semiconductor memory device has plenty of memory elements of the type floating gate, the generator line voltage used for programming the selected memory elements, and the generator programming voltage. The latter is designed to ensure that you have successfully programmed in the selected memory elements or not. The high voltage generator is designed to generate the programming voltage. The adjustment scheme is designed to detect the level of the programming voltage to consistently increase the programming voltage within a specified voltage range each time the selected memory elements are not programmed successfully. The comparison circuit is designed to compare a certain voltage level with a reference voltage with the subsequent generation of the signal comparison. The control circuit generating high voltage is designed to activate the high voltage generator in response to SIO semiconductor memory device, the ability to maintain a uniform threshold voltage of the programmable memory elements. 2 S. and 6 C.p. f-crystals, 12 ill.

1. The scope of the invention

The invention relates to a nonvolatile semiconductor memory device and, more specifically, someprogram.exe circuit in the nonvolatile semiconductor storage device.

Art

A matrix of memory elements with logical NAND (AND NOT) structured elements has many NAND blocks of elements that are organized into a matrix with columns and rows. Fig. 9 is an equivalent circuit diagram showing part of a matrix of memory elements with the standard logical AND structured elements. According to the figure, each of the logic elements AND NOT many logical elements NU1-NUmhas a first transistor selection 120 with its drain connected to the corresponding bit line and the second transistor selection 121 with its source connected to the common bus source CsL. Stock-ishikawae channels of the transistors M1 and M2 of the memory elements (hereinafter referred to as "memory elements") connected in series between the source of transistor 120 of the first selection and the drain of the transistor 121 of the second selection. The gates of transistors 120 of the first allocation, the control gates of the elements and WL1-WL8 and bus SL2 of the second selection respectively. The transistors of the first and second selection 120 and 121 and the memory elements M1-M8 are formed in the potential well of P-type formed on the main surface of a semiconductor substrate. Itokawa-stock General area between the source of transistor 120 of the first selection and the drain of the memory element M1, Itokawa-stock General area of the memory cells M1-M8, and stock-estochowa the General area between the drain of the transistor of the first selection 121 and the source of the memory element M8 formed in the potential well of P-type. The floating gate electrode made of polycrystalline silicon, is formed on each channel of the memory cells M1-M8 through the tunnel oxide layer and the floating gate electrode made of polysilicon or silicide of a metal with a high melting point is formed through the intermediate insulating layer. Stock the area of the transistors 120 of the first selection, educated in the potential well of P-type, respectively connected with the corresponding bit of the tires, made of metal silicide with a high melting point, or through Windows in the metal, stockbee the field effect transistors of the second selection 121 formed in the potential well of P-type, connected with bus CSL common source, made of silicide what mirovanie, i.e. the data record.

The cleanup operation of the memory elements produced by application of the cleaning voltage of about 20 V to the area of the potential well of P-type, i.e. the voltage of the ground to a numeric tire WL1-WL8. With the emission of electrons existing in the floating gates, in the region of the potential well of P-type tunnel through the oxide layer of the memory elements is converted into a mode transistors enrichment. It can be assumed that cleared the memory elements store data "1".

The operation of programming the memory cells connected to the selected digital, i.e., the write operation of data "0" is produced by applying a programming voltage of about 18 V to the selected numeric bus and the reference voltage, i.e. the voltage grounding Vssto the sources and drains of the memory elements, in which the recorded data is "0". Then the floating gates of the memory cells that will be programmed to accumulate the electrons through the tunnel oxide layers, and these memory elements are converted to the transistors of the depletion mode.

After programming the operation verification program to verify that you have successfully programmed in the selected memory elements to have Zadunaisky in Korean patent application No. 94 - 18870, published on 19 August 1994 and owned by the present applicant.

Since the capacity of the EEPROM has become highly integrated, the size of the memory element, such as the width and thickness of the oxide layer of the gate width and length of a channel region of decreased. However, the variability of the manufacturing process cannot guarantee the uniformity of the width and thickness of the gate oxide layer, the intermediate insulating layer and the channel region. This makes the threshold voltage of the programmed memory elements are unequal. If at least one of the programmed memory elements does not reach the desired threshold voltage, it shows the error data. In order to solve the problem, it was proposed device verification program to verify that you have successfully programmed in the selected memory elements. For example, this method of verification of the program disclosed in the above Korean patent application No. 94 - 18870. However, as the reprogramming operation is performed after the operation verification program with the programming voltage of a constant level, the threshold voltage of the programmed memory elements is still not equal. The variability of environmental conditions, such the second statement of the substance of the invention

Thus, the purpose of this invention is to provide a nonvolatile semiconductor memory device capable of supporting a uniform threshold voltage of programmed memory elements, regardless of the variation of the operating temperature and supply voltage.

Another purpose of this invention is to provide a nonvolatile semiconductor memory device capable of increasing its reliability regardless of the variability of the process.

To achieve the above objectives of this invention improvemerit generator voltage non-volatile semiconductor memory device having multiple memory elements with a floating gate, a programming circuit for programming the selected memory elements and schema verification program to verify that successfully programmed in the selected memory elements or not, comprises a generator of high voltage for generating the programming voltage, the circuit adjustment for detecting the level of the programming voltage so in order to consistently increase the programming voltage within a specified diapa for comparing the detected voltage with a reference voltage and then generating a comparing signal and a control circuit generating a high voltage for activation of the high voltage generator in response to the reference signal.

Brief description of drawings

The invention is illustrated by reference to the accompanying drawings, in which:

Fig. 1 is a diagram illustrating the generator programming voltage according to a preferred variant of the present invention;

Fig. 2 is a diagram illustrating a signal generator adjustment according to a preferred variant of the present invention;

Fig. 3A is a diagram illustrating a binary counter according to a preferred variant of the present invention;

Fig. 3B is a diagram illustrating each stage of the binary counter of Fig. 3A;

Fig. 4 illustrates a clock generator for generating clock to run the binary counter of Fig. 3A;

Fig. 5 is a diagram illustrating a signal generator according to a preferred variant of the present invention;

Fig. 6 is a diagram illustrating the cycle counter according to a preferred variant of the present invention;

Fig. 7 is a time chart showing the operation of each part of the circuits associated with the generator programming voltage, according to a preferred variant of the present invention;

Fig. 8 is a scheme according to the present invention;

Fig. 9 is an equivalent circuit schematic showing a portion of a matrix of memory elements with a standard NAND structured memory elements;

Fig. 10 is a schematic circuit diagram showing the flow generator voltage according to a preferred variant of the present invention;

Fig. 11 is a time chart showing the operation of each part of the circuits associated with the flow generator voltage, according to a preferred variant of the present invention, and

Fig. 12 is a diagram showing the relationship between the cycle of the program and the programming voltage and reduced voltage, according to a preferred variant of the present invention.

A detailed description of the preferred option

The present invention is applied to N - channel transistors with a depletion mode /hereinafter referred to as "transistors D-type"/ having a threshold voltage of - 1.8 V, N-channel MOSFET with an enrichment mode/ hereinafter referred to as "transistors N-type"/ having a threshold voltage of 0.7 V and F - channel MOS transistors (hereinafter called "transistors are P-type"/ having a threshold voltage of 0.9 Century

Fig. 1 shows a generator programming voltage is response to the signal transfer charge fRRand its complementary signal received from the control circuit generating high voltage 20. The high voltage generator 10 is a well-known circuit for generating the programming voltage Vpgmhigher than the power source voltage Vccobtained by use of the method of charge pumping. The high voltage generator 10 includes a transistor 17 and the N-type to obtain an initial voltage Vcc-Vthto the node 1, the transistors are N-type 11-16, have their own channels, connected in series between the common output 1 and the common output 2, and MOS capacitors - 3-8, respectively connected to gates of the transistors are N-type 11-16. The gates of transistors N-type 11-16, respectively, are connected to their drains, and stock-ishikawae total odd nodes of the MOS capacitors 3, 5 and 7, and stock-ishikawae shared nodes even MOS capacitors 4, 6 and 8 connected to the signal transfer charge fRRand its complementary signal, respectively.

The channels of transistors D-type 18 and 19 connected in series between the output node 2 of the high voltage generator 10 and the source voltage Vccand their gates respectively connected with the software signal uproarious programming voltage Vpgmto source voltage Vcc.

Scheme adjustment for 30 consecutive increase the programming voltage Vpgmduring operation of the program connected to the output of the output 2. Between the power ground Vssand the output node 2 is connected scheme tune 30, in which the channel of the N-type transistor 31 and the resistor R1-R10, Rn-Rmconnected in series with one another, and the gate of the N-type transistor 31 is connected with the program control signal through an inverter 32. The connection node between the resistors 37 Rnand R10connected to the output connection 38 between the resistor R1and drain of the N-type transistor 31 through the channel of the N-type transistor 33. Conclusions the connection between the resistors R10-R1respectively connected to the output connection 38 through the channels of the transistors 34 and 35. The gates of transistors 33-35 respectively connected to the signal adjustment TRMp10-TRMp1. Transistors 33-35 are bypass means for bypassing consistently resistors R1-R10.

The comparison circuit 40 compares the reference voltage Vprefvoltage V36the connection node 36 between the resistors Rmand Rn. In the comparison circuit 40 keograms the control signal through an inverter 47. The first branch, in which the channels of the P-type transistor 44 and N-type transistor 42 are connected in series and a second branch, in which the channels of the P-type transistor 45 and the N-type transistor 43 are connected in series, are connected in parallel between the supply voltage Vccand a common node 46. The gates of transistors P-type 44 and 45 are connected together and also connected to the output connection 48 between the P-type transistor 45 and the N-type transistor 43. The reference voltage Vprefi.e. about 1,67, applied to the gate of the N-type transistor 43. The gate of the N-type transistor 42 is connected to a common node 36. The node connection 49 between the P-type transistor 44 and N-type transistor 42 serves as the output pin of the comparison circuit 40. The comparison circuit 40 outputs the logic state "low", if the voltage V36more reference voltage Vprefand outputs the logic state "high", if V36< Vpref.

The control circuit generating high voltage 20 is connected between the comparison circuit 40 and the high voltage generator 10 and controls the programming voltage Vpgmto maintain a given constant voltage level. The control circuit generating high voltage 20 contains logical the om control via the inverter 21. The first inputs of the logic elements AND NOT 24 and 25 receive the output of the logical element AND-NOT 22 through the inverter 23, and the second inputs respectively receive the clock pulses and fpfrom the ring generator (not shown). At this time, the clock pulses and fphave a frequency of about 8 MHz. Logical elements AND NOT 24 and 25 output the pumping charge and fRRthrough the inverters 26 and 27.

If V36> Vprefthe control circuit generating high voltage 20 inactivated, and if V36< Vprefit becomes activated. Thus, if the programming voltage Vpgmincreases, then the voltage V36also increases. Therefore, the control circuit generating high voltage 20 is not activated, and thus, the high voltage generator 10 reduces the programming voltage Vpgm. On the other hand, if the programming voltage Vpgmdecreases, the high voltage generator 10 increases the programming voltage Vpgm. Therefore, the programming voltage Vpgmmaintains a constant voltage level by controlling the control circuit generating high voltage 20.

Off Tr is as follows:

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In the on state of the transistor 35 programming voltage Vpgm1on the output node can be represented as follows:

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In the on state of the transistor 34 programming voltage Vpgm1on the node output 2 can be represented as follows:

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As you can see from the above equations, the sequential switching transistors 35-33 programming voltage at output output 2 sequentially increases. Thus, by successive execution of the programs and operations of the verification program with the increase of the programming voltage sequentially within a predetermined voltage range, i.e. from 15 to 19.5 B, can be provided with memory elements having a constant threshold voltage, regardless of the various changes, such as changing the process and ambient conditions change.

Fig. 2 shows the signal generator adjustment 300 for generating adjustment signals that sequentially increase the programming voltage pgm serial switching transistors 35 and 33 in Fig. 1. The signal generator adjustment 300 has many logical elements OR NOT 51-55 who receive combination vicenta OR NOT 55 is connected to one input of the element OR NOT 56 in the trigger. The output of logic element 56 is applied to the logical elements OR NOT 51-55 through the inverter 58, and also to one input of logic element 57. Another output of the logical element OR NOT 57 in the trigger associated with the software control signal and its input is connected to the signal adjustment IRMp10and with another input of logic element OR NOT 56. During the operation of programming the trigger is composed of logic elements 56 and 57, captures the signal adjustment IRMp10in the logic state "high", if the selected item OR NOT 55, i.e., the element OR NOT issuing the logic state "high". The inverter 58 provides an output element OR NOT 56 as the feedback signal. Thus, the logical elements 56 and 57 and inverter 58 are fixing means for fixing the adjustment signals TRMp1+TRMp10in logic state "low". Therefore, if the selected memory is not successfully programmed even after the tenth operation verification program, operations programming support an increased level of maximum programming voltage Vpgmmax, i.e., 19.5 V, according to a preferred variant of the present invention. Since the maximum programmiruya the HHS gate of the memory element, it should be noted that this invention is not limited by the maximum level of the programming voltage of 19.5 C. in Addition, this invention uses 10 signal adjustment, but it also is not limited to this. However, it is desirable that the programming voltage V, increasing in each operation, programming, was below 1, preferably below 0.5 Century.

Fig. 3A shows a binary counter, and Fig. 3B shows a schematic diagram of a circuit in each stage of the binary counter of Fig. 3A.

As shown in Fig. 3B, the channels of transistors of N-type 65-68 are connected between the output output 0; +1 and its complementary output output +1, the gates of transistors 66 and 67 connected together with a complementary output synchronization input and gates of the transistors 65 and 68 with the output synchronization input 0. The inverter 64 is connected between the output pin 0; +1 and its complementary output output +1, the second input of the logical element AND-NOT 61 is connected to the common output between the transistors 66 and 67 through an inverter 63. Second input of the logical element AND-NOT 62 is connected to the common output between the transistors 67 and 68, and its output to the complementary output output +1. Thus, if the signal is clean logical status is in store output +1 assumes the logic state "high". In addition, each time input output 0 goes from logic state "high" to logic state "low", the output state of the output output 0; +1 is changed.

Binary counter 400 of Fig. 3A is composed of 7 stages, connected in series with each other. Conclusion cleaning R associated with the clean signal and the output synchronization input is 0, and its complementary output synchronization input in the first stage are respectively connected to the clock IC and its complementary clock 7 cascades 71 - 77 generates complementary signals under accounts and 4 cascade 71-74 output count LP1-LP4. Each time the synchronization signal SC goes to logic state "low", the signal count LP1-LP4counted, and complementary signals of the counting LP1-LP7recalculated.

Fig. 4 is a circuit diagram showing the oscillator signals to generate a clock, which must be provided for the binary counter 400 of Fig. 3A. In the figure the signal programming and verification is generated from the timer (not shown) in response to the control signal of the program Generator signals comprises a generator of short pulses 80, consisting of inverters 81-83 and item-And-x pulses 80 generates a short pulse logic state "low", when the signal of the programming and verification passes to the logic state "high".

Fig. 5 is a schematic diagram of an oscillator circuit control signal for generating a signal treatment and signal control Generator control signals Fig. 5 generates the signal filtered through the generator short pulses 91 and inverters 92 and 93 in response to improvemerit flag signal Sapgm is extracted from the instruction register (not shown). Improvemerit flag signal Sapgm is applied to the first input of the logical element OR NOT 95 through an inverter 94, the detection signal PDS program to the second input and the signal counting cycles PCOut to its third input.

Logical-OR-NOT 95 outputs the control signal through an inverter 96. The detection signal PDS program is generated according to the operation verification program. If all the selected memory elements have been successfully programmed, the signal detection program goes to logic state "high". On the contrary, if at least one of the selected memory elements has not been successfully programmed, the signal detection program goes to logic state "low". This technique verification p the couple cycles 500 for generating a signal counting cycles PCout. The calculation cycles 500 is a logic circuit composed of logic elements AND NOT 101-110 and logical element OR NOT 111. Complementary signals of the count supplied from the binary counter 400 to the logical elements 101-107, respectively. Conclusions NO-N6 are connected to the voltage ground Vssor with the power source voltage Vccaccording to the frequency of counting cycles. Since frequency is the number of cycles set at 20 according to a preferred variant of the present invention, the conclusions N 2 and N 5 are connected with the power source voltage Vccand the remaining conclusions N 0, N 1, N 3, N 4 and N 6 are connected with a voltage grounding Vss.

Improvementwas scheme according to a preferred variant will be described with reference to a timing diagram of Fig. 7.

As shown in Fig. 7, the operation of the self-programming begins in response to the transition someprogram.exe flag signal Sapgm from logic state "low" to logic state "high". Since the detection signal PDS program and the number of cycles of signal PCout is in logic state "low" at the start of operation of the self-programming, the generator control signal generates the control signal program logia "low" to logic state "high".

In addition, in response to improvemerit flag signal Sapgm, which goes to logic state "high", the generator short pulses 91 generates a short pulse logic state "low", and thus the binary counter 400 of Fig. 3A is cleared. As shown in Fig. 7, a timer (not shown) generates a signal programming and verification in response to the transition signal control program from the logic state "high" to logic state "low". Signal programming and verification is a sync pulse, which has the logic state "low" 30 μs, and the logic state "high" 10 μs, when the control signal program is in logic state "low". The duration when the signal control program leaves the logic state "low", equal to the time of operation, programming, and duration, when the control signal program leaves the logic state "high" equal to the time of operations verification program.

At time t1Fig. 7 in response to the transition signal control program from the logic state "high" to logic state "low", the generator programming voltage 200 of Fig. 1 involved viruet scheme tune 30. In the beginning of the operation, since Vpref> V36the comparison circuit 40 outputs the logic state "high". Therefore, the inverter 23 outputs a logic state "high", and therefore, the control circuit generating high voltage 20 generates a signal transfer charge fRRand its complementary signal Thus, the high voltage generator 10 generates a gradually increasing high voltage signals fRRand the Programming voltage Vpgmincreases until the voltage V36in connection node 36 reaches the reference voltage Vpref. Therefore, the programming voltage Vpgmsupports initial programming voltage Vpgminshown in the above equation (1). Technology programming of the selected memory elements programming voltage Vpgmdisclosed in Korean patent application N 18870.

At time t2signal programming and verification passes to the logic state "high", and in the period between t1and t2the operation verification program for programmed memory elements. In response to the signal of the programming and verification which enters technologies impulse, and the inverter 86 generates a short pulse signal fsplogic state "low". The synchronization signal SC is generated as a signal similar to the signal of the short pulse fsp. Then the binary counter 400 of Fig. 3A generates a signal counting LP1equal to the logic state "high", as shown in Fig. 7. Thus NOR gate 51 of Fig. 2 generates a signal adjustment TRMp1equal to the logic state "high". Thus, the enabled state of the transistor 35 Fig. 1 resistor R1shunted, and the voltage V36in connection node 36 becomes smaller than the reference voltage Vpref.

This will enable the control circuit generating high voltage 20, and the high voltage generator 10 generates a high programming voltage Vpgm1as shown in the above equation (2).

If the selected memory elements are not successfully programmed during the operation verification program between the moments of time t2and t3, i.e., within 10 μs, then the operation will be performed automatically reprogrammed with a high programming voltage Vpgm1in the time period between t3and t4.

At the moment vremena pulses 80 of Fig. 4 generates a short pulse logic state "low" and the inverter 86 outputs a short pulse of logic state "low", as shown in Fig. 7. The synchronization signal SC becomes short pulse logic state "low", and the counting signals LP1and LP2binary counter 400 becomes a logic state "low" and "high", respectively. Thus, the element OR NOT 52 of Fig. 2 generates a signal adjustment TRMp2which goes to logic state "high". In response to the signal adjustment TRMp2logic state "high", the resistors R1and R2Fig. 1 are bridged, and the voltage V36in connection node 36 becomes smaller than the reference voltage Vpref. Therefore, activates the control circuit generating high voltage 20, and therefore, the high voltage generator 10 generates the programming voltage Vpgm2as shown in the above equation (3).

If the selected memory elements are not programmed successfully despite the reprogramming operation, the program operation is performed again in the time period between t5and t6. Similarly with the consistent growth programme memory elements will not be successfully programmed.

The timing diagram of Fig. 7 shows a case where the selected memory elements successfully programmed in the fifth operation programming. After the fifth operation programming the detection signal PDS program, showing that the selected memory elements successfully programmed, goes to logic state "high" when the operation verification program in the period between the moments of time t10and t11. Thus, the generator control signal of Fig. 5 makes the programming signal is equal to logic state "high", and related program schemes such as a ring counter /not shown/ not involved. After about 2.5 μs after the control signal, the program goes to logic state "high", improvemerit flag signal Sapgm passes to the logic state "low".

You can determine how many programming cycles was within 2.5 µs with a complementary signal of count derived from the binary counter 400.

Fig. 8 is a diagram showing the relationship between the software cycle and the programming voltage according to a preferred variant of the present invention. According Fig. 8, the operation of programming the tion increases from 15 to 19.5 In increments of 0.5 V to the tenth of a program. During 11-20-th programming operations the programming voltage Vpgmsupports a maximum level of constant voltage Vpgmmax 19.5 V by the operation of fixing the trigger, composed of logic elements OR NOT 56 and 57. If the selected memory elements are not successfully programmed after the 20th of a program, the schema counting cycles 500 Fig. 6 generates a signal counting cycles PCout, which goes to logic state "high", and therefore the generator control signals Fig. 5 generates a control signal that goes to the logic state "high", thereby stopping the generation of the programming voltage Vpgm.

As described above, improvemerit generator voltage generates a programming voltage, which sequentially increases within a given range of voltages, depending on the programming cycle according to this invention. The programming voltage is applied to the selected numeric bus. However, it is necessary to prevent the change of the threshold voltage and the effect of memory elements that are not to be programmed among the memory cells connected to the selected h is m is a pass voltage Vpass, i.e., a constant voltage of 10 C. for Example, suppose that the selected numeric tire WL2, then the maximum programming voltage Vpqmmaxincreased according to the programme cycle, i.e., 19.5 V, is applied to the selected numeric bus WL2, the memory element M2 inside a logical element AND-NOT many logical elements NU2 must be programmed as data "0" and the memory element M2 inside the element AND-NOT many logical elements NV1 should be kept as a state of purification, i.e., data "1", the supply voltage Vcc5 attached to the bus of the first selection SLI, constant pass voltage Vpass10 V is applied to unselected numeric tyres WL1and WL3WL8and voltage grounding Vssattached to the bus of the second selection SL2 during the operation of the programming. At the same time, the voltage of the ground Vssapplied to bit bus BL2 connected with the memory element M2, which must be programmed as data "0" inside the logical element AND-NOT many logical elements NV2 and the power source voltage Vcc5 V is applied to bit bus BL1 associated with the memory element M2, which must be maintained as a state of purification, i.e., data "I" GNC the Oia within 120 logical element AND-NOT many logical elements NV2, and thus the memory element M2 inside a logical element AND-NOT many logical elements NV2 is programmed as data "0". However, as the supply voltage Vcc5 V is applied to bit bus BL1 associated with the logical element AND-NOT-block elements NU1 and with the gate of the transistor of the first selection 120 inside AND NOT many logical elements NV1, and a pass voltage Vpass10 attached to the shutter control of the memory element M1 inside AND NOT many logical elements NV1. The source of the first transistor selection 120 is charged through the voltage Vpassand thus the first transistor selection 120 is turned off. Thus, the source and drain of the memory element M2 inside a logical element AND-NOT many logical elements NV1 charged reduced voltage Vpass/=10/, and the increased programming voltage 19.5 V sharply attached to the shutter control of the memory element M2. Therefore, the memory element M2 inside a logical element AND-NOT many logical elements NV1 receives the influence of the voltage 9.5 V, and thus breaks the thin tunnel oxide layer due to changes in the manufacturing process, or an intermediate insulating layer. Meanwhile, the cops NV2. Therefore, the application of a constant flow voltage Vpassto unselected numeric tire deteriorates the reliability of the EEPROM. To solve this problem, a preferred variant of the present invention will be described with reference to Fig. 10-12.

Fig. 10 shows a flow generator voltage to generate a pass voltage that must be applied to unselected numeric tires. According to the figure, the flow generator voltage 600 has the same structure as the generator programming voltage 200 of Fig. 1, except that the values of the resistors R'1-R10, R'4and R'min the generator line voltage 600 differ from the values of the resistors R1-R10, Rnand Rmin the generator, the programming voltage is 200, and that of the output node 2 is shown passing voltage Vpassinstead of the programming voltage Vpgm. To control the flow generator voltage 600, also apply to the generators of the control signals shown in Fig. 2-6. The flow generator voltage 600 generates a pass voltage Vpasswhich sequentially increases from an initial voltage Vpassin8 to maximum bore the ass can be done by using the proper values of resistors R'1-R'10, Rnand Rm. The operation of the flow generator voltage 600 are identical to the operations of the generator programming voltage 200 except for the value of a pass voltage Vpassand they will not be described. The generators of the control signals shown in Fig. 2-6 are flow generator voltage 600 Fig. 10 and will not be described.

Fig. 11 is a time chart for describing operations of the flow generator voltage Fig. 10. Fig. 11 is identical to Fig. 7, except that instead of the programming voltage Vpgmgenerates a pass voltage Vpass.

Fig. 12 is a diagram showing the relationship between the programming voltage Vpgmand reduced voltage Vpassaccording to the programme cycle. As you can see in the figure, the voltage difference between the programming voltage Vpgmand reduced voltage Vpassis set to 5 V to the tenth of a program. This voltage difference can be properly installed according to the structure or properties of the memory elements in order to prevent the gap from"ptx2">

As described above, since improvemerit the generator voltage and the generator line voltage according to this invention generate a programming voltage and a pass voltage, which is sequentially increased in a predetermined voltage range, the device reliability can be improved without breaking the insulating layer or change the threshold voltage of the memory elements that should not be programmed. Moreover, it is possible to achieve a uniform threshold voltage and improve the characteristic of the chip regardless of the variability of process and environmental conditions.

1. Improvemerit generator voltage for the nonvolatile semiconductor memory device with memory elements, comprising a generator of high programming voltage, the circuit adjustment and the comparison circuit, wherein the adjustment scheme is designed to detect the level of the programming voltage and is connected to the generator output high programming voltage, made with the possibility of gradual increase of the programming voltage within a specified voltage range, subject to successful programming vibranium and is connected at its input with the scheme of adjustment, and at its output with a control circuit generating a high voltage, is configured to activate the generator high programming voltage and connected between the comparison circuit and the generator high programming voltage.

2. Generator under item 1, characterized in that the adjustment scheme contains a number of resistors connected in series between the generator output high programming voltage and ground, and many tools bypass connected in parallel to the multiple resistors and designed to bypass and gradual increase of the programming voltage.

3. Generator under item 2, characterized in that the means shunting resistors are transistors.

4. Generator under item 3, characterized in that the circuit adjustment contains a signal generator adjustment connected to the gates of the respective transistors and designed for gradual increase of the programming voltage.

5. The generator according to p. 4, characterized in that the signal generator adjustment includes locking means, performed on the element OR NOT and the inverter and designed to generate signal is causesa fact, he receives a combination of the output signals LP1- LP4and complementary signals LP1- LP7from the binary counter designed for sequential activation of multiple tools to bypass, at the synchronization input and auxiliary input sync binary counter act upon the synchronization signal and a complementary signal.

7. The generator according to p. 6, characterized in that it further comprises a calculation cycles, which is a logical circuit composed of the element and NOT the element OR NOT, and is designed to stop generating the programming voltage in response to the complementary signals LP1- LP7submitted from the binary counter to the elements.

8. Volatile semiconductor storage device that contains many of the NU1- NUmlogic elements AND, moreover, each logical element AND-does NOT contain many memory cells M1 - M8 having channels connected in series with each other, each memory cell is a transistor type with a floating gate and a control shutter, each logical element AND-does NOT contain many numerical tires WL1 - WL8, connected to the control gates is the PR of the first selection with the flow, connected to the corresponding bit line and the second transistor selection source connected to the common bus of the source, drain-ishikawae channels of transistors of memory cells serially connected between a source of the transistor of the first selection and the drain of the transistor of the second selection gates of the transistors of the first and second selection connected with tires of the first and second selection, respectively, and the programming voltage is fed to the selected numeric bus from someprogram.exe generator, which is made with the possibility of gradual increase of the programming voltage for the specified memory cells are not programmed successfully, characterized in that the device comprises a generator of a pass voltage, designed for powering unselected numeric tyres reduced voltage with the possibility to gradually improve and maintain the desired voltage differential between the reduced voltage and gradually increasing the high programming voltage.

 

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EFFECT: higher reliability of operation.

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FIELD: information technology.

SUBSTANCE: flash memory element for electrically programmable read-only memory is meant for data storage when power is off. On a semiconductor base with a source and drain between the latter, there is a tunnelling layer, an auxiliary tunnelling layer, a memory layer, blocking layer and a switch. The auxiliary tunnelling and blocking layers are made from material with high dielectric permeability, from 5 to 2000, exceeding the dielectric permeability of the material of the tunnelling layer made from SiO2.

EFFECT: as a result there is reduction of voltage (4 V) and time (10-7 s) for recording/erasing information and increase in data storage time (up to 12 years).

7 cl, 1 dwg

FIELD: information technology.

SUBSTANCE: memory cell for high-speed controlled gate-region potential EEPROM, the electric circuit of the memory cell having an n(p)-MOS transistor, first and second diodes, a capacitor, a number, an address and a bit line, wherein the cathode (anode) of the first diode is connected to the number line and the source of the n(p)-MOS transistor, its anode is connected to the anode of the second diode, the region under the gate of the n(p)-MOS transistor and the first lead of the capacitor, the second lead of which is connected to the gate of the n(p)-MOS transistor and the address line, and the cathode of the second diode is connected to the drain region of the n(p)-MOS transistor and the bit line, wherein the electric circuit of the memory cell additionally includes a p(n)-field-effect transistor, a common and control line, wherein its source is connected to the region under the gate of a MOS transistor, the gate is connected to the control line and the drain is connected to the common line.

EFFECT: higher reliability of memory cell work.

2 cl, 6 dwg

FIELD: electronics.

SUBSTANCE: invention relates to microelectronics. Restoring memory element has a substrate with a conducting electrode located on its working surface. Said conducting electrode has an active layer of dielectric. Second conducting electrode is located on the active layer. Conducting electrode located on the working surface and/or the second conducting electrode are made from metal. Dielectric layer is metal oxide from which conducting electrode located on the working surface and/or the second conducting electrode is made.

EFFECT: technical result is lower voltage of reprogramming, as well as reduction of consumed power for reprogramming.

14 cl, 1 dwg

FIELD: measurement technology; pulse stream generators.

SUBSTANCE: proposed Poisson pulse stream generator has k + 1 memory devices, comparison unit, k digital-to-analog converters, control circuit, register, counter, selector, k bell-shaped pulse generators, adder, voltage-to-current converter, and clock generator.

EFFECT: enlarged generation range of pulses adequate to ionization chamber signals.

1 cl, 2 dwg

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.

EFFECT: enlarged functional capabilities of device.

1 cl, 1 dwg

Flip-flop device // 2248662

FIELD: pulse engineering, computer engineering, and control systems.

SUBSTANCE: proposed device has RS flip-flop 1, two NAND gates 2, 3, EXCLUSIVE OR gate 4, inverter 5, four resistors 6 through 9, capacitor 10, memory item 11 built around magnetic core with rectangular hysteresis loop that carries write and read coils, two diodes 12, 13, control input 14, and common bus 15.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248663

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Flip-flop device // 2248663

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

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