Multi-tap rake receiver-type system spread spectrum communications

 

(57) Abstract:

Multi-tap RAKE receiver-type communications system spread spectrum contains the unit of Association of characters with adder for adding values of the output signals of the Walsh indexes, which are sequentially generated by the correlator using the algorithm of the fast Walsh transform in accordance with the N code sequences Walsh, with the value generated by the last cascade of N-stage shift register, and N-stage shift register for shifting the accumulated value of the output signal of the RAKE receiver corresponding to each index of the Walsh symbol generated from the above-mentioned adder for each of the sample values of the characters on taps tap receiver, the first logical block of the decision to determine the maximum values by sequentially sorting the output signal of block associations characters and the formation index of the Walsh corresponding to the obtained maximum value as a code word, and the second logical block decision for sorting and subtracting the output signal of the above-mentioned block Association of characters in accordance with the status of each zvejnieki the result is a reduced need for hardware without compromising efficiency. 2 C.p. f-crystals, 3 ill.

THE TECHNICAL FIELD

The present invention relates to a communication method mnogochastichnogo access code division (mdcr) channels in a cellular radiotelephone system, and more particularly to a multi-channel receiver RAKE-type for correlation processing of samples of the received signal with a code sequence that provides compression to determine the sequence of received data.

PRIOR ART

In the system with extended range, if the signal is spread spectrum extends in the channel with multipath propagation and fading, the received signal will have additional components tracts of multipath propagation with different amplitude and phase. In this case - in the sense of efficiency, the power consumption is unacceptable to take only one main signal path having the greatest power, because the power components of the other signals multipath propagation is lost.

In the RAKE receiver uses multiple receivers connected in parallel, as shown in Fig.1, for joint participation in demodulation without loss of these components of the signal power of Enema, it is shown in Fig. 1, described in the book "Synchronons Digital Communication", PP 353-354, Kyohaksa, Jnc., 1995. The time interval between receivers multipath component changes, and component power multipath signal is demodulated with latencyiusing a delay line with taps. The delay timeidynamically adjusted additional control scheme. This design minimizes the signal-to-noise ratio of the output signal of the RAKE receiver.

Although the RAKE receiver is effective from the point of view of using the signal strength, however there is a limit on the number of parallel channels, as required significant additional hardware. RAKE receiver is based on the principle that if the width of the signal spectrum in a frequency selective fading more than an extended delay, we can divide the signal into components with independent fading, the corresponding multiple spectra. If the number of parallel circuits hardware more than the number of valid paths of the signal, the performance R receiver deteriorates. If the power value for valid paths similar or equal to each other, the RAKE receiver will be icnam Association rays" described RAKE receiver, contains multipliers for multiplying output signals of the device of the fast Walsh transform on the weight of the accumulating adders for summing with the accumulation of the output signals of the multipliers and decision-making to determine a received code word on the basis of accumulating output signals of the adders. In the process of descrambler descrambler (or roll) the accepted sample. Single correlator calculates the resulting values corresponding to each index of the Walsh using the fast Walsh transform. The multipliers multiply the resulting values for the complex weights, and accumulate adders summarize the accumulation of the output signals of the multipliers. The accumulated values are fed into the device making the decision. The device of making decisions sequentially sorts the accumulated values and determines the index of the Walsh having the maximum value as the received code word.

However, as in the RAKE receiver described in the aforementioned U.S. patent N 5237586, accumulating adder for each index Walsh, it is necessary to use a large amount of hardware is the second value, the above-mentioned RAKE receiver is not effective enough in the search (i.e., when the definition of some component of the signal, i.e. component psevdochumoy phase, demoduliruem using demodulators in the branches RAKE receiver).

THE INVENTION

The objective of the invention is to create a multi-channel receiver RAKE-type, providing an opportunity to reduce the hardware without sacrificing performance.

Also object of the invention is the creation of a multi-channel receiver RAKE-type, providing an opportunity to reduce the hardware and improve efficiency when searching.

In accordance with the invention, a multichannel receiver RAKE-type for receiving the information signal transmitted by the transmitter of the communications system spread spectrum contains the unit of Association of characters with adder for adding output values of the Walsh indexes, which are sequentially generated by the correlator using the algorithm of the fast Walsh transform in accordance with the N code sequences Walsh, with the value generated by the last cascade of N-stage shift register, and having N - customu the index of the character Walsh, received from the adder each time when each branch is assigned a slice of the first logical block of the decision to determine the maximum values by sequentially sorting the output signal of the combining characters and generate the index of the Walsh corresponding to a certain maximum value, as a code word, and the second logical block decision for sorting and subtracting the output signal of the combining characters in accordance with the state of each bit of the corresponding index and generating probability values of the code word.

BRIEF DESCRIPTION OF DRAWINGS

The above and other objectives, features and advantages of the invention will become clearer from the following detailed description when studying it in conjunction with the attached drawings, which represent the following:

Fig.1 is a generalized diagram of a known multi-channel receiver;

Fig. 2 is a block diagram of a multichannel receiver in accordance with the present invention;

Fig.3A is a table of values corresponding to the 8 indexes Walsh;

Fig. 3B is a variant of the implementation of the logical block making soft decisions the present invention is directed to the improvement of the RAKE receiver and its device combining characters used for handling the signal distortion due to the presence of multiple paths of propagation. RAKE receiver compensates for various delays of arrival of a signal under conditions when the information transmitted by the transmitter system, enters the receiver via different paths. To this end RAKE receiver receives not only the signal having the greatest power, but also the signals of different paths having different time delays, and sums these signals, thereby increasing the reception sensitivity.

In Fig.2 depicts a block diagram of RAKE receiver in accordance with the present invention. In Fig.2 - radio-frequency (RF) receiver 31, the buffer 32A I-sample (in-phase sampling), the buffer 32b Q-sample (quadrature sampling), the multiplexer 33, descrambler 34, single correlator 35, complex multipliers 36-1 to 36-N are of the same design as the corresponding block structure shown in Fig. 11 of the above-mentioned U.S. patent 5237586, and perform similar functions. That is, the composite signal is received from the RF receiver 31 and is sampled in the form of I-and Q-samples. These I - and Q-samples buffered in the buffers 32A and 32b, respectively. When using a conventional RAKE receiver multiplex method RAKE multiplexer 33 selective ranges I - and Q-samples. In both cases, the selected ranges of the samples are independent of each other. Descrambler 34 eliminates the scrambling code from the samples by inverting or reinvestiture each sample, depending on the sign bit scrambling code. Samples are transmitted in parallel in a single correlator 35. Single correlator 35 simultaneously correlated sampling with several well-known code sequences using a fast Walsh transform (MCR). The correlation results are multiplied by a complex weight coefficients in the multipliers 36-1 to 36-n IN the RAKE receiver shown in Fig. 11 of the above-mentioned U.S. patent N 5237586, accumulate the adders are connected to multipliers 36-1 to 36-N, and the device is a decision connected with accumulating the adders.

In a preferred specific embodiment of the present invention, since the correlator 35 algorithm is used MCR for the N code sequences Walsh (Walsh - Hadamard transform=N), N output signals of the correlator 35 correspond to the N indexes Walsh. For example, if the number of the Walsh-Hadamard transform is equal to 8, there are 8 indexes Walsh.

In contrast to the above-mentioned U.S. patent N 5237586, RAKE receiver, with the right and logical block 50 making soft decisions which is connected after multipliers 36-1 to 36 - n Device 40 Association of characters includes the adder 42, the logic block 44 with saturation and shift register 46, which consists of N registers, and combines the received symbols with each other. The adder 42 adds the values of the output signals of the multipliers 36-1 to 36-N with the value generated by the N-th register REG N shift register 46. Logical block 44 with saturation translates into saturation value of the output signal of the adder 42 so that it does not exceed a predetermined maximum value. The output signal of the logical block 44 with saturation is fed to the first register REG 1 shift register 46. Each of the registers REG 1 TO REG N shift register 46 contains the accumulated value of the output signal of the RAKE receiver corresponding to each index of the character Walsh.

Logical block 48 of making tough decisions and logical block 50 making soft decisions connected to the output of the first register REG 1 shift register 46. Logical block 48 making tough decisions determines the maximum value by sequentially sorting the output signal of the first register REG 1 shift register 46 in the device 40 of combining characters and Grechesky block 48 making tough decisions includes the block 60 comparison and memory, the register 62 maximum value and the register 64 of the index.

Logical block 50 making soft decisions sorts, and subtracts the output signal of the first register REG 1 shift register 46 in the device 40 of Association of characters in accordance with the state of each bit of the corresponding index and generates a probability value of a code word. Logical block 50 making soft solutions has m(==log2N) of logical blocks 50-1 to 50-m decision-making, and m is the number of binary bits that make up each index Walsh. Each of the logical blocks 50-1 to 50-m decision includes first and second blocks 100 and 104 comparison and remember, the first and second registers 102 and 106 and the subtraction unit 108. The first block 100 comparison and memory determines the maximum value by sequentially sorting the corresponding value of the output signal corresponding to a binary logic "0" representing binary digits, and remembers a certain maximum value in the first register 102. The second block 104 comparison and memory determines the maximum value by sequentially sorting the corresponding value of the output signal corresponding to binary the Istra 106. If processed symbol Walsh one period, the subtraction unit 108 subtracts the value stored in the second register 106, the value stored in the first register 102, and generates the resultant values R1-Rm. The resulting values Rl-Rm are rules that indicates the probability of the code word is defined in the logical block 48 making tough decisions. Character values Sl-Sm result values Rl-Rm is equal to the code word.

Now will be described the operation of RAKE receiver corresponding to the present invention. For convenience, it is assumed that the number of the Walsh-Hadamard transform is 8. In the conventional system with mdcr the number of Walsh-Hadamard transform is 64.

Fig. 3A and 3B are shown to describe the logic block 50 making soft decisions. In Fig. 3A depicts a table showing the values corresponding to the 8 indexes Walsh. In Fig. 3B depicts a working implementation of a logical block 50 making soft decisions.

The values of the symbols of the Walsh corresponding to the index of the Walsh correlator 35, shown in Fig. 3A. Characters Walsh, corresponding to the Walsh indexes are multiplied by weighting coefficients in the multipliers 36-1 to 36-n multiplication Results consistently of podura REG N shift register 46. Since it is assumed that there are 8 characters Walsh, the shift register 46 has 8 registers. Therefore, two input sources are summed in the adder 42 is the value of the previous symbol of the slice of the relevant index and the value of the symbol of the current slice. The result obtained from the adder 42, served in a logical block 44 with saturation. Because the result of the adder 42 is obtained by re-summing the values of the symbols for the various sections may be formed in an overflow. If the output signal of the adder 42 is greater than the predefined maximum value, the logic block 44 with saturation replaces the value of the output signal of the adder 42 to the maximum value. The output signal of the logical block 44 with saturation is fed to the first register REG 1 shift register 46. Each time the withdrawal is processed some slice on the registers REG 1 TO REG N shift register 46 is supplied enable signal EN. Shift register 46 moves to the right the accumulated value whenever you receive an enable signal EN. As a result, the registers REG 1 TO REG N shift register 46 are accumulated value of the output signal of the RAKE receiver, sootvetstvuyuthie in logical block 50 making soft decisions. Output REG 1 shift register 46 is also fed into the unit 60 comparison and storing a logical block 48 making tough decisions. For example, as shown in Fig. 3, the values 3, 7, 5,..., 1 and 2 corresponding to the index of the Walsh consistently served in the block 60 comparison and memorization. Block 60 comparison and storing a logical block 48 making tough decisions compares the previous value with the current value and stores a larger value in the unit's internal memory. For example, if the value 3 index Walsh 000 compared with the value 7 index Walsh 001, the value 7 is stored in the unit's internal memory. In this case, the index 001 larger value 7 is also stored in the unit's internal memory. If this process is repeated during the same period, the maximum value Vmax and the corresponding index stored in the unit's internal memory. According Fig. 3A, the maximum value Vmax is temporarily stored in the register 62 and maximum values, and corresponding to this value of the index 100 is temporarily stored in the register 64 index. The index, which is temporarily stored in the register 64 index corresponds to the code words of a logical "0", among the values of the output signals of the first register REG 1 shift register 46, consistently served in each first block 100 comparison and logical memory blocks 50-1 to 50-m logical block 50 making soft decisions. For example, the values 3, 5, 20 and 1, corresponding to the index of the Walsh youngest binary bits B0, having a binary logic "0", consistently served in the first block 100 comparison and storing the first logical unit 50-1. The values 3, 7, 20, and 4 corresponding to the index of the Walsh bit B1 having a binary logic "0", consistently served on the first block 100 comparison and storing the second logical block 50-2. The values 3, 7, 5, and 6, corresponding to the index of the Walsh senior binary bits B2, having a logical "1", consistently served in the first block 100 comparison and storing the third logical unit 50-3. Each first block 100 comparison and logical memory blocks 50-1 - 50-3 compares the previous value of the output signal from the current value of the output signal and stores a larger value in the unit's internal memory. The maximum values of 20 (B0), 20 (B1) and 7 (B2) a binary logic "0" is defined for one of the quantities, appropriate indexes Walsh binary bits B0, B1 and B2 having a binary logic "1" among the values of the output signals of the first register REG 1 shift register 46, consistently served on every second block 104 comparison and logical memory blocks 50-1 to 50-3 logical block 50 making soft decisions. The second block 104 comparison and storing the second register 106 logical parts 50-1 - 50-3 similar work first block 100 comparison and storing the first register 102. The maximum values of 7 (B0), 6 (B1) and 20 (B2) a binary logic "1" are defined for a single period, temporarily stored in each second register 106 logical parts 50-1 - 50-3, respectively.

The maximum values are temporarily stored in the first register 102 and the second register 106, the respective binary logic state "0" or "1" binary bits B0, B1 and B2 index Walsh, shown in Fig.3V. Each subtraction unit 108 logical parts 50-1 - 50-3 subtracts the value stored in the second register 106, the value stored in the first register 102, and generates the resulting values R-R3. According Fig. 3B have the following result values: R=+13, R2=+14 and R3=-13. The resulting value is more than the value of the resulting values, the higher the probability is the code word. If the resulting value is a positive number, the value equals "0", and if the resulting value is a negative number, the value equals "1". Therefore, the meanings of the symbols S1-S3 are 0, 0 and 1, which is equal to the code word (B0= 0, B1=0 and B2=1). The values of the output signals R1, S1 R3 S3 logical block 50 making soft decisions facilitate determination subject to demodulation of signal component. That is, the logical block 50 making soft decisions increases the efficiency of the search.

The output signals of the logic block 48 of making tough decisions and logical block 50 making soft decisions are fed to the device serial signal processing, such as channel decoder. Channel decoder determines the component of the signal subject to demodulation, using the output signals of the logic block 48 of making tough decisions and logical block 50 making soft decisions and demodulates this signal component.

From the above it follows that multi-channel RAKE receiver corresponding to the invention allows to reduce the hardware needs without compromising efficiency of the illustrated embodiment of the present invention uses only one accumulating adder and does not decrease the processing speed. Moreover, since the present invention uses the logic of making soft decisions, the search efficiency is improved.

Although the present invention has been specifically illustrated and described with references to preferred implementation, specialists in the art it will be clear that it is possible to make various changes in the form and specific details without changing the scope and essence of the invention defined by the attached claims.

1. Multi-tap receiver for receiving an information signal transmitted by the transmitter of the communications system spread spectrum, characterized in that it contains a device combining characters used to unite the transmitted symbols, and includes an adder for adding the values of the output signals indexes Walsh, sequentially generated by the correlator using the algorithm of the fast Walsh transform in accordance with the N code sequences Walsh, with the value generated by the last cascade of N-stage shift register and the N-stage shift register, where N is the number of code sequences Walsh, for shifting the accumulated znmgo with said adder, for each sample, the values of the characters on taps tap receiver, the first logical block of the decision to determine the maximum values by sequential sorting of the output signal of the first register N-stage shift register mentioned devices combining characters and the formation index of the Walsh corresponding to the obtained maximum value as a code word, and the second logical block decision for sorting and subtracting the output signal of the first register N-stage shift register these devices and Association of characters in accordance with the state of each bit of the corresponding index and formation probabilities mentioned code word.

2. Multi-tap receiver under item 1, characterized in that the device of the Association of symbols further comprises a logical block with saturation, included between the said adder and said N-stage shift register for transfer to the saturation value of the output signal of the adder so that it does not exceed some maximum value.

3. Multi-tap receiver under item 1, characterized in that the second logical block to the first of these logical blocks of decision includes a first device for determining the maximum value, designed to determine the maximum value by sequentially sorting the corresponding value of the output signal in accordance with the first binary logic state of the corresponding bit, the second device, determine the maximum value that is designed to determine the maximum value by sequentially sorting the corresponding value of the output signal in accordance with the second binary logic state of the corresponding bit, and the subtraction unit designed for subtracting the maximum value from the output of the second device to determine the maximum value from the maximum value output from the first device to determine the maximum value.

 

Same patents:

The invention relates to the field of radio engineering, in particular to cellular systems with code division multiplexing using the methods of a relay transmission to ensure continuity of communication of the mobile station with the base station

The invention relates to radio engineering, in particular to a device time synchronization for communication systems, including broadband signals

The invention relates to systems in which separated in time monocalibre are generated from the pulse DC and transmitted to the space in which the total bursts of energy dissipated in the baths frequency where the spectral density merges with the ambient noise, and information relating to these bursts is restored

The invention relates to antenna arrays

The invention relates to telecommunication systems and can be used in the radio links with reuse frequency (PMP)

The invention relates to radio communications and can be used in space and terrestrial radio links

The invention relates to the field of radio engineering, in particular to an adaptive antenna systems (AAS)

The invention relates to communication technology and can be used for the transmission of discrete information channels with frequency-selective fading

Radio system // 2085039
The invention relates to the field of radio communications and can be used in space and terrestrial Radiocommunication systems with reuse frequency

Radio system // 2085038
The invention relates to the field of radio communications and can be used in space and terrestrial radio links with reuse frequency

Radio system // 2085037

FIELD: communications engineering.

SUBSTANCE: proposed system has user terminal, gateway, and plurality of beam sources radiating plurality of beams, communication line between user terminal and gateway being set for one or more beams. Proposed method is based on protocol of message exchange between gateway and user. Depending on messages sent from user to gateway, preferably on pre-chosen periodic basis, gateway determines most suited beam or beams to be transferred to user. Messages sent from user to gateway incorporate values which are, essentially, beam intensities measured at user's. Gateway uses beam intensities measured at user's to choose those of them suited to given user. Beams to be used are those capable of reducing rate of call failure and ensuring desired separation level of beam sources.

EFFECT: reduced rate of call failure in multibeam communication system.

20 cl, 27 dwg

FIELD: automatic adaptive high frequency packet radio communications.

SUBSTANCE: each high frequency ground station contains at least one additional high frequency receiver for "surface to surface" communication and at least one additional "surface to surface" demodulator of one-tone multi-positional phase-manipulated signal, output of which is connected to additional information input of high frequency controller of ground station, and input is connected to output of additional high frequency "surface to surface" receiver, information input of which is connected to common high frequency receiving antenna, while control input is connected to additional control output of high frequency controller of ground station.

EFFECT: prevented disconnection from "air to surface" data exchange system of technically operable high frequency ground stations which became inaccessible for ground communications sub-system for due to various reasons, and also provision of possible connection to high frequency "air to surface" data exchange system of high frequency ground stations, having no access to ground communication network due to absence of ground communication infrastructure at remote locations, where these high frequency ground stations are positioned.

2 cl, 12 dwg, 2 tbl

FIELD: planning data transfer in wireless communication systems.

SUBSTANCE: proposed method used for planning data transfer over incoming communication line for definite terminals of wireless communication system includes formation of definite set of terminals for probable data transfer, each set incorporating unique combination of terminals and complies with estimate-designed hypothesis. Capacity of each hypothesis is evaluated and one of evaluated hypotheses is chosen on capacity basis.

EFFECT: enhanced system capacity.

39 cl, 12 dwg

Up!