The transport interface processor for digital television system

 

(57) Abstract:

The invention relates to the field of digital signal processing. The transmitted signal of the high definition television presents the flow of data in packet form in a sequence of data fields with uneven speed sequence data due to the fact that different types of intervals with supporting information that does not contain useful data, have different duration. Each data field is preceded by an auxiliary segment synchronization field followed by 312 data segments in packet form, each of which contains relevant information direct error correction. In the transmitter, the transport processor generates data packets with appropriate headers and performs continuous processing with a constant uniform velocity-distance data at the same time feeding the flow of data in packet form in a block, which generates a serial data fields by inserting into the data stream, the auxiliary information does not contain data. The advantage is that the transport processor operates with a constant uniform velocity-distance data without converting the original the odd data from the transport processor in the corresponding block of the interface/buffer in response to a character clock signal (ST) 3/8 ARTICLE, and also due to a predetermined fill level of the buffer. The corresponding transport processor/decoder in the receiver works in conjunction with the processor data fields and also carries out continuous processing with a constant uniform data rate. The technical result of the invention is created transport processor in which data is recorded with a uniform speed, as described with uneven speed. 3 C. and 15 C. p. F.-ly, 34 ill.

The invention relates to the field of digital signal processing. In particular, the invention relates to a system designed to facilitate the transport processor when processing stream structured in the form of data fields, suitable for data transmission in the system high definition TV.

Recent developments in the field of video processing has led to the creation of systems for processing and transmitting digital television signals high-resolution (high-definition). One such system is described in U.S. patent N 5168356. In this system, the transport processor is a stream of data, which consists of code words in the standard that is compatible with the known compression standard MPEG. The main function of the transport process. Collectively Packed data words, which is called the data packet or cell data, preceded by a header that contains, among other information, information that identifies the corresponding data words. Thus, at the output of the transport processor generates a packetized stream of data consisting of a sequence of transport packets. The use of the transport packets increases the possibility of re-synchronization and recovery of the signal in the receiver, for example, after a signal failure which may occur due to disturbances in the transmission channel. This is achieved through the header data, with which the receiver when the loss or breach of data transferred can determine the point of re-entry into the data stream.

System terrestrial television broadcasting, high-resolution, recently proposed as television systems high resolution Large Alliance in the United States, uses to transmit packetized data stream with a predetermined structure of the data field format digital transmission with partially suppressed sideband. TV system high-resolution Large Alliance is a proposed standard lane is looking television. System description high definition TV Large Alliance, as it was directed to the Technical subgroup of the Advisory Committee on advanced television on February 22, 1994 (draft document), published in the Proceedings of the National Association of broadcasters 1994, 48th Annual Broadcast Engineering Conference Proceedings, March 20-24, 1994.

In the system of the Great Alliance data is organized into a sequence of data fields. Each structure field includes 313 segments: synchronization segment field (which contains no useful information), followed by 312 data segments. Each data segment includes a data component and a direct component error correction (VEC). Each data segment is preceded by a synchronization component. The transport processor generates packets with a fixed length of 188 bytes to the processor of the transmission, which provides various encoding functions for each package with the formation of the output character segments for their submission to the output transmission channel. Each byte contains a predetermined number of characters, such as 4 characters. The data packets contain data in accordance with a compression standard MPEG-2, developed by the International ORGANIZACIJA data packets to processor transfer, which adds an auxiliary component detection and error correction for forward error correction in each segment and sub segment sync field at the beginning of each data field, i.e., between each group of segments of data fields. To perform these operations in a data-flow rate should be regulated, as will be seen hereinafter, accessories direct error correction and auxiliary segment sync field take place at different times and have different duration.

The packages are separated by intervals that enable the transport processor to insert into the data stream auxiliary data required for each segment (e.g., direct error correction). However, when you want to insert into a stream of data field synchronization segment of greater length, which does not contain useful data, as other packages, the flow of the compressed data must be interrupted and delayed for a time equal to the interval of the segment. The data stream is created taking into account the need to interrupt and insert him in the auxiliary information of different duration (data direct error correction or synchronization field), is illustrated in Fig. 3. This thread and errors as will be discussed in the future.

The authors found that interrupted the flow of data, as described above, not only reduces undesirable speed data, but also leads to the formation between the data packets of unequal intervals. The existence of such unequal intervals between packets complicates the signal processing.

In particular, the authors found that interrupted the flow of data is undesirable increases the requirements for the interface between the transport processor and the processor of the transmission in the transmitter, particularly in relation to data synchronization, as well as between any of the systems for recording packetized data stream. It is highly likely that the data flow of high definition TV will be recorded on Studio equipment or equipment of the consumer. To meet the synchronization requirements of the MPEG standard, any system of records should without distortion to reproduce the synchronization packet, including any uneven gaps between packets, which, if they exist, must be inserted between packets. These requirements significantly increase the complexity of the circuits required as an interface for the recording system. In addition, any takaya.

Preferably the present invention is used in a system designed for processing packetized data stream representing a predetermined sequential patterns data fields. The system according to the invention eliminates the need for alignment of structures of data fields that can be characterized by different velocity-distance data due to differences in type auxiliary (service), i.e. does not contain data, information of different duration, such as what is used in the above-described system of high definition TV Large Alliance.

In the transmitter, the transport processor (for example, to generate data packets with appropriate headers) operates with a constant uniform velocity-distance data without interrupting the system, which inserts the auxiliary information does not contain data of different duration in the data stream with the formation of the predetermined sequential patterns data fields. Preferably, the transport processor runs at such a constant uniform speed data without the need of modifying the predetermined initial structure is named schema interface/buffer in response to the predefined clock signal.

According to the invention, the transmitter in the path of the data flow going at a constant speed output from the transport processor, the device recording/playback.

The corresponding transport processor/decoder in the receiver likewise has a continuous processing with a constant uniform data rate.

In the described embodiment, the transmitter according to the present invention for the supply of data bytes in the buffer circuit interface with uniform speed data transport processor runs at a constant uniform speed data without interrupting, in response to the synchronization signal 3/8 CT, where CT is the system clock signal. In response to the synchronization signal 3/8 ARTICLE, buffer writes data and reads the data with uneven speed with issuing them in the scheme of formation of the field data. The scheme of formation of the field works with uneven speed sequence data and, in response to the data containing the bytes, and the auxiliary information does not contain data, produces a sequence of output structures of the character fields. The scheme of formation of the field data requests data from an uneven speed. The scheme inter is A.

In the described embodiment, the receiver according to the present invention the received stream of symbols is characterized by the sequential structure of the data fields. The processing device data field processes adopted the structure of the field of character data with uneven speed and generates output data coming from the uneven speed. Diagram of front-end buffer responds to the clock signal 3/8 ARTICLE reads and converts these data into the output stream of bytes of data in MPEG format, characterized by a constant uniform velocity-distance data. This data stream is processed by the transport decoder which, in response to the clock signal 3/8 ARTICLE, carries out continuous processing with a constant uniform velocity-distance data.

In the drawings:

in Fig.1 illustrates the sequential structure of the data fields including a segment sync and data,

in Fig. 2 depicts a block diagram illustrating in General terms the device for processing packetized data stream,

in Fig.3 shows the packetized data stream in which the data packets are uneven auxiliary intervals

in Fig. 4 depicts a block diagram of asterisk according to the invention, responsive to the input packetized byte data with the issuance of the transmission channel output symbols

in Fig. 5 illustrates the spectrum of a television signal, which can be used to transfer output data generated by the system shown in Fig. 4; it is shown in comparison with the spectrum of a normal television signal in the NTSC system,

in Fig. 6-16 shows the signals that characterize the system operation of the transmitter shown in Fig.4,

in Fig. 17 depicts a block diagram located in the receiver decoder, which includes a processing device of the data fields in the primary frequency band and the scheme buffer/interface according to the invention, responsive to the input packetized character data with the issuance of the transport processor output byte data

in Fig. 18-27 describes the signals that characterize the system operation of the receiver shown in Fig. 17,

in Fig. 28 and 29 depicts the nodes of the system depicted in Fig. 4 and 17, respectively,

in Fig. 30-32 depict signals, which are useful for understanding the operation of the system, made according to the invention,

in Fig. 33 and 34 are illustrated device, is shown in Fig. 4 and 17, respectively, primenitelnoj high resolution Large Alliance in the United States for use in a system for processing packetized data stream. The output stream of character data representing the structure of data fields, is generated by the processor of the transmission in response to the packet input from the previous transport processor. The processor transfer and transport processor will be described in connection with Fig. 4. Each structure of the data fields includes an auxiliary segment sync field (which does not contain useful data), prior to the group of segments of data fields, each of which has a corresponding component synchronization. Each segment of the data field includes a component package data from 187 bytes, component, synchronization of one byte before each data segment and component direct error correction after the data. Each segment corresponds to the spacing "Y" defines the interval of the ban data between each data packet. The transport processor generates packets input data of 188 bytes plus the segment synchronization processor transfer. The processor transmission adds auxiliary information relating to the coding for forward error correction and synchronization fields, and generates output segments in symbolic form for transmission to the output channel.

Synchronization component corresponding Chasovoy lock loop in the receiver in conditions of excessive noise and interference. A four-character synchronization component is a binary (2-level) in order to improve the reliability of recovery packets and synchronization signals, and represents a signal, which is periodically repeated with a unique frequency, in order to provide reliable detection at the receiver in terms of noise and interference. The synchronization symbols are not encoded according to the method of reed-Solomon or using the lattice code and are not subject to alternation. Synchronization component of the field may contain a pseudo-random sequence and is used for several purposes. It provides a means for determining the beginning of each data field, and can also be used by the adaptive equalizer in the receiver as a reference training sequence to remove intersymbol and other distortions. In addition, it provides a means by which the receiver can determine whether or not to use the noise filter, and can be used for diagnostic purposes, for example for measuring the signal-to-noise and frequency characteristics of the channel. In addition, the synchronization component can be used in schemes for tracking phase in the receiver to determine the parameters in the circuit tou errors or cage code and not punctuated. In this example, the field data does not necessarily correspond to the alternating fields of the image, which constitute the image frame in the television signal in the NTSC standard.

In Fig. 2 illustrates in General terms the processing segment 22 data fields of the same type by units of a processor of the transmission and the output processor shown in Fig. 4. This segment is one of the 312 data segments of a given data field consisting of 832 symbols. The segment illustrated in Fig. 2, contains 187 byte packet transport data in MPEG-2 format, to whom should the synchronization component that contains one byte, and then the corresponding direct component error correction, contains 20 bytes of parity reed-Solomon code. Each transport package for use in the system of high definition TV Large Alliance includes the 4-byte header connection, the first byte is byte synchronization to facilitate synchronization packets. It can be followed by optional header adaptation, and the remaining part of the package comprise the payload of MPEG. Single-byte synchronization component before to be subjected to on-off modulation Ananta encoding direct error correction before how to be an 8-position modulation with partial suppression of the sidebar that are encoded by the trellis code with rate 2/3 code and converted to 828 characters. Ways to implement this 2-position and 8 - position modulation with partial suppression of the sideband is well known. The resulting output segment 24 of the field that is passed to the output channel contains a 4-character component synchronization, followed by 828-character component data field containing data of the MPEG data and direct error correction.

In Fig. 3 shows the flow of data packets in accordance with the structure of the data fields shown in Fig. 1. Each data field has 312 segments, each of which includes synchronization components, data and direct error correction. More specifically, each segment of the data field contains the interval that covers the 188 bytes of data including the synchronization signal ("packet bytes"), and the interval that covers the 20 bytes of code direct error correction. In each segment 188 data bytes correspond 188 intervals (periods) of the clock signal, and every 20 bytes of codes direct error correction correspond to 20 intervals (periods) of the clock signals is flexible should be detained at 228 periods of the clock signal, which corresponds to the interval of the synchronization segment (i.e., 20+188+20 periods of the clock signal). The segment sync field does not contain useful data contained in each segment of the packet data. This gap in the data stream causes undesirable unequal intervals or gaps between packets, as shown in Fig. 3. This interrupted the flow of data and unequal intervals between packages very complicate data management and increase hardware requirements related to the interface between the transport processor and the processor of the transmission as in the receiver and transmitter, as well as reduce the rate of repetition of the data. Moreover, when the playback of recorded materials is difficult to achieve the synchronization patterns of the data fields. Unequal intervals between packages very complicate the task of recording the flow of packet data on the Studio equipment or the equipment of the consumer, since the unequal intervals between packets should be stored where they are, i.e., the recording equipment shall faithfully reproduce the synchronization packet MPEG. In addition, unequal intervals should be preserved in the output signal produced by the demodulator in the receiver.

In the system of the transmitter (Fig. 4) according to the present invention, the transport processor 14 operates with a constant uniform velocity-distance data without interruption and gives the byte data in the MPEG with ravnomernoi speed in block 17 of the formation of the field data and coding. Unit 17 operates at uneven speed of sequence data and in response to the byte data and supporting information that does not contain data (the data synchronization field and direct error correction), produces a sequence of structures of output fields of the characters. Unit 17 requests the data with non-uniform speed by a signal Request Service Data Field. The interface block 16 converts this request into a request signal with uniform velocity-distance data (Request Package For Transportation), served in the transport processor 14.

More specifically, the transport processor 14 applies to the transport system level and unit 17 refers to the system level transmission (which includes also the output processor 18), which is separated from the transport layer interface 16. The data source 12 includes a data compression scheme that is compatible with the MPEG standard, and outputs the byte data in the MPEG-2 transport processor 14. The transport processor 14 packs the bytes of the MPEG format in the data words of a fixed length, which in the end are grouped into data packets of a fixed length (188 bytes). Each packet is preceded by a header containing explanatory information about the source of PR is to them. In addition, at the beginning of each packet transport processor 14 inserts a 1-byte sync signal packet of the MPEG format. The processor 10 performs transmission operations, which include the input buffering, encoding for direct detection/error correction, inserting synchronization signal field, lattice coding for improving the signal-to-noise interleaving to reduce the inuence of errors that occur during transmission of the data packet, and character conversion.

Unit 17 performs the function of forming field data, while the input data packets are formed in the structure of the data fields including data and synchronization components of the field and direct error correction, as described previously. Data packets from the interface block 16 block 17 is followed up with a constant uniform intervals between packets so that the data fields are generated by the block 17 "without joints and without interrupting the data flow. The transmission system of Fig. 4 operates in response to a character clock pulses (ST) and clock pulses derived on their basis, as will be described below. A suitable frequency character of clock pulses equal 10,762237 MHz.

The described system according to the present invention allow the initial structure of the data field, containing, for example, one segment sync field for every 312 data segments, with the formation of a uniform data stream with 313-segment field. Moreover, there is no need to interrupt the flow of data to be inserted between the data fields of the auxiliary synchronization information field.

The system of the transmitter depicted in Fig. 4, uses heartbeats 1/4 CT and 3/8 CT, where CT is a character clock signal of the system. Choice for signal processing clock signal is 1/4 of the ARTICLE, as will be shown below, due to the fact that one byte (8 bits) contains 4 characters, with 2 bits per symbol. The clock signal 3/8 CT is preferred for systems with 8-position modulation with partial suppression of the sidebar, while the clock signal 3/4 ART also are within the scope of the present invention, preferred for faster systems with 16-position modulation with partial suppression of the sidebar. In the system, which will be described below, the block contains 16 between the output of the transport processor 14 and the input unit 17 the formation of the field data buffer 46 FIFO type. Packages byte data is read from the transport processor 14 and stored in the buffer 46 in response to the clock pulses 3/8 ARTICLE and bulsa preferably produced by the digital device, instead of a more expensive scheme phase-locked loop. Heartbeats 3/8 ARTICLE synchronize their work as a transport processor 14, and buffer 46 so that transport data between the processor and the buffer are transmitted synchronously. As will be described below, similar requirements apply to the receiver.

In Fig. 6-9 character heartbeats ARTICLE (Fig. 6) and obtained from them a synchronous clock pulses 1/4 CT (Fig. 7) is generated by circuit 40 synchronization control, such as a microprocessor, in block 17. The circuit 40 also generates a signal to Request Service Data Field (Fig. 10), which is synchronized with a symbol clock pulse ARTICLE, so as to generate a signal to Request Service Data Field used heartbeats 1/4 CT. The generator 42 to the clock signal in block 16 generates clock pulses 3/8 ARTICLE (Fig. 8), which is synchronized with a clock pulse ST and the clock pulses 1/4 CT of circuit 40 synchronization. In Fig. 9 (shown only for reference) shows the pulse length (1 byte associated with the emergence of single-byte synchronizing pulse as the first byte at the beginning of each data packet.

Heartbeats 3/8 ARTICLE are generated by counting clock pulses ARTICLE. Bo possible ratio between clock pulses 1/4 ST and the clock pulses 3/8 ARTICLE. To generate clock pulses 3/8 ARTICLE fits any combination of 3 clock pulses within the time interval of 8 clock pulses, however, between the three pulses and clock pulses 1/4 of the ARTICLE should be fixed phase relationship, and it is the same ratio should be maintained between clock pulses 1/4 ST and the clock pulses 3/8 ARTICLE in the receiver and the transmitter. Illustrated on Fig.8 structure of clock pulses 3/8 ARTICLE is preferable, since this signal is easy to convert and align with byte synchronization (which is easy to detect at the beginning of each package), and can be easily replicated in the receiver. Similar considerations apply to the use of any six of the eight character clock pulses for generating clock pulses 3/4 ARTICLE for a signal with 16-position modulation with partial suppression of the sidebar. Illustrated shows the relationship between clock pulses is carried out in the circuit 40 controls the timing by reset the cutting edge of clock pulses 1/4 of the ARTICLE, resulting from the buffer 46 is given byte synchronization package. The count of characters counted from 0 to 7, where 0 is synchronized with the byte synchronizati pulses ARTICLE, however, in the receiver/decoder should be used the same three count.

Scheme 40 synchronization control provides the ability to generate patterns of the data field containing the 312 data segments and one segment sync field. In response to the clock pulses 1/4 ST signal Request Service Data Field (Fig. 10, 13) of the circuit 40 has a high logic level in a period of 188 bytes and a logic low for a period of 20 bytes. The signal Request Service Data Field of the controller 40 (Fig. 10) has a non-uniform intervals between packets. Shows the portion of the field data, in particular the two last segment 311 and 312 data of one field of the data segment 313 synchronization field before the next data field and the first data segment of the next data field. This signal contains the intervals permissions data, when data is requested (each contains 188 bytes of data synchronized with 188 clock pulses 1/4 ST), intervals deny data (each contains 20 clock pulses 1/4 ST) when the data flow should be added direct error correction, or intervals of length 228 of clock pulses 1/4 ST, between fields when data should be supplemented with information regarding ASS="ptx2">

Scheme 44 management responds to the clock pulses 3/8 ARTICLE and heartbeats 1/4 CT and generates at its output a signal Request Package For Transportation, as shown in Fig. 11. This signal requests a 188-byte data packet from the transport processor 14 whenever 313-th clock pulse 1/4 CT. For the formation of a uniform rate of sequence data and data flow without interrupting the signal Request Packet has a constant uniform intervals between requests package. Constant uniform intervals of length 125 clock pulses 3/8 ARTICLE between requests package facilitate the insertion unit 17 of auxiliary data, such as information about direct error correction and synchronization of the field, between fields of data in the data flow without joints and interrupts to create patterns of data fields, as will be explained subsequently.

This invention relates to a data flow having a field structure with 313 segments on the field, including the field synchronization segment, followed by 312 segments of data fields. In this context, the described system will work with the clock pulses, the repetition frequency which is a multiple of the clock pulses 3/8 ARTICLE, for example with a faster Tachtonim suppression sidebar or 16-position modulation with partial suppression of the sidebar. These options will be better understood from the following discussion of Fig.10, 11-30, 31 and 32. From this discussion it will become clear that the principles of the present invention are applicable to other types of structures of the data fields.

The waveform shown in Fig. 10, is a constant for the described variant with the structure of data fields, including 313 segments. The structure of the signal, shown in Fig. 11, may vary depending on several factors as follows. Fig. 30 corresponds to Fig. 11, which depicts the signal Request Package with uniform velocity-distance data and sent from the circuit 44 in the transport processor 14 in response to the clock pulses 3/8 ARTICLE 8-position modulation with partial suppression of the sidebar. If the 8-position modulation with partial suppression of the sideband used heartbeats 3/4 ARTICLE that goes with twice the frequency, the waveform Request Packet sent to the transport processor 14 will be such as shown in Fig. 31. Since the size of each data packet is fixed and equal to 188 bytes, interval data packet remains unchanged and equal to 188 clock pulses 3/4 CT. However, the intervals of the ban data between packages significantly vozrasta to 626 (twice, than in the previous example) due to increase in two times the frequency of the byte clock pulses 3/4 CT. In other words:

626 clock pulses in segment 188 of clock pulses (fixed value) = 438 clock pulses.

Although the number of bytes in the segment has increased, the structure of the data packet has not changed. The structure of the data fields have not changed, because each data field still contains 312 segments, each of which contains 188-byte data packet, in front of which is a segment synchronization field. Similar comments apply to the synchronization pulses fold greater frequency, for example 3/2 ARTICLE or ARTICLE 3, under which the number of clock pulses in the interval between data packets increases. It was determined that the frequency of clock pulses 3/8 ARTICLE is the minimum frequency for synchronization 313 bytes in the segment in the data field of 313 segments.

In Fig. 32 illustrates the use of clock pulses 3/8 ARTICLE that have a high repetition rate, in a system with 16-position modulation with partial suppression of the sidebar. In the case of a 16-position modulation with partial suppression of the sideband frequency clock pulses UVA strip, per unit time is held twice packages. Interval data length 188 clock pulses and the interval of the ban data between the data length of 125 clock pulses are the same as in the case of an 8-position modulation with partial suppression of the sidebar, because of the connection between the frequency of the clock pulses and the data rate with a corresponding modulation type. Lower frequency clock pulses 3/8 ARTICLE at a lower speed data for 8-position modulation with partial suppression of the sidebar is the same, because of the higher frequency clock pulses 3/4 ST at higher speed data for the 16-position modulation with partial suppression of the sidebar. It can be shown that the desired ratio (e.g., 3/8 ST, 3/4, ARTICLE and so on) clock pulses can be obtained in accordance with the following expression that specifies the number of characters per field:

NX(188 + Y) = S(X + 1),

where X(188 +Y) and S(X+ 1) - number of characters in the field;

188 + Y is the number of symbols in the data segment;

X+1 is the number of segments in the field (e.g., 313);

S is the number of characters per segment (for example, 832);

X is the number of data segments in the field (e.g., 312);

Y - interval data;

N - multiplier, which requires ODA is the group of sidebar, and N is equal to 4/3 in the case of clock pulses 3/4 CT.

When reading the data transport processor synchronized clock pulses 3/8 ARTICLE, and in response to the signal Request Packet from block 44, it is within 188 periods of clock pulses 3/8 ARTICLE gives the data packet length of 188 bytes MPEG, as shown in Fig. 12. In fact, in Fig. 12 shows the signal Data is True, which is issued by the transport processor 14 simultaneously with the issuance of 188-byte packets of data. The Data signal is True waveform Request Package For Transportation (Fig. 11). The signal Request Service Data Field of the circuit 40, the synchronization unit 17 (Fig. 10) is not synchronized with the signal of the Request Package For Transportation from circuit 44 (Fig. 11).

Data packets from the transport processor 14 (Data) are fed into the buffer 46 of the block 16. This buffer is relatively small, it is designed for multiple packages. To enable writing of data packets in the buffer 46 in response to the clock pulses records 3/8 ARTICLE (WCK), the buffer 46 also receives at its input the write-enable (WEN) signal Data is True. In addition, from the transport processor 14 in the buffer 46 is flag the Start of Packet (SOP). This flag is generated at the beginning of each data packet simultaneously with bathroom in unit 17 via the interface block 16 not serviced until until the buffer 46 reaches a predetermined level, for example half of the total. Indication of the fill level of the buffer 46 is carried out using a flag Filling, which is fed to the control input of the controller 44.

188-byte data packet is placed in the buffer 46 every 188/313 periods of clock pulses 3/8 ARTICLE (Fig.11 and 12). For the remaining 125 periods of clock pulses 3/8 ARTICLE in the buffer 46 FIFO type data recording is not performed. The arrival rate of the data input buffer 46 uniform and exactly equal to the speed of data output from the buffer 46. The speed of data output is controlled by the signal Request Packet Frame Data from the circuit 40. The signal Request Packet Frame Data and the signal Request Package For Transportation are not synchronized, but are linked through the relation between clock pulses 3/8 ARTICLE and clock pulses 1/4 CT.

The controller 44 includes logic circuit, responsive to the clock pulses 3/8 ARTICLE, the Request signal of the Packet Data Field, the flag Buffer (Fig. 15) from the buffer 46 and the flag of the Start of Packet (SOP), derived from circuit 45 alignment through the buffer 46. To allow reading of data of the transport packet from the buffer in block 17 in appropriate what happens as is shown in Fig. 13-16. The signal depicted in Fig. 13, similar to the signal shown in Fig. 10 and described above.

The normal enable signal readout (Fig. 14) synchronized with the signal of the Request Data Packet Fields (Fig. 13). Flag the Start of a Batch, which normally appears at the beginning of each data packet, causes the controller 44 to issue a signal to the enable input of the read buffer 46 to prevent buffer read data. Specifically, the controller 44 is programmed so that in response to flag the Beginning of a Packet, it reads from the buffer 46 of 188 bytes, then stops reading in the interval signal direct error correction length of 20 bytes. This allows the circuit 50 direct error correction encoder 17 transfer to calculate information relating to direct error correction, for a package that immediately precedes the current packet stored in the buffer 46. This information related to error correction, is inserted into the data stream during the 20-byte auxiliary interval adjustment error at the end of the preceding package. As the signal Request Service Data Field (Fig. 13), and the enable signal read when he was present (Fig. 14), have a structure characterized by naravna unit 17 and to insert the block 58 of the auxiliary synchronization information field of greater duration. This insert auxiliary information is carried out without interruption of the data stream.

Let us return to the description of Fig. 4. Inserting a field synchronization segment without stopping and interrupting flow is facilitated by synchronizing the read/write buffer 46 in combination with a preset fill level of the buffer. As request packets they are continuously written to the buffer 46 from the transport processor. During one period of the field data the exact number of data bytes required for the formation of the field data will be transferred from the transport processor 14 to the buffer 46. The buffer 46 is relatively small, in this example, it holds only 4 data package. Predefined fill level of the buffer is 2 data packet, but this level may be changed in accordance with the requirements of a particular system. In practice, this level should be determined so that the known data intervals and intervals of the ban data in the system buffer is not overflowed, when reading from it will be stopped for insertion into the data stream, the auxiliary information, and is not empty in the rest of the time. When reading from the buffer temporarily stopped to be inserted into the data stream supporting information (Noah speed (Fig.11). During this time, the buffer 46 is not populated until the end. Constant uniform intervals between the data packets (Fig. 11) provide buffer 46 enough time to re-fill until the read data is temporarily prohibited to insert additional information. After the interval ban reading auxiliary data is inserted, the data is again read from the buffer 46. During this time, the transport processor 14 is continuously sent data packets in the buffer 46, as a result, while the transport processor 14 processes the data without interrupting the flow of data flows without interruption.

When using higher frequency synchronization, for example 3/4 ST, 3/2 ARTICLE, the buffer 46 is not empty, because the intervals between packets in mode 8-position modulation with partial suppression of the sidebar is longer. This gives additional buffer time to repopulate from the transport processor.

If the flag Buffer has a low logic level, indicating that the buffer 46 contains less than a predetermined number of packets, the controller 44 also cancels the permission signal read to the buffer 46. At this time segnalato situation may occur, for example, at system startup or after a system reset, for example at time T1. Usually the structure of the field data is initiated at the beginning of the day of the transfer, and from that moment the transmission of data packets continues without a break to exit the station from work at the end of the day transfer. During this time, in those intervals when reading from the buffer 46 is prohibited, the transport processor in response to the signal Request Package For Transportation from the controller 44 continues to send data packets in the buffer 46. After a predetermined number of packets to be recorded and the condition of the buffer is satisfied, the flag state Population (Fig. 15) changes to a high logic level. In the buffer 46 will again be submitted to the enable signal read, which will allow him issuing data packets. Operation permits the read buffer is triggered by leading edge of the first interval resolution of the data, which appears once, in response to execution conditions fill flag Filling will be set to the high logic level. Therefore, at time T2 the first byte (sync) packet of data is aligned with the beginning of the request packet from the Request signal of the Packet Data Field (Fig. 13) and the start signal is Given which exhibits a Fig. 13 - 16. Circuit 45 shown in Fig. 28 together with the blocks 17, 42, 44 and 46, shown in Fig. 4. Scheme 45 alignment contains enabled cascaded D-triggers (registers) 102 and 104, which are synchronized clock pulses read 1/4 of the ARTICLE from the buffer 46 and which are unlocked by applying to the input buffer 46 enable signal read (REN) from the system controller 44. The data from the buffer 46 via triggers 102 and 104 are served in the encoder 17 transfer. In response to the flag of the Start of Packet (SOP) (detained case a copy of the input signal the Beginning of a Packet) from the output of the trigger 102, the controller 44 generates the enable signal to the read buffer. The Start signal is a delayed copy of signal the Start of a Batch input buffer 46.

Let us return to Fig. 4. From the output of the block 45 byte data in parallel code 8 bits and the Data signal is True (Fig. 16) are fed to corresponding inputs of a block 50 direct error correction encoder 17 transfer. Block 50 direct error correction adds 20 bytes of data direct correction of errors in the data flow within the auxiliary spacing data false intervals between each data packet in accordance with the waveform shown in Fig. 16. The flow of data from block 50 direct corrective is it of 8 parallel bits in a group of four case of double-bit words, which are output sequentially. Using well-known methods, the data from block 52 encode block 54 lattice codes with rate 2/3 code with the formation of the output of three bits (two information bits and one calculated excess bits) for every two input bits to improve the characteristics of the signal to noise ratio. These bits are calculated according to a predetermined algorithm, examples of which are well known to specialists in this field. The encoder 54 operates in conjunction with the block 56 generation of bits that forms the third bit in accordance with a preset algorithm.

The output of the encoder 54 lattice code is formed by a sequence of 3-bit words trellis code, and four 3-bit words are bytes. The Converter 58 converts characters each 3-bit word received at its input from the encoder 54, one output symbol and performs a temporal multiplexing of these output symbols received from the block 60 component of the synchronization field, the value of which is set in advance, with the formation of the output character stream data. According to a conversion function block 58, eight successively increasing binary values received from block 54, >/P>The control signals for the generator 60, the synchronization field and the inverter 58 are formed by circuit 40 synchronization control, for example a microprocessor. Circuit 40 controls the operation of the generator 60 so that the block 60 is permitted to give information in respect of segment sync field during an interval of predetermined duration between adjacent data fields, that is, after each of the 312 data segments, as described above. Each segment sync field multiplexed predictable path in the data flow between groups of data fields without interrupting the data flow, as noted above in the description of the buffer 46. The multiplexer 58 also replaces the component synchronization of MPEG at the beginning of each packet to the synchronization signal segment before the final processing block 18.

an 8-level symbol data signal from the block 58 is supplied to the output processor 18, where it suppressed high-frequency carrier may be added a small pilot signal for a sustainable recovery of the carrier in the receiver in difficult reception conditions. Using known methods of signal processing, the modulator 8-position modulation with partial suppression of the sidebar in the processor 18 receives the composition of arty television channel with a bandwidth of 6 MHz, modulates (converts with increasing frequency) signal data carrying intermediate frequency (if) and transfers the signal to the carrier of the high frequency. In Fig. 5 the upper diagram for this example depicts the spectrum of the modulating signal with a partial suppression of the sidebar in comparison with the spectrum of a signal with a bandwidth of 6 MHz in the NTSC standard, which is shown in the bottom diagram.

In Fig. 17 shows a signal receiver with a partial suppression of the sidebar, made according to the invention. The demodulated stream of character data from the preprocessor 72 has the structure of data fields, which was described above, when the uneven speed of the sequence data. The processor 75 data fields related to the level of the transmission system, processes the structure of data fields, walking with an uneven speed data, and outputs data with nonuniform velocity-distance data. Scheme 84 buffer interface converts the data into a byte stream of data in the MPEG standard, coming with a constant uniform speed. This thread is processed in the transport decoder 86 which operates without interruption with a constant uniform data rate and outputs the decoded byte data to the output processor 88. TTY of the transmission channel, processed RF tuner 70, including schema selection and mixers to convert the signal with decreasing frequency. This signal is fed to the if filtering and synchronous detection on the preprocessor 72 using known methods for forming a signal in the band of the modulating signal. Block 72 also includes an equalizer to compensate for amplitude and phase distortions introduced by the transmission channel. The signal symbol data output unit 72 then decoding trellis code, direct detection/correction of errors and other signal processing that is the reverse of the processing performed in the transmission system shown in Fig. 4.

Heartbeats ARTICLE and derivatives heartbeats 1/4 CT and 3/8 ARTICLE identical to the corresponding clock pulses in the transmitter. Thus, the output data stream (byte data in the MPEG standard), which is served in the transport processor/decoder 86 corresponds to the data stream (byte data in the MPEG standard) issued by the processor 14 in the system of the transmitter depicted in Fig. 4. The input character data is supplied to the block character Converter and demultiplexer 74 correspond whitefish is oneto synchronization field of relatively long duration, which respectively define a neighboring field data (Fig. 1 and 3), between groups of packets with respect to the lower duration. Thus, the input stream of character data in the receiver has a non-uniform velocity-distance data. Before you enroll in a transport processor 86 of the receiver, this input stream of character data with nonuniform velocity-distance data is converted into an output signal of the byte data in the MPEG (scheme 84), which contains the data packets coming from uniform speed, divided evenly between packages. This data flow, the following constant uniform speed, easy handling and demultiplexing data transport decoder 86 which operates without interrupting the data flow.

More specifically, the input stream of character data in the frequency band of the modulating signal with non-uniform velocity-distance data obtained after demodulation and equalization, served in character Converter and demultiplexer 74, which carries out the operations reverse to those performed by the Converter 58, shown in Fig. 4. Unit 74 converts each character in a 3-bit word, which is using the Deco is changing the synchronization signal segment at the beginning of each packet segment on the synchronization signal packet MPEG. The stream of character data processed by the block 74, is controlled by the block 90 to detect the occurrence of control information that is present during the sync interval field, for example the so-called "training sequence" for use during the previous equalizer in block 72, the information about the mode and other information. This information is extracted by the block 90 and is served in the previous schemes in accordance with the requirements of a particular system.

Group 2-bit data words from the output of decoder 76 lattice code Converter 80 serial data in parallel is converted from serial form into 8-bit (one byte) parallel form. Consecutive words from the transducer 80 is served in the block 82 detection and error correction, for example a reed-Solomon decoder. After error correction data from the block 82 is served in the block 84, a buffer/interface receiver together with the Data signal is True, the clock pulses ARTICLE and 1/4 of the ARTICLE, and also signal the Beginning of a Packet from the controller 92. Heartbeats ARTICLE and 1/4 ST synchronized and are produced by the local oscillator in the controller 92. Signal the Beginning of a Packet is generated in response to the appearance at the beginning of each the l Data is True.

Block 84 buffer/interface similar to the block 16 of the transmitter depicted in Fig. 29. Diagram of the interface of Fig. 29 includes a buffer 100 FIFO type, the system controller 120, the generator 122 clock pulses 3/8 ARTICLE and circuit 145 alignment characteristics of each of these devices are similar to the characteristics of such devices in block 16 of the transmitter depicted in Fig. 28. Buffer 100 shown in Fig. 29 is essentially the same as the buffer 46 FIFO type in block 16 of the transmitter buffer in Fig. 4, except that the clock pulses of the read and write are reversed. More specifically, the clock input write buffer 100 filed heartbeats 1/4 of the ARTICLE, and the clock input read buffer 100 filed heartbeats 3/8 ARTICLE. In Fig. 29 signal the Beginning of the Packet in the input register 110 is a buffered version of the signal the Beginning of the Packet, and signal the Start of a Batch input transport processor 86 is a delayed version of the signal the Beginning of the Packet in the input register 110.

Let us return to Fig.17. The byte stream of the data in the frequency band of the modulating signal in the MPEG from the block 84 is processed by the transport processor/decoder 86, which essentially produced rocessor 86 decodes the data by dividing them into component parts. The processor 86 provides various schemes for data processing and demuxing, including analyzers, headers, routers signal in accordance with information contained in the header decompression scheme signal of MPEG and other data processing units of image and sound, which generate signals formatted as needed for audio/video processor 88, shown in Fig. 17. Video and audio data, restored by the transport decoder 86 are processed accordingly video and audio in block 88 with the formation of the image signals and sound, suitable for playback.

The detector 90 in the block 75 provides a signal Marker Field in block 92 management. Signal Marker Field prevents the controller 92 record segment sync field in block 84, a buffer, resulting in the output data stream loses synchronization components of the field. The data is output from the block buffer 84 form a single stream that does not contain the components of the synchronization field, resulting in a stream of byte data in the MPEG from the block 84 is characterized by a constant uniform velocity-distance data and constant uniform intervals between packets. Remove sinkhronizatsii read/write buffer 84 with regard to a predetermined fill level of the buffer. If there are packages they continuously read from the buffer 46 to the transport processor. During one period, the corresponding field data from the buffer 84 to the transport processor 86 will be given the same number of bytes, what is needed to make a data field. The buffer 84 is characterized by the same amount and requirements of its filling that buffer 46 in the transmitter. When the record in the buffer 84 is temporarily forbidden to remove from the data stream supporting information (e.g., signal synchronization field), the data packets continue to read in the transport processor 86 with a constant uniform speed. During this time, the buffer 84 is not emptied completely. A constant uniform gap between data packets provides a buffer 84 a sufficient time to partially emptied during the interval when the record it temporarily forbidden to remove from the data stream supporting information. Once during the interval when the record was banned, auxiliary information is deleted, the data is again written to the buffer 84. During this time, the transport processor 86 continuously received data packets from the buffer 84, resulting in the flow of data is as, is depicted in Fig. 18-27, corresponds to the operation of the receiver. Synchronization in the receiver is achieved through the use of byte synchronization package, which, as explained earlier, is the first byte of each data packet. As in the case of the transmitter, after the start of packet is detected, the byte synchronization (Fig. 21), are generated clock pulses ARTICLE (Fig. 18) and synchronized with them heartbeats 1/4 CT (Fig. 19). Also, as in the transmitter to generate the receiver clock pulses 3/8 ARTICLE (Fig. 20) use the counter

counting clock pulses 1/4 CT. Synchronously with each byte synchronization packet this counter is reset to zero. The observations made above concerning the structure and characteristics of clock pulses 3/8 ARTICLE in the transmitter, also applies clock pulses 3/8 ARTICLE in the receiver. Heartbeats 1/4 CT and heartbeats 3/8 ARTICLE in the receiver and the transmitter must be identical.

In Fig. 22 illustrates the synchronization signal True Data generated by the circuit block 82 75 simultaneously with the data signal from the processor 75. Waveform Data corresponds to the True form of the data signal from the processor 75. The synchronization signal Data is True and the corresponding data direct error correction, inserted in the data signal, and a much wider gap in 228 clock cycles corresponding to the inserted data signal to the synchronization signal field. Data packets in the data signal appear during 188 cycles during which the Data signal is a True positive. Thus, the data signal from the circuit 82 is characterized by an uneven flow data compared to the packet data. Similar shown in Fig. 22 signal Data True in the transmitter shown in Fig.3 and 10.

In contrast, the signal of the True Data supplied from the block 84 of the buffer to the transport processor/decoder 86 (Fig. 23), has a uniform structure with uniform intervals between packets. The form of this signal indicates that the flow of data from the block buffer 84 has a constant uniform packet intervals (intervals deny, data length 125 periods of clock pulses 3/8 ST) between constant uniform data packets (intervals permissions "data" in length 188 periods of clock pulses 3/8 ARTICLE). Thus, for the transport processor 86 without interrupting the flow of the byte data in the MPEG standard is constant in a steady stream of data. In response to the Data signal Istence data packets for processing of a continuous stream of data. For transmitter counterparts signal Data is True, is shown in Fig. 23, shown in Fig. 11 and 12.

Block 84 buffer/interface in the receiver is similar to the same block in the transmitter shown in Fig. 28. As noted above, the appropriate buffers FIFO type differ in the input clock pulse Reading and writing. In addition, while the system controller 44 of the transmitter of Fig. 28 in response to the Request Service Data Field, produces a signal Request Package For Transportation, the corresponding block in the receiver shown in Fig. 29, to indicate the beginning of a new packet is sent to the transport processor 86 flag the Start of a Batch. As in the case of buffer 46 in the transmitter buffer 100 in the receiver of Fig. 29 every time you reboot your system cleaned and loaded to a predetermined level. Before data is allowed to read, the buffer 100 must reach a predetermined level of "completion". This operation is illustrated in Fig. 24-27 and is similar to the corresponding operations in the transmitter described above in connection with Fig. 13-16.

The controller 120 generates Autonomous time intervals, is shown in Fig. 24 a dashed line. This signal has a uniform is preset pulses 3/8 ARTICLE (corresponding to intervals of the prohibition of data between packets) between the permanent uniform intervals of length 188 periods of clock pulses 3/8 ARTICLE (corresponding to intervals of the resolution of the data in the data packet). From this signal, the controller 120 generates the enable signal read from the buffer FIFO type (Fig. 25) for the buffer 100 and the Data signal is True (Fig.27) for the transport processor 86, and both signals have a constant uniform structure. These signals are produced in response to a signal Buffer (Fig. 26) and flag the Start of a Batch, fed to the input register 110. This flag is a buffered and delayed version of signal the Start of a Batch. Signal the Start of a Batch (detainee in register with output register 110 is fed to the control input unit 120 and the transport processor 86. The signal Buffer is generated when the buffer 100 reaches a predetermined fill. Operation permissions read is triggered by leading edge of the first (positive) interval resolution of the data that appears after the signal is Filling, satisfying the conditions of filling of the buffer will be established at a high level. Therefore, at time T2 the first byte (byte synchronization) packet of data is aligned with the beginning of the interval of the truthfulness of the data signal Data True (Fig. 27).

As the trigger and clock input read buffer 84, sinhroniziruete the x pulses 3/8 ARTICLE, as explained above. Heartbeats 3/8 ARTICLE are also in the controller 120. Through triggers 110 and 112 signal byte data in the MPEG standard is fed to the input of the data transport processor 86, when the trigger is unlocked by permission signal read generated by the controller 120. Simultaneously, the controller 120 flag the Start of a Batch together with the signal Data True (Fig. 27) is fed to the transport processor 86. The signal Data is True is served in the transport processor 86 in order to permit him to accept data during those intervals when there are data packets.

The interface between the transport processor and the processor of the transmission containing the block 17, which is important for many applications. For example, in television broadcasting, when transmission is started, it is required that the processor has generated and issued field data without interruption. The operation of television receivers based on a continuous stream of data fields, including the field synchronization segments to ensure synchronization. Any change in the speed of the following data fields or patterns in the broadcasting process will lead to the breakdown of synchronization in the receiver. Usually the broadcasting Studio has several sets videomagician the VCRs issue of transport packets, containing information of a transport stream. Each recorder synchronizes its output signal with a data flow processor of the transmission, which cannot change the speed of the following data fields or structure fields. Uneven gaps in the flow of packets from the transport processor in the processor transfer will lead to the fact that the structure of the field passed to the data interface will distort the data stream that contains both the package and the structure of the data field. Each Studio VCR will require complex interfaces that have been able to synchronize the signals at the output of the tape recorder with the boundaries of a package, and fields. You will need to pass through the interface for additional information about the structure of the field or control data flow in the interface. The interface of the tape must contain a means for detecting the synchronization signal packet, detection fields and memory sufficient to store in the buffer structure of the data field. Additional difficulties arise in the case of pre-recorded sounds and insertion of local programming and advertising. These and other difficulties successfully removed by the system recording/playback using the eradica and receiver, is depicted in Fig. 4 and 17, respectively, with the difference that the system of Fig. 33 and 34 include a video capture device. In Fig. 33 tape device 15 recording/playback receives a stream of data with uniform velocity-distance data from the transport processor 14, and through the buffer/interface 16 outputs with uniform speed playback data in the encoder and the block 17 the formation of the field data. As in the case of the system depicted in Fig. 4, the system of Fig. 33 is characterized by the data flow in the interface between the transport layer and transport layer. In this example, the data source 12 contains a Studio video camera and the MPEG encoder for encoding the output signal of the camera to its packaging transport processor 14.

The device 15 may be a device for byte-by-byte write to the tape, commercially available, for example a VCR type PanasonicTMD3. In the design of some devices for recording can be enabled interface 16. The device 15 can be a one of the sets consisting of several devices for recording and widely used, as is well known in the broadcast studios to facilitate the transfer of Studio materials of various types.

going with uniform speed (with remote auxiliary information) from the interface/buffer 84, and generates playback data with uniform velocity-distance transport processor/decoder 86. The system shown in Fig. 34, also characterized by a uniform velocity of flow in the interface between the transport layer and transport layer. In this system, the device 85 record is a cassette recorder user is capable of recording from a broadcast or reproduce material, for example, pre-recorded using a device with characteristics similar to unit 15 in Fig. 33. Block 85 may be a separate unit in the system, where the elements 72, 75, 84 and 86 are embedded in a television receiver. Alternatively, the elements 72, 75, 84 and 86 may be included in the device 85 entries.

1. The system for processing the digital data stream in batch form, containing video information, receiving the output data stream representing a sequence of data fields, each of which contains 313 segments, including: (a) 312 data segments, each of which includes interval data and the auxiliary interval segment, and (b) auxiliary segment fields with other auxiliary interval preceding the specified data segments, which responds to a clock signal is data of a predetermined length and a block (16) interface for receiving data from the output of the specified transport processor, characterized in that it also contains the block (17) the formation of the field data, working with nonuniform velocity-distance data and respond to data from the specified interface unit for forming the specified output stream of data representing the sequence of data fields and is characterized by intervals of data and auxiliary intervals of different duration, and output processor (18), and the specified transport processor generates output data packets to the specified interface unit with a constant uniform velocity-distance data and the specified interface unit includes a buffer circuit, responsive to the clock signal system for receiving data with uniform speed and to supply data in the specified block the formation of the field data with non-uniform speed so that the output data stream processing unit of the data field is continuous.

2. The system under item 1, characterized in that the interface unit includes a buffer (46) to transfer data from the specified transport processor in the specified block the formation of the field data transport processor (14) transmits the data in the specified buffer with a constant uniform velocity-distance data, the training data.

3. The system under item 1, characterized in that the block (17) the formation of the field data requests data from the interface unit with variable speed (Request Service Data Field), and the interface unit (16) requests the data from the specified transport processor with a constant uniform speed (Request Package For transportation).

4. The system under item 2, characterized in that the block (17) the formation of the field data responds to the specified clock system, the transport processor (14) operates in response to a clock signal that is an integer multiple of the signal 3/8 CT, where CT is the clock signal of the system, and the buffer (46) writes data in response to the specified clock signal, which is an even multiple of the clock signal 3/8 ARTICLE.

5. The system under item 4, characterized in that the size of the specified buffer is much less than the data field, and the specified integer is even.

6. The system under item 1, characterized in that the specified input data are MPEG compliant, specified auxiliary interval segment comprises information to direct the correction of the errors specified auxiliary segment field contains timing information field, and the specified interval data contains 188 bytes Dora are byte data and the specified clock system ARTICLE is a symbolic clock signal.

8. The system under item 1, which further comprises a video recorder/playback, located in the transmission path of the data stream with a constant uniform speed between the transport processor and interface unit.

9. Reception system for processing the modulated digital data stream containing video data representing a sequence of data fields, each of which contains multiple segments of data, including interval data and the auxiliary interval, and an auxiliary segment fields with other auxiliary interval preceding the set of data segments, characterized in that it contains the input processor (72) to form a demodulated data stream that represents the sequence of data fields and characterized by uneven velocity-distance data, the processor (75) data fields to remove the auxiliary information from the specified demodulated data stream with the data stream, characterized specified uneven speed route data block (84) interface for receiving data from gnlu 3/8 ARTICLE, where C is the clock signal of the system, and the transport decoder (86) for decoding data packets from the specified interface unit to generate its output, with the specified transport decoder receives the data packets from the specified interface unit with a constant uniform velocity-distance data in response to a clock signal that is an integer multiple of the signal 3/8 CT, where CT is the clock signal of the system.

10. The receiver system under item 9, characterized in that the data intervals of the segment include each of the D components of data elements, where D is the number of specified input processor includes a modulator for 8-position modulation with partial suppression of the sideband specified transport decoder receives the data packets from the specified interface unit in response to the clock signal 3/8 ARTICLE, and the data intervals and intervals not containing data received by the specified transport decoder from the specified interface unit, correspond to the intervals, respectively, D and E of the clock signal 3/8 ARTICLE, where D and E numbers and D > e.

11. The receiver system according to p. 10, characterized in that D = 188, and E = 125.

12. The receiver system under item 9, characterized in that the specified intervals in the SOR contains a modulator for 8-position modulation with partial suppression of the sidebar, the specified transport decoder receives the data packets from the specified interface unit in response to the clock signal 3/4 of the ARTICLE, and the data intervals and intervals not containing data received by the specified transport decoder from the specified interface unit, correspond to the intervals, respectively, D and E of the clock signal 3/4 CT, where D and E are integers such that D < E.

13. The receiver system according to p. 12, characterized in that D = 188, and E = 438.

14. The receiver system under item 9, characterized in that the data intervals of the segment include each of the D components of data elements, where D is the number of specified input processor includes a modulator for 16-position modulation with partial suppression of the sideband specified transport decoder receives the data packets from the specified interface unit in response to the clock signal 3/4 of the ARTICLE, and the data intervals and intervals not containing data received by the specified transport decoder from the specified interface unit, correspond to the intervals, respectively, D and E of the specified clock signal 3/4 CT, where D and E numbers and D > E.

15. The receiver system according to p. 14, characterized in that D = 188, and E = 125.

16. The receiver system under item 9, which dopolnitelnoi velocity-distance data between the interface unit and the transport decoder.

17. The method of data processing in the receiver of the modulated digital data stream containing video data representing a sequence of data fields, each of which contains a number of data segments, each of which includes interval data and the auxiliary interval, and an auxiliary segment fields with other auxiliary interval preceding the set of data segments, wherein: (a) demodulator (72) the specified data flow by obtaining the demodulated data stream with non-uniform velocity-distance data, (b) delete (75) auxiliary information from the specified demodulated data stream without interrupting the specified stream with the data stream with non-uniform velocity-distance data, (C) decode (86) data from the specified data stream generated by the operation (b), and (d) convert the velocity-distance data generated by the operation (b), to perform the operation (C) in a constant uniform speed in response to a clock signal that is an integer multiple of the clock signal 3/8 CT, where CT is the clock signal of the system.

18. The method according to p. 17, wherein each data field contains 313 segments, vkljuchajuwih the

 

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The invention relates to the formation, transmission and processing of the television program guide for broadcast television service

The invention relates to the field of digital signal processing
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FIELD: video decoders; measurement engineering; TV communication.

SUBSTANCE: values of motion vectors of blocks are determined which blocks are adjacent with block where the motion vector should be determined. On the base of determined values of motion vectors of adjacent blocks, the range of search of motion vector for specified block is determined. Complexity of evaluation can be reduced significantly without making efficiency of compression lower.

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7 cl, 2 dwg

FIELD: compensation of movement in video encoding, namely, method for encoding coefficients of interpolation filters used for restoring pixel values of image in video encoders and video decoders with compensated movement.

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5 cl, 17 dwg

FIELD: video encoding, in particular, methods and devices for ensuring improved encoding and/or prediction methods related to various types of video data.

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FIELD: movement estimation, in particular, estimation of movement on block basis in video image compression application.

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FIELD: physics.

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20 cl, 7 dwg

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8 cl, 68 dwg

FIELD: information technology.

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25 cl, 6 dwg

FIELD: radio communications.

SUBSTANCE: receiver of compressed audio and image signal has circuits for measurement of relative mistiming of decompressed signals of audio and image data. If mistiming of audio and image signals is within limits of first range of values, synchronization circuits will try to synchronize signals in time appropriately. If actual mistiming exceeds limits of first range, attempts to synchronize signals are halted and non-synchronized signals of audio and image are sent to output.

EFFECT: higher precision.

2 cl, 5 dwg

FIELD: information technologies.

SUBSTANCE: method is proposed for generation of digital broadcasting transport flow pack, including formation of transport flow pack comprising filling area for insertion of available data of subsidiary reference sequence (SRS), randomisation of pack, which includes filling area, and SRS-data is inserted into filling area of randomised packet, addition of parity for correction of errors in pack, where SRS-data is inserted, pack, in which parity has been added, is alternating, and its trellis coding is carried out. Signal of segment synchronisation and signal of field synchronisation are inserted into pack produced by trellis coding, and modulation is carried out with vestigial sideband (VSB) and RF-transformation of pack for transfer of VSB-modulated and RF-transformed pack.

EFFECT: improved efficiency of reception in receiving system and support of compatibility with existing digital broadcasting transmitting receiving system.

23 cl, 14 dwg

FIELD: information technologies.

SUBSTANCE: in process of generation of system heading included into composition of program stream according to expanded system part MPEG-2, if basic identifier of stream is an expanded identifier, and information on size of basic bugger makes 0 bytes, information on size of expanded buffer is generated and recorded as represented by a combination from 24 bits in composition of expanded identifier, marker bit and expanded stream identifier, and by combination of 24 bits, including expanded stream identifier, marker bit and information of expanded buffer limitation scaling, and required for reproduction of elementary flow, which will be compacted using pair of expanded identifier and expanded identifier of stream.

EFFECT: prevention of errors in data reproduction.

4 cl, 19 dwg

FIELD: information technology.

SUBSTANCE: synchronisation instruction is given for packet switched network protocols. The synchronisation instruction may deactivate audio-video synchronisation in the direction of transmission, in the direction of reception, or in both the transmission and reception directions.

EFFECT: enabling devices to control audio-video synchronisation, and deactivate such synchronisation using a unidirectional technique while maintaining synchronisation in the opposite direction.

29 cl, 4 dwg

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