The wireless link with the amplitude-photomanipulating noise-like signals

 

(57) Abstract:

The invention relates to electrical engineering and can be used in communication systems operating in an uncertain noise. The technical result is to develop a radio that can improve the reception quality in the transmission of heterogeneous information in terms of the impact of an uncertain interference with reduced average power. To do this, the wireless link with AFM PSS inputs of the second decoder, control unit, block alternation, the second digital to analog Converter, the second amplifier. The implementation of added elements allows for the use of the uneven distribution of signals in line with AFM PSS to obtain the energy gain in the region of small noise about 13 dB compared to the case with uniform distribution without alternation and 5.5 dB compared to the case with uniform distribution with alternation. 6 Il.

The invention relates to the field of radio and can be used in communication systems operating in an uncertain noise.

Known radio using to improve noise immunity dip photomanipulation sump the t 1973; AC USSR N 509194, CL H 04 B 9/00 from 1974; AC USSR N 563730, CL H 04 B 7/00 from 1976; U.S. patent N 3665472, CL H 04 B 1/38 from 1972). However, due to the impact of the worst interference of unknown structure and limited average power (for example, when the ripple level of interference power), the immunity of links with FM PSS significantly reduced.

Also known radio link using amplitude-photomanipulation signals (afss) with varying amplitude and phase (see application UK N 1356179, CL H 04 27/00 from 1974.; the application of Germany N 2153376, CL H 04 27/18 from 1976 ; the application of Japan N 55-24826, CL H 04 27/00 from 1976; the application of Germany N 3322954, CL H 04 27/00 from 1985; the application of Germany N 3243373, CL H 04 27/00 from 1985). However, used in these links, the rules of the switching phases and amplitudes are not designed to provide noise immunity due to the impact of the worst interference of unknown structure and limited average power.

Most similar in its essence to the proposed device is known radio line with amplitude-photomanipulating noise-like signals (AFM PSS), described in the as of the USSR N 1635275 A1, class H 04 L 27/18 from 1991 /1/.

The closest analogue (prototype) contains on the transmission side information source, phase modulesto, the pseudo-random sequence generator, a shift register, a storage register, a decoder and digital-to-analogue Converter. The output of the information source connected to the first input of the phase modulator. The output of the phase modulator connected to the first input of the modulator, and the output of the generator carrier frequency is connected to the second input of the modulator. The first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register, and its second output to the clock input of the storage register, the output of a pseudorandom sequence generator connected to the input of the shift register. (N+1) informational outputs of the shift register, where N is 2, is connected to the corresponding (N+1) information input storage register, a N informational outputs of the storage register connected to the corresponding N to the information inputs of the decoder. Additional (N+1)-th output of the storage register connected to the second input of the phase modulator. Information outputs of the decoder are connected to the respective N inputs digital to analogue Converter. The output of the digital to analogue Converter connected to the control input of the amplifier. The input of the amplifier connected to the modulator output, and o the side of the radio line - the prototype contains a receiving antenna, a mixer, an intermediate frequency amplifier, a multiplier, amplifier, integrator, the deciding unit, synchronization unit, a local oscillator, a pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter and the receiver of information. The output of an antenna device connected to the first input of the mixer, and the mixer output is connected to the input of the amplifier intermediate frequency. The output of intermediate frequency amplifier connected to the information input of the multiplier, the output of which is connected to the information input of the amplifier. The output of intermediate frequency amplifier connected to the input of the integrator. The output of the integrator is connected to the input of a casting device and to the input of the synchronization unit. The output of the integrator is connected to the input of the receiver information. The first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and the clock input of the shift register. The second output of the synchronization unit is connected to the clock input of the storage register. The third output of the synchronization unit is connected to the input of the local oscillator. The output of the local oscillator connected to the second input of the mixer. The fourth output of the synchronization unit of podklyucheniya shift. (N+1) informational outputs of which are connected to the corresponding (N+1) to the information inputs of register storage. N informational outputs of the storage register connected to the corresponding N to the information inputs of the decoder. Additional (N+1)-th output of the storage register connected to the control input of the multiplier. The outputs of the decoder are connected to the respective N inputs digital to analogue Converter. The output of the digital to analogue Converter connected to the control input of the decision making unit.

Due to the additional pseudo-random variation of the amplitude of the sub signal, manipulated by the phase of the pseudorandom signal extend range, the wireless link is the prototype compared to the radio - analogs using FM PSS with a fixed amplitude of subcells, provides increased resistance to intermittent interference limited average power of affecting the individual subcells PSS. Theoretically, the energy gain in this radio link with the specified quality requirements can achieve more than 3 dB /2/.

The specified prize is provided under the condition of homogeneous transmission of information, the reception quality of which may be the PI has several disadvantages. First, the device is a prototype does not provide high quality reception when transferring heterogeneous information in an uncertain interference with reduced average power. It is possible that concentration of energy interference on individual bits of the information signal, which more strongly than other places, affect the final quality of communication, as measured by the accuracy of reconstruction of blocks of information, including many places. As such blocks of information bits can be data packets with separately encoded headers cycles group of signals with a temporary seal operational and service channels, digitized samples of analog data, etc. secondly, implemented in the device algorithm uniform distribution of the energy resource is irrational in terms of homogeneous noise with the same noise immunity of the individual digits and the heterogeneity of the structure of the information blocks.

The aim of the invention is to develop a radio link with AFM PSS that can improve the reception quality in the transmission of heterogeneous information and the efficiency of energy resource under the influence of uncertain interference with PSS in the famous radio link, containing on the transmission side information source, a phase modulator, modulator, oscillator carrier frequency, amplifier, power amplifier synchronization unit, the antenna device, the pseudo-random sequence generator, a shift register, a storage register, a decoder and digital-to-analogue Converter. Moreover, the output of the information source connected to the first input of the phase modulator. The output of the phase modulator connected to the first input of the modulator, and the output of the generator carrier frequency is connected to the second input of the modulator. The first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and to the clock input of the shift register, and its second output to the clock input of the storage register, the output of a pseudorandom sequence generator connected to the input of the shift register. (N+1) informational outputs of the shift register, where N is 2, is connected to the corresponding (N+1) information input storage register, a N informational outputs of the storage register connected to the corresponding N to the information inputs of the decoder. Additional (N+1)-th output of the storage register connected to the second input of the phase modulator. Information outputs of the decoder are connected to autopaslaugu the input of the amplifier. The amplifier input is connected to the output of the modulator, and the output to the input of the power amplifier. The output of the amplifier connected to the input of the antenna device. At the receiving side radio line-prototype contains a receiving antenna, a mixer, an intermediate frequency amplifier, a multiplier, amplifier, integrator, the deciding unit, synchronization unit, a local oscillator, a pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter and the receiver of information. The output of an antenna device connected to the first input of the mixer, and the mixer output is connected to the input of the amplifier intermediate frequency. The output of intermediate frequency amplifier connected to the information input of the multiplier, the output of which is connected to the information input of the amplifier. The output of intermediate frequency amplifier connected to the input of the integrator. The output of the integrator is connected to the input of a casting device and to the input of the synchronization unit. The output of the integrator is connected to the input of the receiver information. The first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and the clock input of the shift register. The second output of the synchronization unit is connected to the clock input re the second input of the mixer. The fourth output of the synchronization unit is connected to the clock input of the decision making unit. The output of a pseudorandom sequence generator connected to the input of the shift register. (N+1) informational outputs of which are connected to the corresponding (N+1) to the information inputs of register storage. N informational outputs of the storage register connected to the corresponding N to the information inputs of the decoder. Additional (N+1)-th output of the storage register connected to the control input of the multiplier. The outputs of the decoder are connected to the respective N inputs digital to analogue Converter. The output of the digital to analogue Converter connected to the control input of the decision making unit.

Added on the transmission side block interleave control unit, the second decoder, the second d / a Converter and the second amplifier, and at the receiving side have been added to the block interleave and the control unit. On the transmitting side output of the information source connected to the information input unit of alternations. The information output unit alternation connected to the first input of the phase modulator. Additional (N+1)-th output of the storage register connected to the control input of the second clock output control unit connected to the respective clock inputs of the data source and block interleave. K control output control unit connected to the corresponding K control inputs of the block interleave and K inputs of the second decoder, where K 2. The M outputs of the second decoder, where M 2, each connected to the M inputs of the second digital to analogue Converter. The output of the second digital to analog Converter connected to the control input of the second amplifier. The information input of the second amplifier connected to the modulator output and the output to the information input of the first amplifier. At the receiving side to the second output of the synchronization unit is connected to the clock input of the control unit, and the additional (N+1)-th output of the storage register connected to the control input of the control unit. The first and second clock outputs a control unit connected to the respective clock inputs of the block interleave. Control outputs K control unit connected to the corresponding K control inputs of the block interleave. The output of the decision making unit connected to the information input unit of alternation, and the output of block alternation connected to the input of the receiver of the information.

Thanks to a new set of features will increase the quality of reception of the transmitted information by equalizing the power of the om the transmission of individual bits i = 1,...,k with different power Pc1, . ..,Pck. When this limit, the total energy of the radio resource is expressed in the constant total energy of the emitted signals of duration T transmit k-bit information block.

For a given duration T of the transmission of an information block of k binary digits uneven distribution of energy resource ec= xEcwhere x = { xi} kxi0, i = 1,...,k, xi+...+xk= 1, between the individual bits can be implemented in the General case, different combinations of values of the power Pciand duration of Tisatisfying the condition PciTi= xiEc. In the inventive device is proposed to realize the uneven distribution of power Pci= xiPck at a fixed time Ti= T/k, (see Fig. 2). The advantage of this implementation is that this maintains a uniform temporal structure of the signal and you can use tracts power control similar to the paths that already exist in the radio link with AFM PSS. In Fig. 2 shows an example of the uneven energy distribution of the signals Ec= PcT between k = 4 information bits.

The inventive device is illustrated by drawings, showing:

Fig. 1 - structural diagram of the radio link with the amplitude-photomanipulating pseudonoise signals;

Fig. 2 is an example of the uneven energy distribution of the signals Ec= PcT between k = 4 information bits;

Fig. 3 is an example implementation of an information source;

Fig. 4 is an example implementation of a control unit;

Fig. 5 is an example implementation of block interleave;

Fig. 6 - graphs hung the x between the bits of the digitized analog samples.

Declare the wireless link with the amplitude-photomanipulating noise-like signals, shown in Fig. 1, contains a transmitting-side information source 1, the second decoder 2, the control unit 3, block interleave 4, the second d / a Converter 5, the phase modulator 6, the modulator 7, the second amplifier 8, the first amplifier 9, an amplifier 10, the antenna device 11, the synchronization unit 12, the generator carrier frequency 13, the pseudo-random sequence generator 14, the shift register 15, a storage register 16, the first decoder 17, the first d / a Converter 18. The output of the information source 1 is connected to the information input unit interleave 4. The output of block interleave 4 connected to the first input of the phase modulator 6. The output of the phase modulator 6 is connected to the first input of the modulator 7, and the output of the generator carrier frequency 13 is connected to the second input of the modulator 7. The first output of the synchronization unit 12 is connected to the input of the pseudorandom sequence generator 14 and to the clock input of shift register 15, and its second output to the clock input of storage register 16 and to the clock input of the control unit 3, the output of a pseudorandom sequence generator 14 is connected to the input regitration outputs of the storage register 16 is connected to the respective N inputs of the first decoder 17. Additional (N+1)-th output of storage register 16 is connected to the second input of the phase modulator 6 and to the control input of the control unit 3, and the N outputs of the first decoder 17 is connected to the respective N inputs of the first digital to analog Converter 18. The output of the first d / a Converter 18 is connected to the control input of the first amplifier 9, the output of which is connected to the input of the power amplifier 10. The output of amplifier 10 is connected to the input of the antenna device 11. The first and second clock outputs of the control unit 3 is connected to the respective clock inputs of the information source 1 and block interleave 4, K control output control unit 3 is connected to the corresponding K control inputs of the block interleave 4 and K inputs of the additional decoder 2. The M outputs of the second decoder 2 is connected to the corresponding M inputs of the second digital-analog Converter 5. The output of the second d / a Converter 5 is connected to the control input of the second amplifier 8. The information input of the second amplifier 8 is connected to the output of the modulator 7, and the return to the information input of the first amplifier 9.

At the receiving side of the wireless link includes receiving an ante is to 25, block interleave 26, the control unit 27, an information receiver 28, the local oscillator 29, the synchronization unit 30, a pseudo-random sequence generator 31, the shift register 32, a storage register 33, a decoder 34, a d / a Converter 35. The output of an antenna device 19 connected to the first input of the mixer 20, and the output of mixer 20 is connected to the input of the intermediate frequency amplifier 21. The output of intermediate frequency amplifier 21 is connected to the information input of the multiplier 22, the output of which is connected to the information input of the amplifier 23. The output of amplifier 23 is connected to the input of the integrator 24. The output of integrator 24 is connected to the input of a casting device 25 and to the input of the synchronization unit 30. The first output of the synchronization unit 30 is connected to the input of the pseudorandom sequence generator 31 and the clock input of the shift register 32. The second output of the synchronization unit 30 is connected to the clock input of storage register 33 and to the clock input of the control unit 27. The third output of the synchronization unit 30 is connected to the input of the local oscillator 29. The fourth output of the synchronization unit 30 is connected to the clock input of the decision making unit 25. The output of the oscillator 29 is connected to the second input of the mixer 20. The output of the generator is a pseudorandom sequence to the input of storage register 33. N outputs of the storage register 33 is connected to the respective N inputs of the decoder 34. Additional (N+1)-th output of the storage register 33 is connected to the control input of the multiplier 22 and to the control input of the control unit 27, and the N outputs of the decoder 34 is connected to the respective N inputs to analog Converter 35. The output of the digital to analogue Converter 35 is connected to the control input of the amplifier 23. The first and second clock outputs of the control unit 27 is connected to the respective clock inputs of the block interleave 26. K control output control unit 27 is connected to the corresponding K control inputs of the block interleave 26. The output of the decision making unit 25 is connected to the information input unit interleave 26, and the output of the block interleave 26 is connected to the receiver input information 28.

Separate blocks of the inventive device has the following functions.

Information source 1 itself generates or accepts external source information and converts it into a sequence of binary pulses are grouped into code blocks corresponding to distinct parts of the transmitted information. In particular, when transmitting the digitized analog information kPa 2klevels.

An information receiver 28 converts the input sequence of binary pulses to perceived (or for subsequent transmission to an external device) type of information. In particular, when receiving a digitized analog information code blocks can be transformed into a sequence of voltage levels, optionally by filtering is formed of a continuous analog signal.

As a source of information 1 and the information receiver 28 may be any terminal or intermediate (encoder, channel-forming, switching, etc.) digital device that allows you to generate and process a sequence of information blocks received, for example, via the digital interface S1-FL-BI (GOST 24174-80, GOST 26532-85) /14, 15/. As an example in Fig. 3 shows an embodiment of the source of the digitized analog information.

Source of information consists of a source of an analog signal 1.1, analog-to-digital Converter 1.2 and Converter parallel to serial 1.3. Moreover, the source output analog signal 1.1 connected to the input of analog-to-digital Converter 1.2, a k in the sequential 1.3. The inverter output of the parallel code in a sequential 1.3 is the output of the source of information 1.

Inputs kT0and T0information source 1 are used to synchronize the reading of the charges on the output device.

As the source of the analog signal can be used a microphone or pickup /18/ / 671-687.

An embodiment of the analog-to-digital Converter described /5/ page 215, Fig. 2.22.

An embodiment of the Converter of the parallel code in a sequential described in /3/ / 208, Fig. 5.4 (d).

In the role of receiver of information can be the device of cascaded blocks conversion of serial code in parallel (see /3/ page 208 of Fig. 5.4 (b)) and digital to analog conversions, similar to the above described blocks 15(32) and 5(18,35).

The control units 3, 27 are used for process control unit reading and alternation of binary pulse trains in blocks interleave 4, 26 in accordance with the sequence of pulses generated in synchronization blocks 12, 30, and pseudo-random sequences generated by a pseudorandom generators posledovatelnostei counters 3.1 and 3.2, decoder S cycles 1.3, RS-flip-flop 3.4, item And 3.5 S-bit shift register 3.6. and decoder 3.7. Moreover, the clock output of the counter 3.1 is the entrance counter 3.2 and at the same time is the first synchronizing output device 3. The word clock output of the counter 3.2 is the second synchronizing output device 3 and an R-input trigger 3.4. The Q outputs of the counter 3.1 is connected to the Q inputs of the decoder 3.3 S clock cycles, where the Output of the decoder is connected to the S input of the trigger 3.4. The trigger output 3.4 connected to the first input element And 3.5. The second input element And 3.5 and the meter inlet 3.1 are informational inputs of the control unit 3(27). The output element And 3.5 connected to the first input of the S bit of the shift register 3.6. Second input of the S bit of the shift register 3.6 is the clock input of the control unit 3(27). S outputs of the shift register 3.6 is connected to the S inputs of the decoder, 3.7, and K outputs of the counter 3.2 is connected to the K inputs of the decoder. K outputs of the decoder 3.7 are the outputs of the control unit.

An embodiment of the counters 3.1 and 3.2 are described in /3, page 216, Fig. 5.10/.

An embodiment of the decoder described /5, page 131, Fig. 1.95/.

An embodiment of the S-bit RS trigger in /3, p. 174, Fig. 4.12/.

In shown in Fig. 4 diagram of the control unit 3(27) to form various permutations of k bits is used by the decoder, such decoders 2, 17 and 34, but with a different rule to convert binary codes. Part of the bits of the input code from S << B symbols, where B is the base PSS, is formed from the initial pseudo-random binary characters SRP received at a control input of the control unit in the interval between the formation of the last digit of the previous information block and the first digit of the next. These bits define a variant of the pseudo-random sequence of numbers read bits from the outputs of the control unit depending on the quantum numbers coming from counter data cycles on the rest of the K inputs of the decoder (in addition to the above S inputs) in the control unit. Describes the functions of the decoder with high values of S and K more efficiently can be accomplished by using programmable or random-access memory (ROM) according to the principle described in /16/ on page 328.

Blocks interleave 4, 26 are designed for periodic change of the position of the individual bits in the transmitted code b is eremite 4, 26 together with the control units 3, 27 can be a device listed in /16/ pages 327-330 Fig. 8.11 in /17/ pages 83-85 Fig. 2.10. In addition, an embodiment of the data blocks of the standard logic elements /3, 4, 5/ shown in Fig. 4 and Fig. 5. In shown in Fig. 5 is a schematic block interleave 4(26) for combining procedures read bits from the source information in the order of their receipt of information input and extradition procedures on the output data bits in the order specified in the sequence of codes on K control inputs, uses two registers, performing alternately (with period kT0) function input shift register and the output register storage.

The control unit 4 is composed of D-flip-flop 4.1, items, AND 4.2, 4.3, 4.61-4.6k, 4.8, 4.9, 4.111-4.11k, 4.12, 4.13, k - bit shift registers 4.4 and 4.10, decoder 4.5, elements OR 4.7, 4.14, 4.15. The outputs of the decoder 4.5 are the second inputs of elements AND 4.61-4.6kand 4.111-4.11k. The inputs of the decoder 4.5 are the control inputs of the device interleave 4.

Direct output of D-flip-flop 4.1 connected to the second inputs of elements And 4.8 and 4.9 and to the second input element And 4.13. Inverted output of D-flip-flop 4.1 connected to informatsiuyi entrance D-flip-flop 4.1 is the first clock input unit interleave 4.

The first inputs of elements And 4.3 and 4.9 are information input unit interleave 4, and the first inputs of elements And 4.2 and 4.8 are the second clock inputs of the block interleave 4.

The output element And 4.2 is connected to the clock input k-bit shift register 4.4, and the output element And 4.3 connected to the information input k-bit shift register 4.4, and his k outputs connected to first inputs of elements AND 4.61-4.6k. The outputs of the elements AND 4.61-4.6kconnected to the corresponding inputs of the element OR 4.7. The output element OR 4.7 connected to the first input element And 4.13. The output element And 4.8 connected to the clock input k-bit shift register 4.10, and the output element And 4.9 connected to the information input k-bit shift register 4.10, his k outputs to the first inputs of elements AND 4.111-4.11k. The outputs of the elements AND 4.111-4.11kconnected to the corresponding inputs of the element OR 4.14. The output element OR 4.14 connected to the first input element And 4.12. The outputs of the elements And 4.12 and 4.13 connected to the first and second input respectively of the element OR 4.15. The output element OR 4.15 is the output of the block interleave 4.

Implementation option elements And 4.2, 4.3 the D-flip-flop described in 4.1 /4, page 163, Fig. 4.26/.

An embodiment of the k-bit shift registers 4.4 and 4.10 described in /3, page 209, Fig. 5.6/.

An embodiment of the decoder described in 4.5 /5, page 131, Fig. 1.95/.

Implementation option elements OR 4.7, 4.14, 4.15 described in /5, page 35, Fig. 1.19/.

The phase modulator 6 is designed to change the polarity of the pulses of the reference pseudo-random sequence, forming PSS, in accordance with the polarity of the next samples of the transmitted information sequence. An embodiment of the phase modulator 6 is described in /8, Fig. 11.3 and Fig. 11.4, pages 273-274/.

The generator carrier frequency 13 generates a carrier frequency oscillation. An embodiment of the generator carrier frequency 13 described in /12, Fig. 7.6 and Fig. 7.7, page 212 and 217, respectively/.

The modulator 7 is designed to change phase high-frequency carrier oscillations in accordance with the polarity of the transmitted videokursov. An embodiment of the modulator 7 is described in /12, Fig. 5.13 page 157/.

The amplifiers 9, 23 and additional amplifier 8 are designed to implement the algorithm amplitude manipulation of the PSS (9, 23) and algorithm changes of output signals of the transmission of individual bits of iela 8, 9, 23 described in /4, Fig. 2.2(d), pages 26-40/.

The power amplifier 10 is designed to amplify a high frequency signal to the value needed to compensate for losses in the environment of radio wave propagation. An embodiment of the power amplifier 10 is described in /13, Fig. 11.24, page 327/.

The antenna device 11, 19 are designed to convert high-frequency signal in the radio wave in the transmission (11) and back at the reception (19). An embodiment of the antenna device 11, 19 described in /8, Fig. 7.2 and Fig. 7.4, pages 169-172/.

Synchronization blocks 12, 30 are designed to align with the processes of functioning of pseudorandom sequence generators 14, 31, shift registers 15, 32, registers store the 16, 33 and the control units 3, 27. In addition, the synchronization unit 30 on the receiving side radio controls setting the receiving channel on the received radio signal and determines the moments of reception of received binary pulses in the final block 25. An embodiment of the triggering units 12, 30 described in /9 p. 266-328/.

The pseudorandom sequence generators 14, 31 are used to form the same on the transmitter (14) and receiving (31) the parties to the radio sequences are equiprobable is. 0.20, page 357/.

The shift registers 15, 32 are used to form the sequence (N+1)-bit pseudorandom binary numbers and the implementation of procedures for converting serial data code numbers in parallel. An embodiment of the shift registers 15, 32 described in /3, pages 208-210, for example, Fig. 5.4 (C)/.

The storage registers 16, 33 are designed to hold the parallel code the next pseudorandom numbers over the duration of the formation and processing of a single subcell PSS. An embodiment of the storage registers 16, 33 described in /3, pages 208-210, for example, Fig. 5.4 (a)/.

The decoders 17, 34 and additional decoder 2 are respectively for converting pseudo-random numbers with uniform distribution in the pseudo-random numbers with a specified distribution in accordance with the algorithm uses AFM PSS (17, 34) and to resolve the number of the transmitted bit in the binary code of the gain in accordance with the algorithm uses the energy distribution of signals between the individual bits of information blocks (2). Implementation option decoders 2, 17, 34 described in /4, pages 119-135/.

Digital to analog converters 18, 35 and additional Ajani, managers gain amplifiers respectively 9.23 and additional amplifier 8. An embodiment of the digital-to-analog converters 5, 18, 35 described in /4, pages 185-193/.

The mixer 20 is designed to transfer the received signals to an intermediate frequency. An embodiment of the mixer 20 is described in /12, pages 151-159/.

The local oscillator 29 is designed to generate a frequency offset, which is the difference between the frequency of the received radio signal and the intermediate frequency. A variant of implementation of the local oscillator 29 is described in /4, figure 2.2(g) and Fig. 2.2(K), page 27/.

The intermediate frequency amplifier 21 is designed to amplify the received radio signal to an intermediate frequency to the value required for the subsequent blocks of the receive path. A variant of implementation of the intermediate frequency amplifier 21 is described in /4, Fig. 2.2(g) and Fig. 2.2(K), page 27/.

The multiplier 22 is designed to remove pseudo-random manipulation of the received signal. An embodiment of the multiplier 22 is described in /6, Fig. 4, page 203/.

The integrator 24 is designed for narrow-band filtering of the received signal. An embodiment of the integrator 24 is described in /12, Fig. 6.6(d), page 191/.

RT implementation of the decision making unit 25 shown in /3, pages 363-371/.

The inventive device operates as follows.

In the transmitting part from information source 1 a sequence of binary symbols with velocity V = 1/T0(T0the repetition period of the clock pulses in the first clock output control unit 3) to the input of the multiplier 4, which tracks the boundaries of the blocks of information, including k binary symbols (on the basis of the provisional regulations of clock pulses in the second clock output control unit 3, following with the period T = kT0), and within these boundaries is the permutation information symbols (digits) in accordance with the sequence numbers received in parallel c code control output control unit 3. Synchronously with the receipt of the data numbers corresponding binary symbol is read at the input of the phase modulator 6. This number is fed to the input of the second decoder 2, which forms corresponding to a given number of M-bit binary code of the gain at the input of the second d / a Converter 5, which generates a control voltage that sets the desired gain Westwego conversion in the control unit 3 binary pseudo-random sequence, arriving at the control input of this block with the additional (N+1)-th output of storage register 16.

From the pseudo-random sequence generator (gpsa) 14 with an additional (N+1)-th output of storage register 16 to the second input of the phase modulator 6 is supplied binary signal with pulse width = T0/B, where B is the number of subcells PSS per information symbol. In fact, this number indicates the base PSS. The repetition period of the pulses at the output gpsa 14 equal0= /(N+1) (N is an integer). The signals from the first output of the synchronization unit 12, the repetition period of which is equal to0the sequence of binary pulses from the output gpsa 14 is written in the shift register 15, and then the signals from the second output of the synchronization unit 12, the following frequency f = 1/ register storage 16. With the first N outputs of the storage register 16 N bits of the binary random number R [0,...,2N-1] do for N inputs of the first decoder 17. On the N outputs of the first decoder 17 you receive the N-bit binary number equal to the value of one of the m 2 pseudo-random amplitudes corresponding to the sector number on the unit interval, which gets a random number R/2N(in this case ispolzuya data plots should match the ratio of the probabilities of m different amplitudes of subcells according to the used algorithm AFM PSS /1/. The first digital to analog Converter (DAC) 18 converts the input binary combination in an analog signal corresponding to one of the m pseudo-random amplitudes. From the output of the first DAC 18 the signal at the control input of the first amplifier 9.

The synchronization unit 12 generates two pulse trains with frequencies f and (N+1)f. The second data sequence synchronizes the gpsa 14 and the shift register 15, and the first - synchronizes the operation of the storage register 16 and the control unit 3.

The PSS sequence, transferring the information symbols from the output of the phase modulator 6 is supplied to the modulator 7, in which the phase modulation of the carrier wave supplied to the second input of the modulator 7, a generator carrier frequency 13. Photomanipulating pseudonoise signal output from the modulator 7 is fed to the input of the second amplifier 8, and then to the input of the first amplifier 9, the gain of which change depending on the levels of the signals on the control inputs. From the output of the first amplifier 9 AFM PSS is fed to the input of amplifier 10, where the signal is amplified to the desired level and then through the transmitting antenna 11 is radiated into space.

The synchronization unit 30 generates two pulse trains with frequencies f and (N+1)f, controls the operation mode deciding unit 20, and searches for the AFM signal PSS frequency and time. To search for AFM PSS frequency synchronization unit 30 rebuilds the local oscillator 29, and time delays or accelerates gpsa 31 and its associated blocks. This, along with the juxtaposition in time of pseudo random sequences generated in gpsa 14 and 31, is provided with the 26 after reading the received symbols from the output of the decision making unit 25 on the basis of the sequence numbers, coming from the K outputs of the control unit 27, restores the original sequence of information bits and outputs them to the information receiver 28.

The positive effect of the inventive device will show in the following example.

Let the radio is transmitting digitized analog information in the form of a sequence of independent samples Ut[-UM,+UM] converted to the information source 1 in the k-bit binary code. As indicator of the quality of analog samples will be considered error variance 2aboutWcharacterizing the degree of deviation of the samples taken from the passed.

The total error variance2aboutWthe sum of the variance of the quantization errors2toinand variance of channel errors2toENcaused by the distortions of the individual bits in the communication channel. The variance of the quantization errors (assuming a uniform distribution Utbetween adjacent quantization levels) is determined by the formula2toin= U20/12 where U0= Um/2k-1- step quantization. The variance of channel errors2
< / BR>
When using the radio link with AFM PSS with base B >> 1 action interference with any distribution is asymptotically equivalent to the effect of Gaussian noise /2/. In the worst case, when exposed to the i-th bit of coherent noise with a relative average poweri(allowing for intermittent exposure) the error probability pOsh.ican be calculated by the formula

< / BR>
where

< / BR>
B the expression (2) take into account that wheni< 0.7 B the worst interference is intermittent with a duty cycle of 1-i/0.7 B and the relative power of the noise pulsepeak= 0.7 B.

We denote the ratio of the average interference power to average power of the signals on the duration of transmission of the k bits of one of the analog reference letter . Then, when the energy distribution of interference y = {yi}k and the energy distribution of signals x = {xi}k get i= yi/xi. In Fig. 6 shows graphs of the error variance2aboutWfrom the relative average interference power at different energy distributions of signal and noise at k = 8. In particular, line 1 corresponds to the case of conventional uniform energy distribution signals with a uniform energy distribution of interference, i.e*= {yi*}k with a uniform energy distribution of the signals. This allocation at*depends on the size and is calculated in the General case by numerical solution of the somewhat cumbersome system of differential equations. With a small value for this distribution is characterized by the allocation of all energy interference suppression only senior level, i.e., yk*= 1, y1*=...= yk-1*= 0. With the growth of all most of the energy of interference is allocated to suppress the younger grades. In particular, (k-1)-th digit starts suppressed by > 5.03/k.

By introducing interleave bits can be excluded sighting suppression of high-order bits, resulting in the dependence of the dispersion error on the relative interference power will be guaranteed not above the line 1 in Fig. 6. However, as follows from expression (1) is equal to the error probability of receiving individual bits of the contribution to the error variance of the distortion senior ranks much higher than the contribution of the distortion low. In General, at a known energy distribution of interference, it is possible to solve the corresponding optimization problem and find the best energy distribution of the signals, and then implement it in pronizannoe average power is the best energy distribution of the signals is described by the expression

< / BR>
Note that from the expression (4) follows a simple equation: xi/xi-1= 4, i = 2,...,k, simplifying the implementation of this uneven distribution. When using the energy distribution of the signals (4) guarantees that for any distribution of the interference energy dependence of the dispersion error on the relative average interference power is not above the line 3 in Fig. 6.

As follows from the graphs in Fig. 6, when using uneven distribution (4) energy signals in line with AFM PSS guaranteed energy gain in the region of small noise about 13 dB compared to the case with uniform distribution without alternation and about 5.5 dB compared to the case with uniform distribution with alternation. In Fig. 6 shows graphs of the dispersion error on the relative interference power at different energy distribution of signals and interference between the bits of the digitized analog samples.

Literature

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2. Chudnov A. M. the correlation Immunity of a reception pseudo-random signals, modulated in amplitude and phase // radio engineering and electronics, 1987. ptx2">

4. Batashev Century A. Circuits and their application. M.: Radio and communication, 1983. - 271 S.

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6. Papernov A. A. Logical framework CHT. M: Communications, 1973. - 352 S.

7. Chudnov A. M. On the minimax algorithms of generating and receiving signals. // Problems of information transmission, 1986, I. XXII. - vol. 4, S. 49-54.

8. J.Spilker. Digital satellite communications. M: Communications, 1979. - 592 S.

9. Varakin L. E. communication Systems with noise-like signals. M.: Radio and communication, 1985. - 384 S.

10. Banquet Century A. Dorofeev, C. M. Digital techniques in satellite communications. M.: Radio and communication, 1988. - 213 S.

11. U. Titze, K. Schenk. Semiconductor circuitry: a reference guide. M.: Mir, 1982. - 512 S.

12. A receiving device, Ed. L., Barulin. M.: Radio and communication, 1984. - 272 S.

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14. Macaw A. A., szczerba Century, the Interfaces of the data processing systems. M.: Radio and communication, 1989. - 416 S.

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The wireless link with the amplitude-photomanipulating noise-like signals with a transmitting-side information source, a phase modulator, modulator, oscillator carrier frequency, the first amplifier, power amplifier, antenna device, the synchronization unit, the pseudo-random sequence generator, shift register, the register storing the first decoder, the first d / a Converter, and the output of the phase modulator connected to the first input of the modulator, the output of the generator carrier frequency is connected to the second input of the modulator, the first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and the clock input of the shift register, and its second output to the clock input of storage register, the output of a pseudorandom sequence generator connected to the information input of the shift register, N + 1 informational outputs of the shift register, where N is 2, is connected to the corresponding N + 1 to the information inputs of the storage register, N informational outputs of the register storing the connected storage connected to the second input of the phase modulator, N outputs of the first decoder connected to the respective N inputs of the first digital to analog Converter whose output is connected to the control input of the first amplifier, the output of which is connected to the input of the power amplifier, the output of which is connected to the input of the antenna device, and at the receiving side contains a receiving antenna, a mixer, an intermediate frequency amplifier, a multiplier, amplifier, integrator, the deciding unit, a local oscillator, the synchronization unit, the pseudo-random sequence generator, a shift register, a storage register, a decoder, a d / a Converter and receiver information, and the output of an antenna device connected to the first input of the mixer, the mixer output is connected to the input of the intermediate frequency amplifier, the output of which is connected to the information input of the multiplier, the output of which is connected to the information input of the amplifier, the output of which is connected to the input of the integrator, the output of which is connected to the input of a casting device and the input of the synchronization unit, the first output of the synchronization unit is connected to the input of the pseudo-random sequence generator and the clock input of the shift register, the second output of the synchronization unit connected to the tact is connected to the second input of the mixer, the fourth output of the synchronization unit is connected to the clock input of the decision making unit, the output of a pseudorandom sequence generator connected to the information input of the shift register, N + 1 informational outputs of which are connected to the respective N + 1 to the information inputs of the storage register, N informational outputs of which are connected to the corresponding N to the information inputs of the decoder, and the additional (N + 1)-th output of the storage register connected to the control input of the multiplier, N outputs of the decoder are connected to the respective N inputs to analog Converter whose output is connected to the control input of the amplifier, characterized in that additionally introduced on the transmission side control unit, block alternation, the second decoder, the second d / a Converter and the second amplifier, and the output of an information source connected to the information input unit interleave, output block alternation connected to the first input of the phase modulator, an additional (N + 1)-th output of the storage register connected to the control input of the control unit, the second output of the synchronization unit is connected to the clock input of the control unit, the first and second sinhroniziruete interleave, and K control output of the control unit, where K 2, connected to the corresponding K control inputs of the block interleave and K inputs of the second decoder, the M outputs of the second decoder, where M 2, each connected to the M inputs of the second digital to analog Converter whose output is connected to the control input of the second amplifier, the information input of the second amplifier connected to the output of the modulator, and the output of the second amplifier to the information input of the first amplifier, and at the receiving side have been added to the block interleave and the control unit, and the second output of the synchronization unit is connected to the clock input of the control unit, and the additional (N + 1)-th output of the storage register connected to the control input of the control unit, the first and second clock outputs a control unit connected to the respective clock inputs of the block interleave, and K control output control unit connected to the corresponding K control inputs of the block interleave, output deciding unit connected to the information input unit of alternation, and the output of block alternation connected to the input of the receiver information.

 

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