Dual-mode communication system with frequency modulation and multiple access, code-division multiplexing
(57) Abstract:The proposed dual-mode digital communications system for transmission of the information signal when the mode using frequency modulation (FM) and multiple access. Digital communication system contains a dual mode transmitter for transmitting the information signal using FM communication signal when operating in the FM mode and to transmit the information signal using the communication signal mode multiple access mode multiple access. The communication system also includes dual-mode receiver for receiving FM communication signal when the mode using the FM and for receiving communication signal mode multiple access mode multiple access. Dual mode receiver includes a digital demodulator (96) for recovering the information signal from a received FM signal mode using the FM and for recovering the information signal from a received signal mode multiple access mode multiple access. The technical result is to provide filtering in the base band without loss of information on the carrier frequency. 2 S. and 4 C.p. f-crystals, oncrete, the present invention relates to a new dual-mode communication system selectively operating in either the world Cup, and in the mode multiple access code division multiplexing (mdcr).Prior art
The demodulation of the received FM signal communication is traditionally performed using analog signal processing techniques. However, recently developed methods that allow you to process the analog communication signals using digital signal processing techniques. Among such methods include methods of sampling phase and discrimination incoming signal to recover information transmitted messages. The information contained in the messages, often restored using, for example, quadrature methods of detection.One method of FM demodulation signal suitable for digital implementation is the so-called "direct conversion". When using the method of direct conversion or zero intermediate frequency in the receiver is made by mixing the incoming RF signal by converting it directly in the frequency band modulation (base band). The advantage of the change directly in the base strip, and therefore, it can be profitably implemented using integrated circuit technology.The lack of direct conversion demodulation associated with the emergence of the parasitic voltage bias DC component, which can occur at the output of the mixer together with the useful signal of the base band, which may also contain spectral components DC. Parasitic offset voltage DC component can also be caused by shifts by a constant current, resulting in a cascade mixer and signal leakage of radio frequency local oscillator subjected to downward transformation to the frequency of the DC. The impact of such unwanted DC offsets on the process of demodulation of FM signal can be modeled, for example, in the form of non-linearity contained in the ideal demodulated signal. The value of the resulting distortion, i.e., "bias error", is a function of the magnitude of the DC offset relative to the envelope of the FM signal. For typical applications using valid audio fidelity requires displacement errors were less than a few percent. Therefore, sushestvu unwanted DC offsets.In addition, digital receivers, operating on the principle of direct conversion, have a relatively narrow dynamic range. For handling the dynamic range of the received FM signal, it is necessary to provide an additional circuit for automatic gain control (AGC). In a typical case in digital receivers procedure ARU includes detection, analog-to-digital conversion and measurement in the base-band power of the incoming signal. The measured value is compared with a useful reference value and generates an error signal. The error signal is filtered by the filter circuit AGC, and the filtered digital output signal is used to adjust the amplifier gain so that the signal level coincides with the desired signal. For digital demodulation with optimal signal-to-noise AGC is used to maintain the signal values of the base strip close to the full dynamic range of the analog-to-digital converters (ADC) base strip. However, in the General case, this requires ensuring that amplifiers with AGC blocked the full power dynamic range of received signals.
The present invention relates to a new dual-mode digital communications system for transmission of the information signal when working in it for transmission of the information signal using FM communication signal when operating in the FM mode and to transmit the information signal using a signal with a quadrature phase shift keying (Kfmn) spread spectrum when operating in mode mdcr.The communication system also includes a dual-mode receiver for receiving FM communication signal when operating in the FM mode and for receiving a signal from Kfmn spread spectrum when operating in mode mdcr. Dual mode receiver also contains a digital demodulator for recovering the information signal from a received FM signal when operating in the FM mode and for recovering the information signal from a received signal with Cfmn when operating in mode mdcr.As for the dual-mode receiver, the demodulator FM signal may be included in a digital demodulator for converting the digitized received FM signal communication base strip, preferably with a center frequency at a predefined frequency of the base band shifted relative to the zero frequency, the recovered information signal. The conversion is performed so that each digital sample of the received signal of the base band included the first and second components of the sample in phase quadrature. In a preferred embodiment, the demodulator FM signal initially provides the calculation of the ratio of the first and second components of each digital sample of the input signal. Vasodilatorany integration signal, equivalent demodulated informational signal is determined by filtering the demodulated phase sequence using a digital block differentiation.Brief description of drawings
Fig. 1 is a block diagram of the dual mode digital communication system corresponding to the invention.Fig. 2 is a block diagram of the interpolation filter audio designed for use in dual mode transmitter of the communication system corresponding to the invention.Fig. 3A - 3D set of discretized broadband sinusoidal signals generated by the generator of the broadband signal included in the dual-mode transmitter in the FM mode.Fig. 3E is a view in tabular form the information illustrated in Fig. FOR 3D.Fig. 4 is a block diagram of the preferred alternative implementation of the signal generator broadband data.Fig. 5 is a block diagram of the block summation and gain control, part of the dual-mode transmitter.Fig. 6 is a block diagram of the multiplexer mdcr/FM, ensuring selective signal mode mdcr and digital FM signal for RF transmitter.about the composition of the dual-mode receiver, corresponding to the invention
Fig. 8 is a block diagram of the in-phase channel component of the system of compensation of the offset DC.Fig. 9A is a block diagram of the preferred alternative implementation of the filter circuit of the sample contained in the circuit of the filter circuit compensate for the offset DC channel in-phase component.Fig. 9B is a table of time constants corresponding to the tuning of the circuit correction DC when operating in modes of tracking and capture.Fig. 10 is a block diagram illustrating the oscillator quadrature phase values, included in the quadrature demodulator FM signal.Fig. 11 is a block diagram of the preferred alternative implementation of the generator for converting the phase in the frequency included in the quadrature demodulator FM signal.Fig. 12A is an illustration of the digital AGC circuit for adjusting the gain of the if signal.Fig. 12B is a block diagram illustrating the preferred implementation of the indication unit signal for the circuit of the digital AGC.Fig. 13A - preferred implementation of the circuit of the digital AGC containing the integrator and b is m selected gain settings of the AGC circuit.Fig. 14A is an illustration of the preferred alternative implementation of the circuit of the tracking frequency, part of the dual mode receiver corresponding to the invention.Fig. 14B is a table of the time constant circuit monitoring frequency corresponding to the selected constant time circuit gain control.Fig. 15 is a block diagram of the preferred alternative implementation of the decimation filter of the audio signal included in the dual mode receiver corresponding to the invention.Fig. 16 is an illustration of the implementation of schemes for the restoration of broadband data.Fig. 17 is a block diagram of the interpolation filter included in the restoration schemes broadband data.Fig. 18A is a block diagram of circuits of a recovery synchronization and decoding using the Manchester code.Fig. 18B is a table of time constants and values of the bandwidth circuit for fasolada circuit in the decoding scheme using the Manchester code.Fig. 19A is a schematic representation of a decoder of the type no return to zero", which is part of the restoration schemes broadband data.Fig. 19B is a table illustrating the operation of logicism the first description of a preferred variant embodiment of the invention
In Fig.1 presents an example of implementation of dual-mode digital communications system corresponding to the invention. Dual-mode communication system contains a dual mode transmitter 14, for transmitting digital information signals to the dual-mode digital receiver 16. In digital mode FM transmitted digital information signals are generated in the dual-mode transmitter via FM radio frequency carrier on the basis of digitized audio signals and broadband data signals. In the mode of operation multiple access information transmitted signals include, for example, information signals mdcr type. The signal selection modes FM and mdcr supplied to the transmitter 14 through a control processor (not shown), provides a selection of either mode digital FM or mode mdcr.1. General characteristics of the dual mode transmitter
As shown in Fig. 1 channel digital FM transmitter 14 provides reception discretized information of the audio signals 18 from the digital signal processor 20, and receiving the serial stream of binary data messages 21 from the control processor (not shown). In the present embodiment, dis is biosignal transmitter 14 with a speed of 20 televisores per second (kvib./C). As described below, the interpolation filter 42 converts the sampled audio data at a speed of 20 quib./with the flow with a speed of 120 quib./with discretized data of the audio signal 44, and each audiolibro 44 consists of 10 bits. Sampled audio data 44 are then combined in the summation and gain control 48 discretized with a broadband data signal 50 generated by the generator 54 broadband data.The composite digital signal of frequency modulation 58 generated by the unit summation and gain control 48, is supplied to the mode select switch 60 in the structure of the transmission interface mdcr/FM signals. In the mode using the FM signal selection switch modes 60 delivers the digital signal of frequency modulation for digital-to-analogue Converter (DAC) 62. The transmitter 64 RF signal received analog signal frequency modulation directly modulates the carrier FC. In more detail, the method of generating a digital signal of frequency modulation in accordance with the invention is described below with reference to Fig.2-4.After switching from digital FM mode mdcr signal mode data mdcr supplied PCIe. Mode mdcr transmitter 64 generates in-phase (I) and quadrature (Q) pseudosolenia sequences PNI and PNQ, which typically correspond to a specific area (cell to cell communication), in which information is transmitted in mode mdcr. The transmitter 64 data signal mdcr processed according to the scheme "Exclusive OR" with sequences PNI and QNI to provide spread spectrum data signal mode mdcr before its transfer. The resulting sequence spread spectrum in-phase channel (I-channel) and quadrature channel (Q-channel) are used for two-level phase modulation of a pair of sinusoidal signals in quadrature. Modulated sinusoidal signals are summed, filtered in the band, is converted to radio frequency and again filtered and amplified before their radiation antenna 70 through the communication channel to the dual-mode receiver 16. The variant of implementation of the transmitter and the signal generator mode mdcr described, for example, in U.S. patent N 5103459, issued in 1992, for "System and method for generating signals in a cellular telephone system with mdcr", assigned to the assignee of the present invention and are mentioned here for reference.2. About the roadways to the antenna 80 for receiving information signals I - channel and Q - channel, the transmitted dual mode transmitter 14. As in mode mdcr and digital mode FM, the information signals of the I - channel and Q - channel received by the antenna 80, are processed by the analog receiver 84 direct conversion. In an analog receiver 84 information signals I - channel and Q - channel are mixed with the lo signal for forming in-phase (I) and quadrature (Q) signals of the base band. In digital mode FM frequency of the local oscillator is selected shifted by a predefined amount relative to the RF carrier. In this way received I and Q information signals are converted into I and Q signals to digital FM base strip is offset from zero frequency, i.e., from zero if at a predefined value.As mentioned above, in the conventional direct conversion receivers FM signal any spurious signal energy is constant component contained in the input signal is directly displayed in the band at the zero frequency, relative to which centered quadrature components of the useful signal of the base band. In the subsequent evaluation phase angle can be distorted by the offset frequency, deliberately introduced into the analog receiver 84, allows to eliminate this parasitic energy signal DC component when processing the I and Q signals of the base band.Mode mdcr components in-phase and quadrature channel signal mdcr in the base band are served through output lines 88 and 90 to the ADC 92 interface receiver for mdcr and FM. Then signal components mdcr base strip is transferred from the ADC 92 to the processing circuit 94 mdcr signals. In the processing circuit 94 mdcr signal components of the signal mdcr base strip demodulators, are separated and decoded, for example, hook described in U.S. patent N 5103459.In digital mode FM in-phase and quadrature signals of the base band served on the ADC 92 on the output lines 88 and 90 of the receiver. The ADC 92 in-phase and quadrature signals of the base band digitized with the speed of the sequence of samples, for example, 40 quib./for the formation of 8-bit in-phase and quadrature samples. The received 8-bit in-phase and quadrature samples are served with a speed, for example? 40 quib./with the demodulator 96 I/Q samples of the FM signal. In the demodulator of the digital FM signal in-phase and quadrature signals of the base band demodulated with policee, the demodulator digital FM signal 96 also includes a circuit to monitor the DC offset is designed to eliminate bias DC component introduced in the radio-frequency processing in the receiver 84, the AGC circuit and circuit tracking frequency.As shown in Fig. 1, the digital FM demodulated by the frequency signal with a speed of, for example, 40 quib./with both the decimation filter 102 audio and recovery scheme for broadband data 104. After processing by the decimation filter 102 audio signal sampled with a lower frequency of samples that is applied to the vocoder (not shown) for recovery of the received audio information. Simultaneously with this recovery scheme broadband data 104 provides the allocation of the received broadband data and synchronization information from the demodulated by the frequency of the signal. This selected information of the wideband signal is then used by the decoder messages broadband data 108 to identify a frame of code words of broadband data, error correction bit and for directing the identified code words and messages in the control processor for further evaluation.3. Detailed product description product the s block diagram of the interpolation filter 42 of the audio signal. As shown in Fig. 2, each 12-bit sampling audio data from the CPU 20 of the digital signal is transmitted at a speed of 20 quib./with on line 18 to the storage register 140 zero order in the structure of the interpolation filter 42 of the audio signal. The output signal of the storage register 140 zero-order discretized using interpolation switch 44 with a frequency equivalent to a pre-defined integer multiple of the speed of the input data. In a preferred embodiment, the switch 144 has a switching frequency of 120 kHz, i.e., corresponds to six times the speed of the input data. The resulting audio data sampled at a rate of 120 KB/s, then sequentially processed SINC filter 148 with 8 outlets and SINC filter 152 with 4 taps. The filters 148 and 152 may be characterized by the following conversion functions T8 and T4 in the z-region:
T8=(1+ z-1 + ... + z-7)/8;
T4=(1+ z-l = ... = z-3)/4,
The filter 152 with 4 taps provides the flow with a speed of 120 KB/s discretized audio data 44, and each sample of audio data 44 consists of 10 bits.C. the signal Generator broadband data
In a preferred embodiment, the generator 54 signal broadband data provides direct this message 21 consists of a sequence of binary data without returning to zero (BVD), the generator 54 provides encoding Manchester code sequence BVD data, and synthesizes the modulating signal with FMN. Each logical unit of the BIA data encoded in Manchester code into a sequence of zero-one, and each logical zero BVD data encoded in Manchester code into a sequence of one or zero. To limit the spectral bandwidth of the resulting signal is modulated using FMN, idealized transitions Manchester sequences are synthesized as sinusoidal transitions. Generator broadband data preferably is designed to eliminate the need for low-pass filtering the modulation signal broadband data prior to frequency modulation of the carrier.In Fig. FOR - 3D presents a set of discretized broadband signals generated by the generator 54 in response to different pairs of bits BVN data. The first bit in each pair of bits WBD data is identified on the horizontal axis in Fig. FOR 3D recording X(n-1), and the second bit is identified by the entry X(n). As shown in Fig. 3A - 3D, the twelve samples are generated in response to each bit BVN data for forming sinusoidal the check, corresponding to the last six samples of Manchester data for FU-bits X(n-1) and the first six samples of Manchester data for FU-bits X(n). Synthesized signal values defined by the predefined constants +/- s0, s1, s2 and s3. The information illustrated in the graphs of Fig. 3A - 3D, are presented in tabular form in Fig. 3E.In Fig. 4 presents a block diagram of the preferred option run generator 54 broadband data. In the example of Fig.4 input binary BVN data are served with a speed of, for example, 10 KB/s and discretized Manchester view is formed at a rate of 120 quib./with resolutions of samples equal to 10 bits. The generator 54 includes a register 160 BVN data for storing successive pairs of binary BVN data X(n-1), X(n). The input multiplexer 164 generates a sequence of values s0, s1, s2 and/or s3, based on the values X(n-1) and X(n) stored in register 160. For example, in Fig. 3E shows that for X(n-1) = 0 and X(n) = 1 multiplexer 164 will generate a sequence s0, s1, s2, s3, s3, s3, followed by the sequence s3, s3, s3, s2, s1, s0. These sequences and the inverse values of these sequences formed the Noah multiplexer 172 generates a sequence s0, -s1, -s2, -s3, -s3, -s3, respectively second half of X(n-1) = 0 and sequence-s3, -s3, -s3, -s2, -s1, -s0, respectively, the first half of X(n) = 1. In the General case, the output multiplexer 172 selects between the sequence generated by the input multiplexer 164, and a complementary sequence, generated by an inverter 168 to generate a discrete signal associated with a pair of VBN values X(n) and X(n-1) stored at the moment in the register 160.C. Unit summation and gain control
In Fig. 5 presents a block diagram of the block summation and gain control 48. The unit 48 includes a digital adder 178 to join discretized audio data 44 with discretized signal broadband data 50 (Fig. 4). The resulting 10-bit discretized signal frequency modulation is then scaled using a multiplier 180 using 6-bit constants GADJgain control. The constant GADJselected to compensate for any deviations from the desired response characterizing a voltage dependence of the frequency of voltage-controlled oscillator (not shown) in the radio frequency transmitter 64. Signal 58 digital is diplexer 60 modes mdcr and the world Cup.D. d / a converters interface for mdcr and world Cup
In Fig. 6 presents a block diagram of the multiplexer 60 modes mdcr and FM. As shown in Fig. 6, the data multiplexer 190 receives as data mode mdcr and signal 58 digital frequency modulation. A corresponding data stream is multiplexed and transmitted to the DAC 192 for conversion to an analog signal before feeding to the RF transmitter 64 (Fig. 1). The selection of the digital input stream for transmission to the exit is made when the control signal mode selection FM/mdcr input to the multiplexer 190. Similarly, either the clock signal for the mode mdcr, or the clock signal for the digital FM signal is fed to the DAC 192 for the implementation of the synchronization procedure of data conversion with bronirovanie input data sequence (FM or mdcr).4. A detailed description of the dual mode receiver
A. a Demodulator of a digital FM signal to base band
1. General features
In accordance with Fig. 1, when operating in the FM mode 8-bit in-phase and quadrature samples are issued with ADC 92 interface reception modes mdcr/FM with a speed of 40 quib./with the demodulator 96-phase and Quadros and quadrature components of the FM signal shown in Fig. 7. In-phase and quadrature samples, respectively represent the real and imaginary parts of the complex vector representation of the broadband equivalent of the received FM signal. In this example, the implementation of the broadband equivalent signal is transferred to the frequency of the base band is offset from zero frequency (i.e., 0 Hz) to a predefined value. As noted above, the analog receiver 84 provides a mapping of these received signals, which are offset from the center frequency of the radio frequency signal to a predefined value, for example 150 Hz at zero frequency. This offset DC allows the distinction between unmodulated FM signal, i.e., a continuous signal, and offset errors DC, introduced by analog processing. In accordance with one aspect of the invention, the displacement errors DC remain at zero frequency, while the transferred frequency signal DC component is displayed at a non-zero frequency of the base band equivalent to a predefined offset frequency (for example, 150 Hz). As operatornode (Q) channels are designed to eliminate this bias DC current in the receive channel signal before further processing by the demodulator 96-phase and quadrature components. Chain correction, DC 210 and 212 provide effective Troubleshooting bias DC without making misrepresentations in the information contained in the signal DC component.The demodulator 96 FM signal, in addition, contains a generator 214 in-phase and quadrature phase values intended for formation evaluation phase angle of the vector of the received FM signal. The function represented by the generator 214 in-phase and quadrature phase values may be represented as follows:
where P(n) denotes the phase angle related to the sample vector FM signal is defined components of I(n) and Q(n). Example determine the function of the arctangent in the four quadrants, allowing to estimate the phase angle P(n) may be represented as follows:
(ii) to determine the assessment phase of the Pein the range from 0 to /4, where Pe(n) = TAN-1(B)
(iii) to display the evaluation phase of the Pein the range from - to , based on the relative values of modules and the I and qThe above defines a possible way to perform the calculation of the arctangent in the four quadrants. It is clear that the experts in this field tehnaz with generator 214 in-phase and quadrature phase values is converted into a frequency signal by a generator 218 phase conversion in frequency. In this embodiment, to the input of the generator 218 phase conversion in the frequency is served 8-bit normalized signal phase P(n), where 0 < P(n) < 2. Function differentiation performed by the generator 218 phase conversion in frequency, can be mathematically represented as follows:
F(n)=P(n) - P(n-1),
where F(n) - sampling frequency obtained from the normalized sampling phase P(n) and P(n-1). In a preferred example, the sampling frequency F(n) are normalized relative to the sequence of samples FN(n) so that -1 < FN(n) < 1. Generator 214 in-phase and quadrature phase values and the generator 218 phase conversion in the frequency described below in more detail with reference to Fig. 10 and 11.As shown in Fig. 7, the block determining the level of a received signal 220 calculates an estimate of the level of the received signal, based on the parameters provided by generator 214 in-phase and quadrature phase values. The resulting signal indicating the level of a received signal used in the digital AGC circuit 222 to generate digital AGC signal, which is then converted to an analog signal with AGC DAC 224.As shown in Fig. 7, the filter circuit 250 with the frequency. The filter 250 chain tracking frequency generates a digital signal that is converted to an analog signal monitoring frequency (FTRAK) with DAC 251. The signal FTRACKan analog receiver to tune the frequency of the lo signal used Panigale converting a received RF signal. As noted above, the energy of the FM signal in-phase and quadrature channels are often tolerated in an analog receiver 84 to the frequency of the base band other than 0 Hz, in order to facilitate an exception offset errors DC. Accordingly, in the filter circuit 250 tracking frequency is provided by a predetermined constant offset frequency (FBIAS), to deduct from the processed samples frequency FN(n) to provide compensation offset in the base band input analog receiver 84.2. Job description FM demodulator signal
In Fig. 8 presents a block diagram of the filter circuit correction, DC 210-phase (I) channel. It is clear that the filter circuit correction, DC 212 quadrature (Q) channel is identical to the filter 210. As shown in Fig. 8, the signal correction, 260 phase to the second strip. The filter correction circuit 210 is designed so that the correction signal offset 260 in-phase channel approximates any parasitic offset DC current present in the path of the in-phase channel. In this way compensated signal generated by the subtraction unit 262, essentially becomes free from errors bias DC.During the operation of the digitized in-phase signal channel output AP 266 in the receiver 84 is sampled and filtered in the filter chain sampling 270. The resulting digital signal correction in-phase channel is then converted to an analog signal correction 260 in-phase channel by means of the DAC 272 and is supplied to the subtraction unit 262.In Fig. 9A presents the preferred implementation of the filter circuit sampling 270. The filter 270 includes a register 276 allocation senior level to supply high-order, i.e., the sign bit 8-bit output ADC offset register 278. The time constant of the filter circuit correction, DC 210-phase channel can be controlled through adjustment of the number of bits of the shift 280, which together with the signal offset 282, complementary to Dura shift 278 is supplied to the drive 286, which forms the 21-bit accumulated output signal, advanced at the expense of the sign, the 9-bit selection scheme senior level 290. Selection scheme 290 transmits the nine high-order bits of the 21-bit accumulated digital signal correction offset to the DAC 272 (Fig. 8), which generates an analog signal correction 260 in-phase channel.More specifically, in the table shown in Fig. 9B, illustrates the way in which shifts bits made in the shift register 278, set the time constant circuit correction, DC. As shown in Fig. 9B, the circuit correction DC operates as in the tracking mode, and capture mode. Work in capture mode is characterized by a more permanent short-time circuit that provides a fast initial convergence correction. A relatively short time constants of the circuit used in the capture mode, increase the bandwidth of the circuit with respect to the width of the strip in the tracking mode, which causes a large offset errors in the capture mode than in the tracking mode. Conversely, longer time constants of the circuit and, consequently, a more narrow width floor is ukrainee operation provides the possibility of achieving initial convergence with minimum delay and at the same time optimize performance in steady state.In Fig. 10 presents a block diagram of the generator 214 in-phase and quadrature phase values. Generator 214 contains schema binary conversion 296 and 298 in-phase and quadrature channels to determine the sign and magnitude data of the base band to in-phase and quadrature channels. In the preferred embodiment, these data are presented schemes binary conversion 296 and 298 in-phase and quadrature channels in binary form with offset.For the data of the base band binary offset schema transformation 296 and 298 function, are presented in Table 1. Namely, if the high order bit of the input sample data base strip is a logical unit, then the absolute value (i.e., or ) of the sample is equivalent to eight younger discharge sampling, otherwise the absolute value obtained by inverting the eight least significant bits. Schema transformations also form a significant value of Iand Qrespectively, indicating the signs of the current data samples of the base band in-phase and quadrature channels.As shown in Fig. 10, the digital comparator 302 compares the values and submits min respectively on digital Affairs management CI/Qset to 1. Otherwise, the control signal CI/Qset to 0.The divider 306 generates the 6-bit signal RATIO (ratio), defined as the Signal RATIO is served at the table ARCTAN ROM function arctangent) and serves as a pointer for table 316. More specifically, the function THETA = arctan (RATIO) is memorized in the table 316. The index RATIO is in the range from 0 to 63 in accordance with the decimal range from 0 to 1, and the calculated values of THETA are in the range from 0 to 31, respectively decimal range from 0 to 4 In the example table 316 ARCTAN ROM contains a set of 64 5-bit estimates of the phase, as presented in table 2.As shown in table 2, in table 316 ARCTAN ROM is stored only "basic values" of the phase information. I.e. in order to save memory space table ARCTAN ROM includes only values 1/8 plane polar coordinates, i.e., from zero to 4. Accordingly, the determining module of the octant 320 provides the formation of the output sequence P(n) of phase values by turning theTA values obtained from table 316 ARCTAN ROM, to the right of the octant. The procedure for determining the octant is performed using ratios 1 > 0, Q > 0, i.e., using C is performed by the block determining the octant 320, in relation to theTA values associated with the respective combinations of I+/-, Q+/-CI/Q.Logical operations performed to calculate the phase values, are shown in table 3, can be equivalently expressed in the following form:
PHASE  = Q+/-;
PHASE  = I+/-EXCLUSIVE OR Q+/-;
PHASE  = CI/QXOR I+/-EXCLUSIVE OR Q+/-;
PHASE [4...] = CI/QXOR I+/-EXCLUSIVE OR Q+/-EXCLUSIVE OR THETA [4...],
where PHASE [i] indicates the i-th bit 8-bit unsigned values, and bit 0 is the low order.In Fig. 11 presents a block diagram of the preferred option implementation generator 218 phase conversion in frequency. Generator 218 is designed to convert the sequence of phase values P(n) generated by the generator phase I/Q 214 in the normalized sequence of values of frequency FN(n). And again, the function of the differentiation performed by the shift register 330 and a digital adder 332 generator 218 phase conversion in the frequency can be mathematically represented in the form F(n) = P(n) - P(n-1). The detection range 334 is designed to moreruela example is the specification of the range is calculated modulo 2. For example, the specification of the range of P(n) = 1,1 modulo 2 displays this value in the normalized frequency FN(n) = - 0,9. This arithmetic summation modulo 2 eliminates any ambiguity in the calculation of the phase difference resulting from cycles of phase, "cheat" around the unit circle. The frequency samples are then processed using a filter decimation of the audio signal 102 and restoration schemes 104 broadband data, as will be described below.In Fig. 12A shows the block diagram of the digital AGC circuit for adjusting the gain of the if signal generated by the receiver 84. The digital AGC circuit includes a display unit of the signal level 220, the diagram of digital AGC 222 and DAC 224. In the operation of the AGC circuit signals indicating the level of the received signal, formed by the display unit of the level of received signals 220 based on the values generated by the demodulator I/Q 96. As shown in Fig. 12A, in the AGC circuit provides digital subtraction unit 340 for subtracting the reference level AGE_REF from the output signal indicating the level of a received signal. The resulting error signal is integrated by the integrator 342 in the filter circuit and then fed to the DAC 224.Analog AGC signal from the DAC 224 filmic. The amplifier 350 provides a linear (in dB) gain control over a wide dynamic range. The amplifier 350 may be such as described in U.S. patent N 5099204 on "Amplifier with linear gain control", assigned to the assignee of the present invention.Below is a generic description of processing in the base band performed in the receiver 84. More specifically, the adjustable level of the if signal from amplifier with AGC 350 is transferred to the frequency of the base band using a mixer 354. As indicated above, the frequency of the lo signal applied to the mixer 354, is chosen so that the Central VFD display to the frequency of the base band shifted from zero Hz. The signals I and Q base band generated by the mixer 354, then filtered and converted into digital form in block 358 LPF and ADC before passing them on to the interface 92 modes mdcr and FM receiver.In Fig. 12B presents the preferred implementation of the block indicating signal 220. Block level indication 220 provides the function 10 log10(I2+ Q2). This function can be in the alternative form as follows:
< / BR>Values can be polychemotherapy phase. The calculations are performed in the first and second blocks 370 and 372 logarithmic functions that can be performed using, for example, lookup tables in ROM programmable logic arrays or conventional logic circuits. The signal indicating the received signal is then obtained by combining the output signals of blocks 370 and 372 logarithmic functions in a digital adder 374.In Fig. 13A presents the preferred implementation of the digital subtraction unit 340 and integrator 342 digital AGC circuit 222. As shown in Fig. 13A, the signal AGC_REF from register 344 is supplied to the subtraction unit 340 together with the signal level indication (RSSI) with a schematic indication of the level of the received signal 220. In this example of implementation, the parameter AGC_REF is a 5-bit constant is loaded into the register 344 by a control processor of the receiver. As shown in Fig. 13A, 5-bit signal AGC_ REF predefined constants with the control processor is served along with a 7-bit signal RSSI block display signal 220 to the subtraction unit 340. The resulting difference (i.e., error signal) between the value of the RSSI signal and the useful signal level (AGC_ REF) = O a1a21SHIFT. In this embodiment, the fractional components (a1and2contain the 2-bit values, and the arithmetic left shift, specified by the parameter SHIFT is a 3-bit value. As an example, for a1= 1, a2= 1 and SHIFT= 3 is equivalent to the amplification circuit is equal to 0,11 2-3(binary value) or 3/32 (in decimal value).As shown in Fig. 13A, the procedure of fractional scaling is implemented as a full multiplication, and the shift is performed as an arithmetic left shift. Two predefined constant signal amplification circuit, respectively defined as AGC_Attack and AGC_Decay fed to the AGC circuit. Each of these signals consists of a 2-bit segment representing the components of the gain a1 and a2, and a 3-bit segment representing the SHIFT parameter. The sign bit signal of the error signal determines the scaling by signals AGC_ Attack and AGC_Decay. If this sign bit is positive (i.e., logic 0), the error is scaled by the gain determined by the signal AGC_Decay. For a positive error signal, the AGC circuit will reduce the signal by reducing the gain of the amplifier with AGC. In this smuclovisky way in the presence of the negative error signal of the AGC circuit increases the signal level by increasing the gain of the amplifier with AGC. Under these conditions, the amplification circuit and the time constants are determined by the value AGC_Attack.The choice of the time constant circuit is carried out in accordance with the desired balance that must be struck between the ability of the tracking signal level of the AGC circuit and the degree to which the signal level of the base band must be supported by the limited dynamic range of the DAC of the receiver with AGC. In Fig. 13B presents the parameter values corresponding to the taken for example to set the time constant circuit.In accordance with Fig. 13A, scaled 8-bit level error signal into a 14-bit integrator with saturation 342. In addition, the 6-bit pre-defined upper and lower saturation levels (AGC_ Max, AGC_ Min) integrator 342 fed to the AGC circuit by a control processor of the receiver. The integrator 342 provides a reduction of the average error signal to zero, which is equivalent to minimizing the difference between the average estimate of signal strength (RSSI) and the desired signal level (AGC_REF). Limit values of saturation (AGC_Max,allaudio voltage amplifier with AGC. Seven bits are allocated from the output signal of the integrator 342 is fed to the DAC 224 (Fig. 12A), which again provides a gain control amplifier with AGC.In Fig. 14A presents the preferred implementation of the circuit of the tracking frequency, part of the dual-mode receiver. As shown in Fig. 14A, the filter circuit monitoring frequency 250 includes a digital subtraction unit 390, served on an 8-bit signal demodulated frequency generator 218 phase conversion in frequency. The subtraction unit 390 is designed for subtracting an offset signal frequency (FBIAS), which in this embodiment is roughly equivalent to one bit younger frequencies (i.e., 156 Hz) 8-bit demodulated signal frequency. The resulting differential signal is supplied to the shift register 392 and bitwise shifted in accordance with a constant gain circuit monitoring frequency FGAIN. Table 14B shows time constants of the circuit monitoring frequency associated with different constant gain FGAIN.The output signal of the shift register 392, advanced at the expense of the sign, is then passed to the digital memory 394. In this embodiment, the implementation is Asano in Fig. 14A, the output signal of the drive 394 in the form of 8 bits is supplied to the DAC 251. It should also be borne in mind that when working in mode mdcr signal tracking frequency mdcr can be multiplexed DAC 251 instead of the output signal of the drive 394.Signal tracking frequency FTRACKgenerated by DAC 251, is used to adjust the lo frequency 396, part of the RF stage receiver 84. The receiver 84 also contains a mixer 398 to move the frequency of the received RF signal in accordance with the applied frequency of the local oscillator 396. The resulting if signal is then fed to a cascade of processing on the inverter 402, the output of which is sampled ADC 266 and is supplied to the generator I/Q phase 214. In this way the chain tracking frequency in Fig. 14A facilitates digital tracking in a closed circuit at the carrier frequency of the received RF signal. In addition, the digital implementation of the device shown in Fig. 14A provides a programmable parameter FGAINto provide the desired response of the circuit.B. Filter decimation audio
In Fig. 15 presents a block diagram of the preferred alternative implementation of the de filter is the frequency of the demodulator I/Q phase signal with a lower data rate. In this embodiment, 8-bit data with a speed of 40 quib./with that generated by the FM demodulator of the signal converted by the filter 102 in the 12-bit data at a rate of 12 quib./C.The implementation of the filter, as shown in Fig. 15, based on the set of SINC filters (i.e. filters that are characteristic of the species sinc (x) = sin(x)/x) to ensure effective implementation of the hardware. In particular, the filter 102 has input SINC filter 412 with three taps, a cascade connected with SINC3filter 416 with two taps. The filter output signal 416 sub-sampled using a switch 418, for example, with a frequency of 20 quib./C. the Filter 102 is typically configured to provide attenuation of at least 40 dB in the frequency range from 16 to 20 kHz. This degree of attenuation can be achieved through the implementation of the SINC filter in accordance with the following conversion functions in the z-region:
SINC filter Transfer function
3-taking SINC filter (412) - (1+z-1+z-2)/4
2-taking SINC3filter (416) - (1+z-1)(1+z-1)(1+z-1)/8
C. Synchronization of the broadband signal and data recovery
In Fig. 16 presents the variant of implementation of the restored block the establishment of synchronization and decoding of the data stream, encoded using the Manchester code, adopted dual mode receiver 16. The block 104 includes a filter 430 receiver, which approximates a consistent filter for a stream of characters Manchester code. In addition, the filter 430 receiver limits the band of the demodulated FM signal and rejective high-frequency noise generated in the generator 218 phase conversion in frequency. In a possible embodiment, the filter 430 receiver is designed to emulate the analog low-pass filter, Butterworth fourth order with a cutoff frequency approximately equal to 13 kHz. If the demodulated FM signal is generated by the demodulator I/Q phase speeds of 40 quib./with the filter 430 receiver may be implemented as a 2-taking SINC filter (zero speed transmission 20 quib./(C) having a transfer function z-transform of the form (1+z-1)/2.As shown in Fig. 16, the interpolation filter 432 is provided to increase the sampling rate of the filtered signal generated by the filter 430 receiver, to achieve resolution of samples corresponding to the processing performed by the units of recovery synchronization and decoding of data encoded by the h contains a storage scheme zero-order 436, designed to receive a stream of samples at a speed of 40 quib./with filter 430 receiver. Switch 438 provides additional sampling of the output signal storage schema zero order 436, for example, with a frequency of 320 quib./to provide the desired resolution in time to restore synchronization and detection of the stream of characters encoded in Manchester code, with a speed of 20 KB/S. the resulting discretized flow with a speed of 320 quib. /s filtered 8-bypass SINC filter 440 with transfer function (1 + z-1 +...+ z-7)/8. The resulting linearly interpolated sequence y(n) generated 8-bypass SINC filter 440 in response to the sequence x(n) generated by the filter 430 may be represented in the following form:
y(8n + k) = x(n), for k=0, and
y(8n + k) = y(8n + k - 1) + (x(n) - x(n-1))/8 for k = 1, ...7.In Fig. 18A shows a variant implementation of the recovery block synchronization and block decoding of the Manchester code 433 and 434. In the present embodiment, the block decoding of the Manchester code 434 is implemented using a digital fasolada chain 1-th order, the synchronization of which is controlled by the zero crossings 460, formerlythe in the scheme of threshold data 464 for submission of data bits 470, past the threshold processing at the speed of interpolation 320 quib. /s in the scheme of zero-crossings 472. Data bits 470, past the threshold processing, are formed on the basis of the sign of the input sequence of samples. More specifically, each zero crossing 460 is formed in the scheme of zero-crossings 472 by processing the XOR circuit serial data bits 470, past the threshold processing.Digital fasolada circuit block decoding of the Manchester code 434 is designed to provide synchronization with taken for example the speed of transmission of characters Manchester code 20 quib./C. Block decoding 434 contains a phase detector 480 to determine the zero crossing discretized values phase, providing the discretization of the output signal of the drive phase 484 after generating each zero crossing 460. In a preferred embodiment, the phase detector 480 generates a 3-bit error signal, selected from 3 bits of the drive phase, to which is added an offset of 1/2 the least significant bit for forming the unbiased 4-bit estimate of the phase error. Each proyektirovaniya sampling phase generated by the phase detector 480, bitwise SDW> with the control processor of the receiver. The value of this bit shift performed in the scaling register 490, determines the time constant and hence the bandwidth digital fasolada circuit in block 434. Time constants and the values of the bandwidth associated with taken for example set of values of LSHIFTpresented on Fig. 18B.As shown in Fig. 18B, in the preferred embodiment, values of LSHIFTare in the range of from 5 to 8, which corresponds to the range of values of the bandwidth from 80 Hz to 10 Hz.As shown in Fig. 18A, the drive phase 484 updated identical phase increments of, for example, with a frequency of 320 Hz. In this embodiment, each fixed increment phase is chosen equal to 1/8, which results in changing the value of the drive 484 from -1 to +1 for each character Manchester code 16 clock cycles with a frequency of 320 kHz. The drive phase 484 is generally implemented with a cyclic return overflow from +/-1.During the operation of the digital fasolada circuit according to Fig. 18A is synchronized in phase so that the zero crossing 460 input signal coincide with the zero crossings of the output signal of +/-1 nakapag detector 480, however, various factors (for example, the time resolution of the quantization noise signal) ensure continuous operation fasolada circuit, determining a non-zero error diskretisierung phase. As a concrete example, consider the case where the transitions of signal +/-1 from the drive phase 484 are "leading" zero crossings 460 of the input signal. In this case, the resulting positive error signal is subtracted from the next value 1/8 increment phase supplied to the subtraction unit 498, thereby reducing the ahead of phase with the output of the drive phase 484 with respect to the input of zero-crossings 460.In accordance with Fig. 18A, the recovered clock signal 502 Manchester code can be obtained from the sign of the phase error accumulated by the accumulator 484. In the phase synchronization of the positive transitions of the recovered clock signal 502 Manchester code correspond to character transfers the restored data of the Manchester code 504 generated by the register-latch 506. More specifically, the data of the Manchester code 504 are formed by fixing (506) signal 470, past the threshold processing on the trailing edge of the recovered clock signal 502 Manchester code.
FIELD: radio engineering; construction of radio communication, radio navigation, and control systems using broadband signals.
SUBSTANCE: proposed device depends for its operation on comparison of read-out signal with two thresholds, probability of exceeding these thresholds being enhanced during search interval with the result that search is continued. This broadband signal search device has linear part 1, matched filter 2, clock generator 19, channel selection control unit 13, inverter 12, fourth adder 15, two detectors 8, 17, two threshold comparison units 9, 18, NOT gates 16, as well as AND gate 14. Matched filter has pre-filter 3, delay line 4, n attenuators, n phase shifters, and three adders 7, 10, 11.
EFFECT: enhanced noise immunity under structural noise impact.
1 cl, 3 dwg
FIELD: radio engineering for radio communications and radar systems.
SUBSTANCE: proposed automatically tunable band filter has series-connected limiting amplifier 1, tunable band filter 2 in the form of first series-tuned circuit with capacitor whose value varies depending on voltage applied to control input, first buffer amplifier 3, parametric correcting unit 4 in the form of second series-tuned circuit incorporating variable capacitor, second buffer amplifier 5, first differential unit 6, first amplitude detector 7, first integrating device 9, and subtraction unit 9. Inverting input of subtraction unit 9 is connected to reference-voltage generator 10 and output, to control input of variable capacitors 2 and 4. Automatically tunable band filter also has series-connected second amplitude detector 11, second integrating unit 12, and threshold unit 13. Synchronous operation of this filter during reception and processing of finite-length radio pulses is ensured by synchronizer 14 whose output is connected to units 10, 8, and 12. This automatically tunable band filter also has second differential unit whose input is connected to output of buffer amplifier 3 and output, to second control input of variable capacitor of band filter 2.
EFFECT: enhanced noise immunity due to maintaining device characteristics within wide frequency range.
1 cl, 1 dwg
FIELD: radio communications engineering; mobile ground- and satellite-based communication systems.
SUBSTANCE: proposed modulator that incorporates provision for operation in single-channel mode with selected frequency modulation index m = 0.5 or m = 1.5, or in dual-channel mode at minimal frequency shift and without open-phase fault has phase-shifting voltage analyzer 1, continuous periodic signal train and clock train shaping unit 2, control voltage shaping unit 3 for switch unit 3, switch unit 3, switch unit 4, two amplitude-phase modulators 5, 6, phase shifter 7, carrier oscillator 8, and adder 9.
EFFECT: enlarged functional capabilities.
1 cl, 15 dwg
FIELD: electronic engineering.
SUBSTANCE: device has data processing circuit, transmitter, commutation unit, endec, receiver, computation unit, and control unit.
EFFECT: high reliability in transmitting data via radio channel.
FIELD: electronic engineering.
SUBSTANCE: method involves building unipolar pulses on each current modulating continuous information signal reading of or on each pulse or some continuous pulse sequence of modulating continuous information code group. The number of pulses, their duration, amplitude and time relations are selected from permissible approximation error of given spectral value and formed sequence parameters are modulated.
EFFECT: reduced inetrsymbol interference; high data transmission speed.
16 cl, 8 dwg
FIELD: communication system transceivers.
SUBSTANCE: transceiver 80 has digital circuit 86 for converting modulating signals into intermediate-frequency ones. Signal source 114 transmits first periodic reference signal 112 at first frequency. Direct digital synthesizer 84 receives second periodic signal 102 at second frequency from first periodic reference signal. Converter circuit affording frequency increase in digital form functions to convert and raise frequency of modulating signals into intermediate-frequency digital signals using second periodic signal 102. Digital-to-analog converter 82 converts intermediate-frequency digital signals into intermediate-frequency analog signals using first periodic reference signal 112.
EFFECT: reduced power requirement at low noise characteristics.
45 cl, 3 dwg
FIELD: radio engineering; portable composite phase-keyed signal receivers.
SUBSTANCE: proposed receiver has multiplier 4, band filter 6, demodulator 8, weighting coefficient unit 5, adding unit 7, analyzing and control unit 10, synchronizing unit 3, n pseudorandom sequence generators 21 through 2n, decoder 1, and switch unit 9. Receiver also has narrow-band noise suppression unit made in the form of transversal filter. Novelty is that this unit is transferred to correlator reference signal channel, reference signal being stationary periodic signal acting in absence of noise and having unmodulated harmonic components that can be rejected by filters of simpler design than those used for rejecting frequency band of input signal and noise mixture. Group of synchronized pseudorandom sequence generators used instead of delay line does not need in-service tuning.
EFFECT: facilitated realization of narrow-band noise suppression unit; simplified design of rejection filters.
1 cl, 8 dwg