Encryption/decryption of messages hashiriya function and the device for its realization

 

(57) Abstract:

The invention relates to telecommunications, and in particular to the technique of secret confidential communication. Encryption/decryption of messages hashiriya function involves the preliminary formation of the error correcting blocks cryptogram, hashing, comparison with the information block q-ary symbols, the choice among them is closest and the transmission of the message recipient, error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, hashing the received identified error correcting unit cryptogram. Device encryption/decryption of messages hashiriya function on the sending node added selection block, the memory module error correcting blocks of cryptograms, the switch, and at the receiving node, the identification block, the memory module error correcting blocks of cryptograms and key. The technical result achieved in their implementation, is support for improving the reliability of transmission of encrypted messages over channels with interference due to the detection of transmission errors and re-send encrypted messages with the Osh plan and relate to the field of telecommunications, namely, the technique of confidential communication, for encrypted transmission of redundant messages, such as converted to digital mind speech, audio, TV, Fax, etc. messages.

The proposed method and device for encryption/decryption of messages hashiriya function can be used to prevent unauthorized access by third parties to messages transmitted by the sender to the message receiver via digital communication channels, while enhancing the reliability of transmission in terms of the impact of transmission errors. The term "encryption" understand the message conversion using a known sender and receiver of the message secret key for transfer and inverse transform on the reception, eliminating or significantly impede unauthorized access to transmitted messages of third parties who do not know the secret key. The term "cryptogram" understand that is transmitted over the communication channel encrypted message.

Known methods of encryption/decryption of messages is described, for example, in the book: J. Messi "Introduction to modern cryptologia". TIER, 1988,, 76, No. 5, page 34. They zakluchautsya the next element of a sequence of messages with another element of the encrypting sequence, the transmission of the message recipient, the encrypted sequence, the formation of the message recipient decrypting the sequence of the secret key and the decryption sequence of messages elementwise subtraction from the next element of the encrypted sequence of the corresponding element of the encryption sequence. A disadvantage of the known methods of encryption/decryption of messages is low reliability of the transmission of encrypted messages over channels with interference caused by the inability of detecting transmission errors. By referring to the received encrypted message is impossible to determine distorted if it is a transmission error, as in the known methods of encryption/decryption of messages can be generated encrypted message can be of any form.

The known device encryption/decryption of messages is described, for example, in the book: U. Diffie, M. Hellman "Security and infotouriste". TIER, 1979,, 67, N3, page 55. The device includes a transmitting and receiving nodes. The transmitting node consists of a superposition encoding sequence, the memory block of the secret key, the processing block and counter. Encrypting the sequence at the output b block overlay encrypting sequence is carried out element-by-element summation of a sequence of messages with encryption sequence. The encrypted message is transmitted over the channel. In the receiving node, consisting of a subtraction unit which encrypts the sequence of memory block private key conversion unit and the counter, synchronously is formed by encrypting a sequence that is identical to the encryption sequence generated in the transmitting node. Decryption of a message is performed in the subtraction unit which encrypts the sequence element-by-element subtraction of the received encrypted message sequence encoding sequences. A disadvantage of the known device encryption/decryption of messages is low reliability of the transmission of encrypted messages over channels with interference caused by the inability of detecting transmission errors. By referring to the received encrypted message is impossible to determine distorted if it is a transmission error, as in known devices, encryption/decryption of messages can be generated encrypted message can be of any form.

The closest in technical essence to the claimed method of encryption/decryption of messages hashiriya function is the method described in U.S. patent 5483598 IPC6H 04 L 9/20 from 9.01.96. Way-punkcie hash the secret key and the starting block of binary symbols, the transmission between the sender and the message recipient secret key and the starting block of binary symbols, splitting messages into information blocks of binary symbols, the hash with the sender of the message start of block of binary characters of the hash function and a secret key, encrypting the first information block of binary symbols by adding it with the hashed starting block of binary symbols, the transmission of the message recipient, the cryptogram block of binary symbols, hashing popechitelem messages starting block of binary characters of the hash function and a secret key, the decryption of the received cryptogram block by subtracting from it hashed the starting block of binary symbols and recovery thus the first information block of binary symbols. To encrypt the second and subsequent blocks of binary information symbols hairout previous cryptogram block on the hash function and a secret key, and then encrypt the next block of binary symbols by adding another hashed block of binary symbols. The next block of the cryptogram convey the message recipient, which key and then decrypts the next received block cryptogram by subtracting from it the next hashed block of binary symbols, and re-hashing blocks of cryptograms and the subsequent steps to perform until receive regular information blocks of binary symbols.

The disadvantage of the prototype of the claimed method of encryption/decryption of messages hashiriya function is the low reliability of the transmission of encrypted messages on channels with interference caused by the inability of detecting transmission errors. By referring to the received encrypted message is impossible to determine distorted if it is a transmission error, as in the known methods of encryption/decryption of messages hashiriya function can be formed encrypted message can be of any form.

The closest to the technical nature of the claimed device encryption/decryption of messages hashiriya function is the device described in U.S. patent N 548 3598 IPC5H 04 L 9/20 from 9.01.96. The known device is the prototype includes transmitting and receiving nodes. On the sending node, the input module memory information block is an input device. The input data is an eye hashing connected to the output of the switching unit, the first information input of the switching unit is connected to the output of the memory module starting unit, the second information input of the switching unit is connected to the output of the memory module of the previous block of the cryptogram. The output of the memory module information unit connected to the first input of the adder modulo 2, the output of block hash is connected to the second input of the modulo 2. The output of the adder modulo 2 is connected to the input of the memory module unit cryptogram and in parallel with the input of the memory module of the previous block of the cryptogram. The output of the memory module unit cryptogram is connected to the input of the communication channel. On receiving the input node of the memory module received cryptogram block connected to the output of the communication channel. Input a secret key block hash is connected to the output of the memory module secret key, the first information input of the block hash is connected to the output of the switching unit, the first information input of the switching unit is connected to the output of the memory module starting unit, the second information input of the switching unit is connected to the output of the memory module of the previous received block cryptogram. The output of the memory module received cryptogram block connected to the first input of the modulo 2 and in parallel with vchodove.

The disadvantage of the prototype of the claimed device encryption/decryption of messages hashiriya function is the low reliability of the transmission of encrypted messages on channels with interference caused by the inability of detecting transmission errors. By referring to the received encrypted message is impossible to determine distorted if it is a transmission error, as in known devices, encryption/decryption of messages hashiriya funkcia can be formed encrypted message can be of any form.

The aim of the invention the claimed technical solution is to develop a method of encryption/decryption of messages hashiriya function and device, its implements, for enhancing the reliability of the transmission of encrypted messages over channels with interference due to the detection of transmission errors and re-send encrypted messages received with an error.

This objective is achieved in that in the known method of encryption/decryption of messages hashiriya function, which consists in the preliminary formation of hash functions, secret key, and the starting block of binary symbols, the transmission between the sender and the recipient of saabsaab, the hashing of the message sender blocks of binary symbols, the transmission of the message recipient blocks of binary symbols and hashing the received blocks of binary symbols, optionally pre-form N error correcting blocks of cryptograms, where N>2. The formation of the N error correcting blocks of cryptograms performed by multiplying each of the N blocks of binary symbols to generate a matrix of binary error-correcting code. Hairout error correcting blocks of cryptograms on hash functions, secret key, and the starting block of binary symbols, compare each i-th, where i= 1, 2,...,N, hashed robust cryptogram block with the first block of information of q-ary symbols, where q>2. Among N hashed error correcting blocks of cryptograms choose the most close to the first information block q-ary symbols. For comparison, each of the i-th, where i = 1, 2, . . . ,N, hash error correcting unit cryptogram with the first block of information of q-ary symbols from the value of each q-ary counting the i-th hash error correcting unit cryptogram subtract the corresponding value of the q-ary counting the first data block q-ary symbols, for each i-th kashirovannoy hashed robust unit cryptogram to the first information block q-ary symbols choose the appropriate minimum amount of the obtained differences. Robust unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, transmit a direct communication channel to the receiver of the message, identify the accepted error correcting unit cryptogram with N error correcting blocks of cryptograms, and if they are not identified, wash adopted by the error correcting unit cryptogram and a reverse communication channel transmit a control signal for re-transmission of the message recipient, error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram. Adopted by the identified error correcting unit cryptogram hairout on hash functions, secret key, and the starting block of binary symbols. Re hairout N error correcting blocks of cryptograms on hash functions, secret key, and error correcting unit cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram, compare each i-th, where i=1,2,..,N, hashed robust cryptogram block with the next block of information of q-ary symbols, among N hashed error correcting blocks of cryptograms choose the most Blimber what about the error correcting unit cryptogram with the next information block q-ary symbols from the value of each q-ary counting the i-th hash error correcting unit cryptogram subtract the corresponding value of the q-ary counting the next information block q-ary symbols, for each i-th hash error correcting unit cryptogram absolute value of the obtained difference summarize, and closest to the hashed robust unit cryptogram to the next information block q-ary symbols choose the appropriate minimum amount of the obtained differences. Transmit a direct communication channel to the receiver of the message error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram. Identify adopted by the error correcting unit cryptogram with N error correcting blocks of cryptograms, and if they are not identified, wash adopted by the error correcting unit cryptogram and a reverse communication channel transmit a control signal for re-transmission of the message recipient, error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram. Hairout adopted identified robust cryptogram block on the hash functions, secret key, and the previous adopted identified by the error correcting unit cryptogram. Re-hashing of error-correcting blocks of cryptograms and the subsequent actions performed is the population of actions performed by transmission across a communication channel pre-formed error correcting blocks of cryptograms can improve the reliability of transmission by detecting transmission errors and re-send encrypted messages, received with an error, without introducing additional redundancy in the transmitted encrypted message.

This objective is achieved in that in the known device, the encryption/decryption of messages hashiriya fiction, containing on the sending node memory information block, the entrance of which is the input of the block hash, input a secret key which is connected to the output of the memory module secret key. The first input of the block hash is connected to the output of the switching unit, the first information input of the switching unit is connected to the output of the memory module starting unit, the second information input of the switching unit is connected to the output of the memory module of the previous cryptogram block, the memory block of the cryptogram, the information output of which is connected to the input of the direct communication channel. At the receiving node, the memory module received cryptogram block, whose input is connected to the output of the direct communication channel, the block hash, input a secret key which is connected to the output of the memory module secret key. The first information input of the block hash is connected to the output of the switching unit, the first information input of the switching unit is connected to the output of the previous module the received cryptogram block. On the sending node is added to the block selection information input connected to the memory module information unit, the second information input unit selection is connected to the output of the block hash, the output of block selection is connected to the information input of the memory module error correcting blocks of cryptograms, the output of which is connected with the information input switch, a first output switch connected to the second information input of the hash, the second information output switch connected to an information input of the memory module unit cryptogram and parallel to the input of the memory module of the previous block of the cryptogram. The first control input of the memory module unit cryptogram is connected to the output of the reverse channel. At the receiving node further introduced the identification block, the first information input connected to the output of the memory module received cryptogram block, the second information input of the identification block is connected to the output of the memory module error correcting blocks of cryptograms, the first control output of the identification block is connected with the control input of the memory module error correcting blocks of cryptograms, the second upravlyayuchi connected to the input of the reverse link and in parallel with the input erase the memory module of the received cryptogram block, information input key is connected to the output of the memory module received cryptogram block, the information output of the key is connected to a second information input unit hashing and parallel to the input of the memory module preceding the received cryptogram block, the output block hash is the output device, and memory information block, the block selection block hashing, memory module secret key, the switching unit, the memory module starting block, the memory block of the cryptogram, memory of the previous block of the cryptogram, memory module error correcting blocks of cryptograms, the memory block of the cryptogram, the switch on the sending node, the memory module received cryptogram block, the identification block, the switching unit, the memory module secret key, the block hash, switching unit, a memory module of the previous received block cryptogram, memory module starting block at the receiving node is equipped with control inputs that receive the control signals generated by control unit forming part of the claimed device. Conducted by the applicant's analysis of the level of technology has allowed to establish that the analogues, characterized by sets of attributes, t is a function, no. Therefore, each of the claimed invention meets the condition of patentability "novelty."

Search results known solutions in this and related areas of technology in order to identify characteristics that match the distinctive features of prototypes signs of each of the claimed invention, have shown that they do not follow explicitly from the prior art. Of certain of applicant's prior art there have been no known impact provided the essential features of each of the claimed inventions to the achievement of the technical result. Therefore, each of the claimed invention meets the condition of patentability "inventive step".

The stated objects of the invention are illustrated by the drawings, in which:

- Fig. 1 is a structural diagram of a device encryption/decryption of messages hashiriya function;

- Fig. 2 is a waveform illustrating the essence of the proposed method of encryption/decryption of messages hashiriya function;

- Fig. 3 is a block diagram of the block hashing 3;

- Fig. 4 is a block diagram of the switching unit 3.7;

- Fig. 5 is a block diagram of the identification block 12;

- Fig. 6 - SEMA block 2;

- Fig. 9 is a block diagram of the computing unit modulo 3.5;

- Fig. 10 is a block diagram of a memory module error correcting blocks of cryptograms 10;

- Fig. 11 is graphs showing the effect of the claimed method;

- Fig. 12 is a timing chart explaining the essence of the proposed device encryption/decryption of messages hashiriya function;

- Fig. 13 is a timing chart explaining the essence of the operation unit 3 of the proposed hashing device encryption/decryption of messages hashiriya function.

The implementation of the inventive method consists in the following. To improve the reliability of the transmission of encrypted messages via communication channels with interference using their error-correction coding of redundant code, which allows to detect transmission errors in received messages. However, this requires a transmission channel of the additional redundant information generated from the encrypted message according to the encoding rule error-correcting code, which requires an increase in bandwidth of the communication channel. On the other hand, encrypted transmission via discrete channels of redundant messages, such as voice, audio, television facsimile the methods of analog-to-digital conversion does not ensure complete removal of the redundancy of the above signals, therefore, digital voice, audio, TV, Fax and similar messages have significant residual redundancy, as described, for example, in the book "Compression and retrieval of information ". - M.: Radio and communication, 1988, page 77. Kind of digital voice, audio, TV, Fax and similar messages, discretized with sampling frequency F = 1/T and is quantized to q levels (q>2) is shown in Fig. 2(b).

However, the known methods of encryption/decryption of messages does not take into account the presence of this message redundancy and encryption process form basicbuttonui cryptogram. By the form adopted from the communication channel of the cryptogram is impossible to determine distorted if it is a transmission error. So for redundant transmission of encrypted messages via communication channels with errors significant advantages of using the noise-tolerant cryptograms, without providing additional redundancy detection of the fact of their distortion during transmission.

The inventive method for providing encryption/decryption of messages hashiriya function with error detection transmission and re-transmission of encrypted messages received with an error, which will increase the reliability of incli hash the secret key and the starting block of binary symbols is the following. As hash functions use the hash conversion unit of binary symbols in the hashed block q-ary symbols satisfying the following requirements.

1) Each q-ary symbol hash of the block depends on each binary symbol hash block, each binary symbol of the secret key, and each binary symbol of the starting vector, i.e. a change in any binary symbol hash unit, a secret key or the start of a block causes a change in the multiple q-ary symbols hashed block.

2) Knowing full description fiction hash value of the starting block of binary symbols and arbitrarily large number of values hashirama blocks and the corresponding values of hashed blocks, third parties (the enemy) is not able to calculate used in the process of hashing the secret key.

3) Knowing full description of the hash function and the value of the starting block of binary symbols, a third party is not able to generate the hashed block for an arbitrary hash block, without knowing the secret key.

Known methods will prefix the I data: Past and future". TIER, 1988,, 76, No. 5, page 49. They consist in the formation of the hash function with a secret key, using the encryption algorithm DES in feedback mode to text mode or output feedback. However, these methods prior to the formation of hash functions are designed for hashing blocks of binary characters only 64 bits, which significantly narrows the scope of their use. In addition, known methods of forming the hash functions generate hashed blocks of binary characters instead of q-ary symbols that is required in the invention. So for hashing blocks of binary characters of arbitrary length with the formation of hashed blocks of q-ary symbols is proposed hashing function has the following form. Randomly choose an algebraic Galois field GF(p), consisting of p elements. In the selected Galois field find one of the primitive elements and can result in random order all the values of the elements of this field, if you consistently build it in whole, positive degree from 1 to R-1, computing the result modulo p;

a1(mod p)= a and2(mod p), and3(mod p), andi(mod p),.., ap-1mod p),

where ai
ei,k+ e*j-1,k< / BR>
yi,j,k=(a(modp))(mod q), i= 1,2,...,N, j= 1,2.....,

where yi,j,k- the k-th q-ary symbol hash error correcting unit cryptogram Yi,jobtained by hashing the i-th image block of the cryptogram Eiencryption of the j-th information block Mjq-ary symbols ( i=1,2,...,N, j= 1,2,..., k=1,2,..,n);

ei,k- the k-th binary symbol previously selected i-th image block of the cryptogram Ei(i= 1,2,.,..,N);

e*j-1,k- the k-th binary symbol error correcting unit cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram:

q is a Prime number, q<

To encrypt/decrypt the first data block of M1q-ary characters as the value of error-correcting block cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram, use the value of the starting block of binary symbols E0,

E*j-1= E0if j = 1

The computation of the exponentiation modulo phanie from 0 to q-1 with the same probability 1/q, as evidenced in the book: D. Knuth "the Art of computer programming on the computer". - M.: Mir, 1978, T. 3, page 604.

Select secret key perform random selection of one of the primitive elements selected Galois fields GF(p). The number of primitive elements of the field is estimated by the value of the Euler function from values of the Euler function and if p > 1020is computing neverborne for third parties (of the enemy) the number of possible values of the secret key. The way of finding a primitive element of Galois field are described, for example, in the book: THEY are. Vinogradov "fundamentals of theory of numbers". - M.: Nauka, Main editorial Board for physical and mathematical literature, 1981, page 89.

Select the starting block of the binary symbols is carried out by randomly selecting a block of binary symbols described, for example, in the book: D. Knuth "the Art of computer programming on the computer". - M.: Mir, 1977, so 2, page 22. View of the start block of the binary symbols is shown in Fig. 2(d).

The transmission between the sender and the message recipient secret key and the starting block of binary symbols is carried out until the start of transmission by the sender of the message encrypted messages. The value of the secret key must be unknown to third persons (FR who eat the necessary precautions. Known methods of transmission between the sender and the message recipient secret key and blocks of binary symbols are described, for example, in the book: J. Messi "Introduction to modern cryptologia". TIER, 1988,, 76, No. 5, page 24.

If the message length exceeds the length of the information block q-ary symbols, the message is divided into sequentially transmitted information blocks of the q-ary characters fixed length n. Known methods of breaking the message into successively transmitted information blocks q-ionyl characters fixed length is described, for example, in the book: C. I. Vasiliev, A. P. the Burkin, C. A. Sviridenko "communication Systems". - M.: Vysshaya SHKOLA, 1987, page 208.

The preliminary formation of the N error correcting blocks of cryptograms is the following. Arbitrary binary error-correcting code describes a generating matrix G of dimension r rows and n columns, where n > r. The value of n is the length of the error correcting code blocks, r is the number of information bits in error correcting code blocks. The formation of the N error correcting blocks of cryptograms Eiis performed by multiplying each of the N blocks of binary characters Iithe length of r bits, where i=1,2....,N. the generating matrix G DOI ustoichivyh blocks described, for example, in the book of U. Peterson, E. Weldon "error-correcting Codes". - M.: Mir, 1976, page 252. The number N of pre-generated error correcting blocks of cryptograms chosen depending on the required accuracy of the recovery information blocks q-ary symbols recipient of the message, as shown, for example, in the book: J. Makhoul. C. Rokos, G. Gish "Vector quantization for encoding speech". TIER, 1985,, 73, No. 11, page 23. View N pre-formed error correcting blocks of cryptograms shown in Fig. 2(b).

Hashing error correcting blocks of cryptograms on hash functions, secret key, and the starting block of binary symbols can be performed, for example, using the proposed hash function based on exponentiation in a primitive element of Galois field modulo primes p and g:

ei,k+ e0,k< / BR>
yi,1,k= (a(mod p))(mod q), i= 1,2,...,N, k = 1, 2,...n, q<i,l,k- the k-th q-ary symbol hash error correcting unit cryptogram Yi,1to encrypt the first information block q-ary symbols M1(i= 1,2,..., N, k= 1,2,..,n );

ei,k- the k-th binary symbol error correcting unit cryptogram Ei(i= 1,2...,N);

e0,k

Each i-th, where i=1,..,N, hashed robust unit cryptogram compared with the first block of information of q-ary symbols. Known methods of comparing blocks of q-ary symbols are described, for example, in the book: U. Peterson. E. Weldon "error-correcting Codes"', - M.: Mir, 1976, page 52. For comparison use metric If, in accordance with which to compare each of the i-th hash error correcting unit cryptogram with the first block of information of q-ary symbols from the value of each q-ary counting the i-th hash error correcting unit cryptogram subtract the corresponding value of the q-ary counting the first data block q-ary symbols, and for each i-th hash error correcting unit cryptogram absolute values of the differences are added up.

Among N hashed error correcting blocks of cryptograms choose the most close to the first information block q-ary symbols, corresponding to the minimum sum of the obtained differences. Known methods of selecting the minimum value among several mn is Transmit a direct communication channel to the receiver of the message error correcting unit cryptogram, the corresponding selected kashirovannuyu error correcting unit cryptogram. How binary blocks the communication channel is known and described, for example, and the book: A. G. Zuko, D. D. Klovsky, M. B. Nazarov. L. M. Fink, "theory of signal transmission". - M.: Radio and communication, 1986, page 11.

Adopted by the error correcting unit cryptogram identify with N error correcting blocks of cryptograms. Known authentication methods are described, for example, in the book: U. Peterson, E. Weldon "error-correcting Codes". -M.: Mir, 1976, page 15. To identify the received error correcting unit cryptogram with N error correcting blocks of cryptograms it sequentially compared with each of the N error correcting blocks of cryptograms. If there is not one error correcting block cryptogram, coinciding with the received error correcting unit cryptogram, the accepted error correcting unit cryptogram is considered unidentified.

Adopted unidentified robust cryptogram block erase and reverse channel transmit a control signal for re-transmission of the message recipient, error correcting unit cryptogram corresponding to the selected kashirovannuyu of pomeroyton book:, Peterson, E. Weldon "error-correcting Codes". -M.: Mir, 1976, page 17. Known methods of transmission via a reverse communication channel sending signals for re-transmission of the message recipient, error correcting block are described, for example, in the book: U. Peterson, E. Wheddon "error-correcting Codes", -M.: Mir, 1976, page 17,

Adopted by the identified error correcting block hairout on hash functions, secret key, and the starting block of binary symbols by the way, is identical to the hash of the message sender error correcting blocks of cryptograms on hash functions, secret key, and the starting block of binary symbols, using the proposed hash function based on exponentiation in a primitive element of Galois field modulo primes p and g:

e'1,k+ e0,k< / BR>
m^1,k=(a(modp))(modq), k = 1, 2,...,n, g<1,k
- the k-th q-ary symbol of the first recovered information block M^1q-ary symbols;

e1,k' - k-th binary symbol first accepted the identified error correcting unit cryptogram E1';

e0,k- the k-th binary symbol of the start block of binary symbols E0.

In the restore on pickup is on and the subsequent information blocks q-ary symbols again hairout N error correcting blocks of cryptograms on hash functions, the secret key and the error correcting unit cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram using the proposed hash function based on exponentiation in a primitive element of Galois field modulo primes p and g:

ei,k+ e*j-1,k< / BR>
yi,j,k= (a(mod p))(mod q), i=1,2,...,N, j=1,2,..., k=1,2,..., n, q<i,j,k- the k-th q-ary symbol hash error correcting unit cryptogram Yi,jto encrypt the j-th information block q-ary symbols (i= 1,2,...,N, j= 1,2,..., k= 1,2,...,n);

ei,k- the k-th binary symbol error correcting unit cryptogram Ei(i= 1,2,...,N);

e*j-1,k- the k-th binary symbol error correcting unit cryptogram E*j-1you selected in the previous step kashirovannuyu error correcting unit cryptogram Y*j-1.

Each i-th, where i=1,2,...,N, hashed robust unit cryptogram is compared with the next information block q-ary symbols. Known methods of comparing blocks of q-ary symbols are described, for example, in the book: U. Peterson, E. Weldon "error-correcting Codes'". - M.: Mir, 1976, page 52. For comparison I use is ogramme with the next information block q-ary symbols from the value of each q-ary counting the i-th hash error correcting unit cryptogram subtract the corresponding value of the q-ary counting the next information block q-ary symbols, and for each i-th hash error correcting unit cryptogram absolute value of a member of the differences are added up.

Among N hashed error correcting blocks of cryptograms choose the most close to another information block q-ary symbols, corresponding to the minimum sum of differences. Known methods of selecting the minimum value among multiple values are described, for example, in the book: D. Knuth "the Art of computer programming on the computer". - M.: Mir, 1978, T. 3, page 219.

A direct communication channel to transmit the message recipient, robust unit cryptogram corresponding to the selected hashes rowanna error correcting unit cryptogram. How to transfer binary block over the communication channel are known and described, for example, in the book by A. G. Zuko, D. D. Klovsky M. B. Nazarov, L. M. Fink, "theory of signal transmission". - M.: Radio and communication, 1986, page 11.

Adopted by the error correcting unit cryptogram identify with N error correcting blocks of cryptograms. Known authentication methods are described, for example, in the book: U. Peterson, E. Weldon "error-correcting Codes". -M.: Mir, 1976, page 15. To identify the received error correcting unit cryptogram with N error correcting blocks of cryptograms it sequentially compared with each of the N error correcting blocks of cryptograms. If not nagetsy, the adopted error-correcting block cryptogram is considered unidentified.

Adopted unidentified robust cryptogram block erase and reverse communication channel to transmit the control signal re-transmission of the message recipient, error correcting unit cryptogram associated with the selected kashirovannuyu error correcting unit cryptogram. There are ways to erase the received error correcting blocks are described, for example, in the book: U. Peterson. E. Weldon "error-correcting Codes". -M.: Mir, 1976, page 17. Known methods of transmission on the reverse channel control signals for re-transmission of the message recipient, error correcting block are described, for example, in the book; U. Peterson, E. Waldon "error-correcting Codes". -M.: Mir. 1976, page 17.

Adopted by the identified error correcting unit cryptogram hairout on hash functions, secret key, and the previous adopted identified by the error correcting unit cryptogram by the way, is identical to the hash of the message sender error correcting blocks of cryptograms on hash functions, secret key, and error correcting unit cryptogram that is matched to the hash-based exponentiation primitive element of Galois field modulo primes p and g:

e'j,k+ e'j-1,k< / BR>
m^j,k= (a(mod p))(mod q), k = 1,2...,n, q<j,k- the k-th q-ary symbol j-ro restored information block M^jq-ary symbols;

e'j,k- the k-th binary symbol j-ro received identified error correcting unit cryptogram E'j;

e'j-1,k- the k-th binary symbol previous adopted identified by the error correcting unit cryptogram E'j-1.

As a result of this restored at the receiving side the approximation of the next information block q-ary symbols.

Transfer the direct channel to the recipient of the message error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, and transfer via a reverse communication channel control signal for re-transmission of the message recipient, error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, synchronized. The synchronization methods described, for example, in the book by E. M., Martynov, "Synchronization in systems of transmission of discrete messages. -M.: Communication, 1972, page 186.

In an analytical form valuable / private data>), k=1,2,...,n,

E0=(ea 0.1eof 0.2,...,e0,k,...,e0,n), k=1,2,...,n,

Ei=(ei,1ei,2,...,ei,k,...,ei,n), k=1,2,...,n,

Yi,j=(Yi,j,1, Yi,j,2,...,Yi,j,k,...,Yi,j,n), k=1,2,...,n,

E*j= (e*j,1e*j,2,...,e*j,k,...,e*j,n), k=1,2,...,n,

E*j-1=(e*j-1,1e*j-1,2,...,e*j-1,k,...,e*j-1,n), k=1,2,...,n,

E^j=(e^j,1e^j,2,...,e^j,k,...,e^j,n), k=1,2,...,n,

E'j=(e'j,1e'j,2,...,e'j,k,...,e'j,n), k=1,2,...,n,

E'j-1=(e'j-1,1e'j-1,2,...,e'j-1,k,...,e'j-1,n), k=1,2,...,n,

M^j=(m^j,1m^j,2,...,m^j,k,...,m^j,n), k=1,2,...,n,

ei,k+ e*j-1,k< / BR>
Yi,j,k= (a(mod p))(mod q), i=1,2,...,N, j=1,2,..., k=1,2,..n, q<*
j-1,k= e0,kif j=1,

< / BR>
e'j,k+ e'j-1,k< / BR>
m^j,k= (a(mod p))(mod q), j=1,2,..., k=1,2,..,n, q<j-1,k= e0,kif j=1,

where Yi,j- the i-th hashed robust unit cryptogram to encrypt the j-th information block Mjq-ary symbols consisting of n q-ary symbols yi,j,k;;

Y*j- selected kheshirovaniye of n q-ary symbols y*j,k;

E0- the starting block of binary symbols, consisting of n binary symbols e0,k;

Ei- the first error correcting unit cryptogram consisting of n binary symbols ei,k;

E*j- robust unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram consisting of n binary symbols e*j,k;

E*j-1- robust unit cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram consisting of n binary symbols e*j-1,k;

E^j- the j-th adopted by the error correcting unit cryptogram consisting of n binary symbols e^j,k;

E'j- j adopted identified robust unit cryptogram consisting of n binary symbols e'j,k;

E'j-1- previous adopted identified robust unit cryptogram consisting of n binary e'j-1,k;

M^j- j recovered information block q-ary symbols consisting of n q-ary symbols m^j,k.

Verification of theoretical assumptions of the claimed method of encryption/decryption submembrane/decryption redundant messages, transmitted over the communication channel with interference, were obtained the results presented in graph form in Fig. 11. In Fig. 11 shows the dependence of the signal-to-noise ratio Aothe decoded redundant signal from the error probability p in a binary symmetric channel without memory. Figure 1) is constructed for the case of use of the claimed method of encryption/decryption of messages hashiriya function, and graph 2) - for the case of using the prototype method. Signal-to-noise ratio Aothe decoded redundant signal was determined by the formula:

< / BR>
where mj,k- the k-th q-ary symbol of the j-th information block Mjq-ary symbols;

m^j,k- the k-th q-ary symbol of the j-th recovered information block M^jq-ary symbols;

Q - number of encrypted information blocks of the q-ary signals.

As a redundant signal was used speech signal is quantized using 8-bit codec (pulse-code modulation and having 253 different values of the amplitude (q=253).

Experimental studies confirm that the use of the proposed method of encryption/decryption of messages hashiriya function is provided by which the position of the transmission errors and re-encrypted transmission of redundant messages, taken with an error.

Device encryption/decryption of messages hashiriya function shown in Fig. 2, consists of transmitting and receiving nodes. The transmitting node includes a memory module information block 1, block 2, block hashing 3, the memory module secret key 4, the switching unit 5, a memory module of the starting unit 6, the memory module unit cryptogram 7, the memory of the previous cryptogram block 8, the switch 9 and the memory module error correcting blocks of cryptograms 10. The receiving node includes a memory module received cryptogram block 11, the identification block 12, a memory module error correcting blocks of cryptograms 13, the key 14, the memory module secret key 15, the block hash 16, the switching unit 17, a memory module of the previous received cryptogram block 18 and the memory module starting block 19. The input module memory information block 1 is the input device. The output of the memory module information unit 1 is connected with the first information input unit 2, the output of which is connected to the information input of the memory module error correcting blocks of cryptograms 10. The second information input unit 2 is connected to the output of the block hashing 3. Input a secret key block x is replaced with the output of the switching unit 5, the first information input connected to the output of the memory module of the starting unit 6, the second information input of the switching unit 5 is connected to the output of the memory module of the previous cryptogram block 8. The first output switch 9 is connected to the second information input of the hash, the second output switch connected to the input of the memory module selected cryptogram block 7 and in parallel with the input of the memory module of the previous selected cryptogram block 8, the input switch 9 is connected to the output of the memory module error correcting blocks of cryptograms 10. The output of the memory module error correcting unit cryptogram 7 is connected to the input of the direct communication channel, and the first control input of the memory module error correcting unit cryptogram 7 is connected to the output of the reverse channel. The output of the direct communication channel connected to the input of the memory module received cryptogram block 11, the first output of which is connected to the first input of the identification block of the received cryptogram block with error correcting blocks of cryptograms 12, the output of which is connected to the information input key 14. The second input of the identification block 12 is connected to the output of the memory module error correcting blocks of cryptograms 13. First opravlyaushi the control output connected with the control input of the key 14 and in parallel with the input of the reverse channel. Exit key 14 is connected to a second information input unit hashing 16 and in parallel with the input of the memory block of the previous received cryptogram block 18. Input a secret key block hashing 16 is connected to the output of the memory module secret key 15, the first information input unit hashing 16 is connected to the output of the switching unit 17, the first input of which is connected to the output of the memory module preceding the received cryptogram block 18, and the second to the output of the memory module starting block 19. The output of block hash is the output device.

Memory module information block 1, block 2, block hashing 3, the memory module secret key 4, the switching unit 5, a memory module of the starting unit 6, the memory module selected cryptogram block 7, the memory module previous selected cryptogram block 8, a switch 9, a memory module received cryptogram block 11, the identification block 12, a switching unit 14, a memory module secret key 15, the block hash 16, the switching unit 17, a memory module of the previous received cryptogram block 18, the memory module starting unit 19 is supplied with inputs control signals generated by the control unit, not shown on the drawings.

The module is of length n symbols, write the value first, and then the next information block q-ary symbols, store and read the first information input unit 2 for comparison with the value of each i-th, where i=1,2,..., N. hashed error-correcting cryptogram. As the memory module information unit 1 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other "Circuits and their applications: a reference guide". - M.: Radio and communication, 1983, page 175, Fig. 5.12. Memory module information unit 1 can be implemented, for example, on the memory chip TO RU (see C. I. Korneichuk, B. N. Tarasenko "Computing devices on chips: a Handbook."-K.: Engineering, 1988, pp. 85-87).

Unit 2 shown in Fig. 8, is designed to compare the value of each i-th, where i=1,2,..,N, hash error correcting unit cryptogram with value first, and then the next information block q-ary symbols, and to select among N hashed error correcting blocks cryptogram is closest to the first, and then the next information block q-ary symbols. Unit 2 consists of s 2.5) and multiplexer 2.6.

The first input vicites 2.1 is the second information input unit 2. The second entrance (the entrance) myCitadel 2.1 is the first information input unit 2. The output of vicites 2.1 connected to the first input (input A) adder 2.2. The output of the adder 2.2 is connected in parallel with the information input of the control switch 2.3 and its second input (the input). On the control input of the controlled switch 2,3 signals control output of the control unit, not shown in the drawings. The control input of the controlled switch 2.3 is the first Manager of the input unit 2. Information output controlled switch 2.3 in parallel connected with the second input (input) of the comparator 2.4 and the first information input (input X) multiplexer 2.6. On the second information input (input Y) multiplexer 2.6 constantly being fed information signals to a single value "1". On the control input (S) of the multiplexer 2.6 serves the control signals from the output of the control unit, not shown in the drawings. The control input of multiplexer 2.6 is a control input unit 2, the Output of multiplexer 2,6 connected with the information input (input X) of the register storing the minimum when vtorogo connected with the control input (entrance W) of the register storing the minimum amount of 2.5, and is the output of the block selection 2.

MyCitadel 2.1 is designed to determine the difference values of the q-ary characters hashed error correcting unit cryptogram and the corresponding q-ary symbols of an information block q-ary symbols. MyCitadel 2.1 represents an adder, working in the subtraction mode. Scheme vicites known, see, for example, in the book: p. P. Maltsev, and other "Digital integrated circuits: a Handbook. -M.: Radio and communication, 1994, page 76, and may be, for example, implemented on the chip CIM (see C. L. awl "Popular digital circuits". - M.: Radio and communication. 1987, pp. 159-161).

The adder 2.2 is designed to sum the values of the differences between the values of q-ary symbols hash error correcting unit cryptogram and the information block q-ary symbols. The adder circuit is known, see, for example, in the book: L. A. Maltsev and other "fundamentals of digital techniques. -M.: Radio and communication, 1986, pp. 53-54, Fig. 51 and can be performed, for example, on the chip CIM (see C. L. awl "Popular digital circuits". - M: communications, 1987, page 156).

Managed switch 2.3, shown in Fig. 7, is designed to ensure that the read value is multiplexor 2.6 when it arrives at the control input of the control switch 2.3 control signals. Physical entities managed switch 2.3 is a two-position controlled switch. Schemes managed switches are known and described, for example, in the book; B. L. Shyla Popular chip CMOS Guide. -M.: Jaguar, 1993, page 22.

The comparator 2.4 is designed to compare the value obtained from the output of the adder 2.2 and a number value stored in the register storing the minimum amount of 2.5. The comparator circuit is known, see, for example, in the book: p. P. Maltsev, and other "Digital integrated circuits: a Handbook. -M.: Radio and communication, 1994, pages 83 and may be implemented, for example, on the chip CSP (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987. p. 183).

The register storing the minimum amount of 2.5 is designed for storing the minimum value of the number of obtained in the adder 2.2. Diagram of the register storing the minimum amount of 2.5-known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other Circuits and their applications: a reference guide. - M. : Radio and communication, 1983, page 134. rice, 4.34. and can be implemented, for example, on the chip TO IR (see owner. Shyla Popular digital circuits". - M.: Radio and communication, 1987, page 120).

The Mulia is. Maltsev and other "fundamentals of digital techniques. -M.: Radio and communication, 1986, page 52, Fig. 48, and may be implemented, for example, on the chip CCP (see, C. L. awl "Popular digital circuits". - M.: Radio and 1987, page 146).

Block hashing 3 shown in Fig. 3, is designed for robust hashing blocks of cryptograms on hash functions, secret key, and the starting block of binary symbols when encrypting the first information block q-ary symbols and for hashing error correcting blocks of cryptograms on hash functions, secret key, and error correcting unit cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram for encryption of the next information block q-ary symbols. Block hashing consists of adder 3.1, registers 3.2, 3.6, 3.12, 3.16, 3.19, vychitala 3.3 and 3.8, Comparators 3.4, 3.11, 3.13, blocks calculate the residue from division 3.5, 3.18, switch, 3.9, block commutation 3.7 and 3.17, multiplier 3.10, 3.14 and 3.15, elements OR 3.20 and 3.21 and inverter 3.22.

The first input of the adder 3.1 is the entrance read the starting block of binary symbols read from the memory module starting block at the encryption of the first and the existing selected in the previous step, Cheshire bathing error correcting unit cryptogram, read from the memory module previously selected block of cryptograms 8 when the encryption of the next information block q-ary symbols (depending on the value of the control signal at the control input of the switching unit 5). The first input of the adder 3.1 is the first information input unit 3 hash. The second input of the adder 3.1 is the input of the read error correcting unit cryptogram read from the memory module error correcting blocks of cryptograms 10 and is the second information input unit 3 hash. The first information input of the switching unit 3.17 is the entrance of the secret key block hashing 3. The output of the adder 3.1 is connected to the first information input of the switching unit 3.3 and parallel to the first comparator input 3.4. To the second input of the comparator 3.4 constantly applied signal level zero ("0"). On the control input of the switching unit 3.3, which is the first managing unit 3 hash, served control signals from the control unit, not shown in the drawings. On the control input of the switching unit 3.17, which is the second managing unit 3 hash, served control signals from the control unit, not shown in the drawing, the fourth control inputs of the block hashing 3, serves the control signals from the control unit, not shown in the drawings. On the control input key 3.14, which is the fifth managing unit 3 hash, served control signals from the control unit, not shown in the drawings. The output of the switching unit 3.3 connected to the input of the register 3.6, the output of which is connected to the first input of vicites 3.8. To the second input of vicites 3.8 constantly applied signal unit level (1). The output of vicites 3.8 connected to the first input of the comparator 3.11 and parallel to the second information input of the switching 3.3 and to the first input of the comparator 3.13. The output of the comparator 3.11 connected to the first input element OR 3.20 and in parallel with the first input element OR 3.21. The output of the comparator 3.13 connected with the second input element OR 3.20 and in parallel with the input of the inverter 3.22. The output of the inverter 3.22 connected to a second input of element 'OR' 3.21. The output element OR 3.20 connected with the control input of the switch 3.9. The output element OR 3.21 connected with the control input of the key 3.15. The output element OR 3.21 connected with the control input of the key 3.15. To the second input of the comparator 3.11 constantly applied signal unit level (1), and to the second input of the comparator 3.13 constantly applied signal level zero (0). The second to the first input of the computing unit modulo 3.18. The second input of the computing unit modulo 3,18 coupled to the output register 3.19, and the output of the computing unit modulo 3.18 - to the input of the register 3.16. The output of register 3.16 connected with the information input key 3.14 and in parallel with the information input key 3.15. Exit key 3.14 connected to the input of the register 3.12. The first input of the multiplier 3.10 coupled to the output key 3.15, the second input - output register 3.12, and the output of multiplier 3.10 connected to the information input switch 3.9. The first output switch 3.9 connected with the second information input of the switching unit 3.7, a control input connected to the output of the comparator 3.4. The first information input of the switching unit 3.7 constantly applied signal unit level ("1"). The first input of the computing unit modulo 3.5 connected to the output of the switching unit 3.7, the second input of the computing unit modulo 3.5 connected to the output of the register 3.2, and the output of the computing unit modulo 3.5 is the output of the block hashing 3.

The adder 3.1 is designed to sum the values of the starting block of binary symbols when encrypting the first information block q-ary symbols or error correcting unit cryptogram corresponding to you the information block q-ary symbols (depending on the value of the control signal, submitted to the control input of the switching unit 5) with the value of error-correcting block cryptogram read from the memory module error correcting blocks of cryptograms 10. The adder circuit is known, see, for example, in the book: L. A. Maltsev and other "fundamentals of digital techniques. -M. : Radio and communication, 1986, pp. 53-54, Fig. 51 and can be performed, for example, on the chip CIM (see C. L. awl '"Popular digital circuits"", - M.: Radio and communication, 1987, page 156).

Case 3.2 is designed to store the value of the Prime number q. Scheme 3.2 register known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other Circuits and their applications: a reference guide. - M.: Radio and communication, 1983, page 134, Fig. 4.34, and can be implemented, for example, on the chip TO IR (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 120).

Switching unit 3.3 is identical to the switching unit 3.7, shown in Fig. 4, and is designed to switch the unit hashing 3 mode read input register 3.6 number value from the output of the adder 3.1 mode read input register 3.6 number value from the output of vicites 3.8.

The comparator 3.4 is designed for a number value received from the output of the adder is an integrated circuit: a Handbook. -M.: Radio and communication. 1994, page 83 and may be implemented, for example, on the chip CSP (see C. L. awl "Popular digital circuits"', - M.: Radio and communication, 1987, page 183).

The computing unit modulo z 5 shown in Fig. 9, is designed for finding the remainder from dividing the value of the dividend number read from the output of the switching unit of 3.7, the value of the Prime number stored in the register 3.2, the evaluation Unit modulo 3.5 consists of a register 3.5.1, myCitadel 3.5.2, 3.5.3 switch, comparator 3.5.4 and 3.5.5 key. The first information input key 3.5.5 is the first input of the computing unit modulo 3.5, the Output key 3.5.5 connected to the input of the register 3.5.1. Control input key 3.5.5 is a control input of the computing unit modulo 3.5. The output of register z 5.1 connected to the first input of vicites 3.5.2. The second input of vicites 3.5.2 parallel with the first input of the comparator 3.5.4 is the second input of the computing unit modulo 3.5. The output of vicites 3.5.2 connected with the second input of the comparator 3.5.4 and in parallel with the information input switch 3.5.3. The comparator output 3.5.4 connected with the control input of the switch 3.5.3. The second output switch 3.5.3 is the output of the computing unit">

Register 3.5.1 is designed to store the value read to the input of the computing unit modulo 3.5 and storage in the future, the value of the intermediate results of a calculation of dividing the number of on the Prime number q. The scheme register 3.5.1 known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other Circuits and their applications: a reference guide. - M.: Radio and communication. 1983, page 134, Fig. 4.34 and can be implemented, for example, on the chip TO IR (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 120).

MyCitadel 3.5.2 designed to determine the difference between the value of the divided number, read through the register 3.5.1, and is a Prime number read from the second input of the computing unit modulo 3.5. MyCitadel 3.5.2. represents an adder, working in the subtraction mode. Scheme vicites known, see, for example, in the book; p. P. Maltsev, and other "Digital integrated circuits; Reference. -M.: Radio and communication, 1994, page 76. It can be implemented, for example, on the chip CIM (see C. L. awl "Popular digital circuits". - M. : Radio and communication. 1987, pp. 159-161).

Switch 3.5.3 shown in Fig. 6, is designed to switch a slave who is a Prime number in the scan mode from the output of the computing unit modulo 3.5 the values of the calculated balance. Switch 3.5.3 contains the first controlled switch 3.5.3.1, the second controlled switch 3.5.3.2 and inverter 3.5.3.3. The information input of the first controlled switch 3.5.3.1 and connected with it in parallel to the information input of the second controlled switch is 3.5.3.2 information input switch 3.5.3. The control input of the second controlled switch 3.5.3.1 connected to the output of the inverter 3.5.3.3. The outputs of the first controlled switch 3.5.3.1 and the second controlled switch 3.5.3.1 are respectively the first and second outputs of the switch 3.5.3. The control input of the first controlled switch 3.5.3.1 and connected with it in parallel to the inverter input 3.5.3.3 are control inputs of the switch 3.5.3.

The first controlled switch 3.5.3.1 is designed to read the value of the intermediate results of a calculation of the remainder from dividing the number by a Prime number q from the output of vicites 3.5.2 on the second information input key 3.5.5. Scheme of the first controlled switch 3.5.3.1 identical to the scheme key 3.14 shown in Fig. 7. The second controlled switch 3.5.3.2 is designed to read the output of the computing unit modulo 3.5 values calculated ostad rednaznachen to provide a control signal, arriving at the control input of the second controlled switch 3.5.3.2. Diagram of the inverter 3.5.3.3 known and described, for example, in the book: C. L. Shyla Popular chip CMOS guide. -M.: Jaguar, 1993. page 22.

The comparator 3.5.4 designed to compare the value of the number read from myCitadel 3.5.2 with the value of the Prime number received from the second input of the computing unit modulo 3.5. The comparator circuit is known, see, for example, in the book: p. P. Maltsev, and other "Digital integrated circuits; Reference. -M.: Radio and communication. 1984, page 83 and can be implemented, for example, on the chip CSP (see C. L. awl "Popular digital circuits". -M.: Radio and communication, 1987, page 183).

Key 3.5.5 is designed to switch the operation of the computing unit modulo 3.5 mode of reading the value of the number read on the input of the computing unit modulo 3.5 mode of reading the value of the intermediate results of the computation modulo a few on the Prime number q to the input of the register 3.5.1. Diagram key 3.5.5 identical to the scheme of the switching unit 3.7, shown in Fig. 4.

Register 3.6 is designed to store the value read from the output of the switching unit 3.3. Scheme Registon allowance. - M.: Radio and communication, 1983, page 134. Fig. 4,34, and can be implemented, for example, on the chip TO IR (see C. L. awl "Popular digital circuits". -M.: Radio and communication, 1987, page 120).

Switching unit 3.7, shown in Fig. 4, is designed to switch the operation unit 3 hash of the reading mode of the intermediate hash values of error-correcting block cryptogram in the mode of reading a single value to the input of the computing unit modulo 3.5. Switching unit 3.7 contains the first controlled switch 3.7.1, the second controlled switch 3.7.2 and inverter 3.7.3. The information inputs of the first controlled switch 3.7.1 and the second controlled switch 3.7.1 are respectively the first and second information inputs of the switching unit 3.7. Connected in parallel information outputs of the first and second controllable switches 3.7.1 and 3.7.2 are the output of the switching unit 3.7. Inverter input 3.7.3 and connected with it in parallel to the control input of the first controlled switch 3.7.1 are managing the input of the switching unit 3.7. The output of the inverter 3.7.3 connected with the control input of the second controlled switch 3.7.2. Schemes managed switches and invert">

MyCitadel 3.8 is designed to subtract from the number value received from the output of the register 3.6, a single value. MyCitadel 3.8 represents an adder, working in the subtraction mode. Scheme vicites known, see, for example, in the book: p. P. Maltsev, and other "Digital integrated circuits: a Handbook. -M.: Radio and communication, 1994, page 76, and may be, for example, implemented on the chip CIM (see C. L., Shyla Popular digital circuits". - M.: Radio and communication, 1987, pp. 159-161).

Switch 3.9 identical to the switch 3.5.3 shown in Fig. 6, and is designed to read an integer value from the output of the multiplier 3.10 to the input of the switching unit 3.7 or to the input of the switching unit 3.17 depending on the values of the output signals of the Comparators 3.11 and 3.13 received at a control input of the switch 3.9.

The multiplier 3.10 is designed to multiply the values of the numbers obtained from the outputs of the register 3.12 and key 3.15, respectively. Diagram of the multiplier 3.10 known, see, for example, in the book: p. P. I. Maltsev other "Digital integrated circuits: a Handbook. -M.: Radio and communication, 1994, page 82 and may be, for example, implemented on the chip CIP (see C. L. awl "Popular digital circuits". -M.: Radio and communication, 1987, with the La 3.8, a single value. The comparator circuit is known, see, for example, in the book: p. P. Maltsev, and other "Digital integrated circuits: a Handbook. -M.: Radio and communication, 1994. pages 83 and may be implemented, for example, on the chip CSP (see C. L. awl "Popular digital circuits". - M.: Radio and communication. 1987, page 183).

Register 3.12 is intended to hold a number value received from the output of the key 3.14. The scheme register 3.12. known and described, for example, in the book: C. A. Batashev, C. N., Veniaminov and other Circuits and their applications: a reference guide. - M.: Radio and communication, 1983, page 134. Fig. 4.34. and can be implemented, for example, on the chip TO IR (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 120).

The comparator 3.13 is intended for comparison of a number value received from the output of vicites 3.8, with a zero value. The comparator circuit is known, see, for example, in the book: p. P. Maltsev, and other "Digital integrated circuits: a Handbook. -M.: Radio and communication, 1994, pages 83 and may be implemented, for example, on the chip CSP (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 183).

Key 3.14 shown in Fig. 7, is designed to control the reading naczelny managed switch. Schemes managed switches are known and described, for example, in the book: C. L. Shyla Popular chip CMOS guide. -M.: Jaguar, 1993, page 22.

Key 3.15 identical key 3.14 shown in Fig. 7, and is designed to control the read value from the output of the register 3.16 at the first input of the multiplier 3.10.

Register 3.16 is intended to hold a number value received from the output of the computing unit modulo 3.18. The scheme register 3.16 known and described, for example, in the book: C. A. Batashev, B. N. Veniaminov and other Circuits and their applications: a reference guide. - M.: Radio and communication, 1983, page 134, Fig. 4.34, and can be implemented, for example, on the chip TO IR (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 120).

Switching unit 3.17 identical to the switching unit 3.7, shown in Fig. 4, and is designed to switch the operation of the hashing 3 mode of reading the value of the secret key in the reading mode of the intermediate hash values of error-correcting block cryptogram to the first input of the computing unit modulo 3.18. The computing unit modulo 3.18 identical to the computing unit modulo 3.5, shown in Fig. 9, and p is a Prime number p, stored in the register 3.19.

Register 3.19 is designed to store the values of the Prime p. The scheme register 3.19 known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other Circuits and their applications: a reference guide. -M.: Radio and communication, 1983, page 134, Fig. 4.34, and can be implemented, for example, on the chip TO IR (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 120).

Element OR 3.2.0 is designed for the signal coming from the output of the comparator 3.11, or signal, polypaudio from the output of the comparator 3.13, the control input of switch 3.9. Element OR 3.21 is designed for the signal coming from the output of the comparator 3.11 or signal coming from the output of the inverter 3.22 on control input key 3.15. Schema elements OR 3.20 and 3.21 are identical, known and described, for example, in the book: C. A. Biryukov Digital devices in MOS integrated circuits". - M.: Radio and communication, 1990, pages 5 and can be implemented, for example, on the chip LE.

The inverter 3.22 designed for inverting the binary signal from the output of the comparator 3.13, and its output to the second input element OR 3.21. Diagram of the inverter 3.22 known and described, for example, in the book: C. sovan, for example, on the chip LP.

The memory module secret key 4 is designed to store the value of the secret key and its output to the input of a secret key block hashing 3. As the memory module secret key 4 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: B. A. Batashev, B. N. Veniaminov and other "Circuits and their applications: a reference guide". - M.: Radio and communication, 19S3, page 175, Fig. 5.12. The memory module secret key 4 may be implemented, for example, on the memory chip TO RU (see C. I. Korneichuk, B. N. Tarasenko "Computing devices on chips: a Handbook." -K.: Technika, 1988, pp. 85-87).

Switching unit 5 is identical to the switching unit 3.7, shown in Fig. 4 and is designed to switch the device mode values of the starting block of binary symbols in the input mode, the values of the error correcting unit cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram, on the first information input unit hashing 3.

The memory module starting unit 6 is designed to store the value of the starting blackbyte used static random access memory (RAM), scheme for the construction of which is known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other "Circuits and their applications: a reference guide". - M.: Radio and communication, 1983, page 175, rice, 5.12. The memory module starting block b may be implemented, for example, on-chip memory CRU (see C. I. Korneichuk, B. N. Tarasenko "Computing devices on chips: a Handbook." -K.:Technika, 1988, pp. 85-87).

The memory module unit cryptogram 7 is designed for recording the values of the error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, storage and issuing it to the input of a direct link. As the memory module unit cryptogram 7 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other "Circuits and their applications: a reference guide". - M. : Radio and communication. 1983, page 175, Fig. 5.12. The memory module unit cryptogram 7 may be implemented, for example, on-chip memory CRU (see C. I. Korneichuk, B. N. Tarasenko "Computing devices on chips: a Handbook." -K.:Technika, 1988. pages 85-87).

The memory module preceding the corresponding selected kashirovannuyu unit cryptogram, storage and issue it to the input of the switching unit 5. As the memory module of the previous cryptogram block 8 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other "Chips and their application; reference manual". - M.: Radio and communication, 1983, page 175, Fig. 5.12. The memory of the previous cryptogram block 8 may be implemented, for example, on the memory chip TO RU (see C. I. Korneichuk, B. N. Tarasenko "Computing devices on chips: a Handbook." -K.: Technika, 1988, pp. 85-87).

The switch 9 is identical to the switch 3.5.3 shown in Fig. 6, and is designed to switch the device operation mode, reading the value of error-correcting block cryptogram to the input of the block hashing 3 in the reading mode to the input of the memory module selected cryptogram block 7 and to the input of the memory module of the previous selected unit cryptogram 8.

The memory module error correcting blocks of cryptograms 10 shown in Fig. 10, is designed to store values previously generated error correcting blocks of cryptograms and read them on the information input switch 9.of addresses 10.2, multiplexer, 10.3 and storage module 10.4. The enable input write (log W) register storing address 10.2 information is input to the memory module error correcting blocks of cryptograms 10. To the input of the address generator signal 10.1 and the control input (S) of the multiplexer 10.3 serves the control signals. The output of address generator signal 10.1 is connected in parallel with the information log (log (N) of the register storing the address 10.2 and the second information input (input X2) multiplexer 10.3. The first information input (input X1) multiplexer 10.3 connected to the output of the register storing the address 10.2. The output of multiplexer 10.3 is connected to the input storage module 10.4, the output of the memory module 10.4 is the output of the memory module error correcting blocks of cryptograms 10.

The address generator signal 10.1 is designed to generate an address error correcting unit cryptogram read from the storage module 10.4 and generate addresses corresponding to the selected kashirovannuyu error correcting unit cryptogram error correcting unit cryptogram. The address generator signal 10,1 physical entity is a counter, which is known, see, for example, in the book: A. Sigarev,Tr. 128, rice, 518, and may be implemented, for example, on the chip CIE (see C. L. awl "Popular digital circuits". -M.: Radio and communication, 1987, pp. 90-93).

The register storing the address 10.2 is designed to store addresses corresponding to the selected kashirovannuyu error correcting unit cryptogram error correcting unit cryptogram. Diagram of the register storing the address 10.2 known, see, for example, in the book C. A. Batashev, C. N. Veniaminov and other "Circuits and their applications: a resource manual". - M.: Radio and communication, 1983, page 134, Fig. 4.34, and can be implemented, for example, on the chip CIR (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 120).

The multiplexer 10.3 is designed to switch the memory module error correcting blocks of cryptograms 10 mode sequential read values of N error correcting blocks of cryptograms in the read error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, memory module 10.4. Diagram of the multiplexer 10.3 known, is given in the book of L. A. Maltsev and other "fundamentals of digital techniques. -M.: Radio and communication, 1986, page 52, Fig. 48, and may be implemented, for example, on microsi module 10.4 is used for storing values of N error correcting blocks of cryptograms.

The storage module 10.4 is a ROM, which is known, see, for example, in the book of B. A. Batashev, B. N. Veniaminov and other "Circuits and their applications: a reference guide". - M.: Radio and communication, 1983, page 182, Fig. 5.17 and can be performed, for example, on the memory chips of the type CRT (see A. A. Sigarev, O. N. Lebedev microelectronic device design and processing of complex signals. -M.: Radio and communication, 1983, page 133, PL. 5.13).

The memory module received cryptogram block 11 is designed for recording from the output of the direct communication channel values of the received error correcting unit cryptogram, read and store it on the first information input of the identification block 12 and in parallel to the information input key 14, and also to erase adopted unidentified error correcting unit cryptogram. As the memory module is received cryptogram block 11 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other Circuits and their applications: a reference guide. - M.: Radio and communication, 1983, page 175, Fig. 5.12. The memory module received cryptogram block 11 may be implemented is iroshima: a Handbook." - K.:Technika, 1988, pp. 85-87).

The identification block 12 shown in Fig. 5, is designed to identify the value of the received error correcting unit cryptogram with values of N error correcting blocks of cryptograms stored in the memory module error correcting blocks of cryptograms 13. The identification block 12 consists of a comparator 12.1, the address generator 12.2 and shaper 12.3. The first information input of the comparator 12.1 is the first information input of the identification block 12, the second information input of the comparator 12.1 is the second information input unit indelicacy 12, the output of comparator 12.1 is connected to the input of the address generator 12.2 and in parallel with the input of the shaper 12.3. The output of address generator 12.2 is the first to control the output of the identification block 12. The output of the comparator 12.1 is the second control the output of the identification block 12. The output of shaper 12.3 is the third control the output of the identification block 12.,

The comparator 12.1 for comparison of a number value received from the output of the memory module received cryptogram block 11 with N values of error-correcting blocks of cryptograms stored in the memory module error correcting blocks of cryptograms 13, and to form the second input key 14. This control signal is generated by comparator 12.1, if the received error correcting unit cryptogram identified with any of the N error correcting blocks of cryptograms. The comparator circuit is known, see, for example, in the book of p. P. Maltsev, and other "Digital integrated circuits: a Handbook. -M. : Radio and communication, 1994, pages 83 and may be implemented, for example, on the chip CSP (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987, page 183).

The address generator 12.2 is designed to generate an address error correcting unit cryptogram read from the memory module error correcting blocks of cryptograms 13. The address generator 12.2 physical entity is a counter with a control input of the counter reset to zero, the scheme of which is known, see, for example, in the book: A. Sigarev, O. N. Lebedev

Microelectronic device design and processing of complex signals. -M Radio and communications, 1983, page 128, Fig. 5.18, and implemented, for example, on the chip CIE (see C. L. awl "Popular digital circuits". - M.: Radio and communication, 1987. pages 90-93).

Driver 12.3 is designed to generate the control signal, the control re-transmission of the floor of the stable block of the cryptogram, as well as managing erasing this error-correcting cryptogram from the memory module selected cryptogram block 7. The control signal for re-transmission of the message recipient, error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, is formed in the case, if the received error correcting unit cryptogram unidentified. In this case, the control signal controls the erasing of the received error correcting unit cryptogram from the memory module received cryptogram block 11. Diagram of the shaper 12.3 known by its physical nature is the inverter and identical to the scheme of the inverter 3.22.

The memory module error correcting blocks of cryptograms 13 is designed to store error correcting blocks of cryptograms and read them to the input of the identification block 12. As the memory module error correcting blocks of cryptograms 13 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: C. A. Batashev, B. N. Veniaminov and other Circuits and their applications: a reference guide. -M. : Radio and communication, 1983, page 175, Fig. 5.12. The memory module domehouse is. is Aracena "Computing devices on chips: a Handbook." -K.: Technika, 1988, pp. 85-87).

The key 14 is identical to the key 3.14 shown in Fig. 7, and is designed to control the reading of the received identified error correcting unit cryptogram from the output of the memory module received cryptogram block 11 on the second information input unit hashing 16 and in parallel to the input of the memory module preceding the received cryptogram block 18. Reading is permitted upon receipt of the control signal from the third control output of the identification block 12 to the control input of the key 14.

The memory module secret key 15 is designed to store a secret key and its output to the input of a secret key block hashing 16. As the memory module secret key 1.5 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other "Circuits and their applications: a reference guide". - M.: Radio and communication, 1983, page 175, Fig. 5.12. The memory module secret key 15 may be implemented, for example, on-chip memory CRU (see C. I. Korneichuk, B. N. Tarasenko, computer ustrojavanje 3, it is shown in Fig. 3, and is designed for hashing received identified error correcting unit cryptogram on hash functions, secret key, and the starting block of binary characters when decrypting the first information block q-ary symbols or previous adopted identified by the error correcting unit cryptogram when the decryption of the next information block q-ary symbols.

Switching unit 17 is identical to the switching unit 3.7, shown in Fig. 4, and is designed to switch the device operation mode, reading the value of the starting block of binary symbols to decrypt the first data block q-ary symbols in the reading mode and the previous received identified error correcting unit cryptogram when the decryption of the next information block q-ary symbols on the first information input unit 16 hash.

The memory of the previous received block cryptogram 1.8 is designed for recording the received identified error correcting unit cryptogram, storage and issuing it to the second input of the switching unit 17. As the memory module of the previous received block cryptogram 18 local and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other "Circuits and their applications: a reference guide". - M.: Radio and communication. 1983, page 175, Fig. 5.12. The memory of the previous received cryptogram block 18 may be implemented, for example, on-chip memory CRU (see C. I. Korneichuk, B. N. Tarasenko "Computing devices on chips: a Handbook." -K.: Technika, 1988, pp. 85-87).

The memory module starting unit 19 is designed to store the starting block of binary symbols and read it at the first input of the switching unit 17. As the memory module starting block 19 can be used in a static random access memory (RAM), the scheme of which is known and described, for example, in the book: C. A. Batashev, C. N. Veniaminov and other "Chips and their application; reference manual". - M.; Chapman and hall, 1983, page 175, Fig. 5.12. The memory module starting block of binary symbols 19 may be implemented, for example, on-chip memory CRU (see C. I. Korneichuk. B. N. Tarasenko "Computing devices on chips: a Handbook." -K.: Technika, 1988, pages 85 - 87).

The claimed device encryption/decryption of messages hashiriya function works as follows.

Prewar the new error-correcting blocks of cryptograms, in memory of the starting unit 6 and 19 write the value of a previously transmitted between the sender and receiver of the message start of block of binary symbols in the memory of the secret key 4 and 15 write the value of a previously transmitted between the sender and the message recipient's secret key.

The information sequence of q-ary symbols from the output of analog-to-digital Converter messages that are not part of the claimed device and not shown in the drawings, is received at the input device encryption/decryption of messages hashiriya function shown in Fig.1, and is read to the input of the memory module information block 1. As analog-to-digital Converter can be used, for example, the encoder pulse code modulation that generates the output q-ary symbols. The paging message is represented by an information sequence of q-ary symbols, implemented a sequential write n of another q-ary symbols in the module memory information block 1. The control signals received at a control input of the memory module information block 1, and the control account n q-ary symbols of the first and the subsequent info is, 12(m), served on the control input (S) of the multiplexer 2.6, which is the second managing unit select 3, poluchaetsya second information input (input Y) multiplexer 2.6 on its output and writes to all memory cells of the register storing the minimum amount 2.5 unit 2 of the information signal in the form of a code combination consisting of the single character "1", which provides the initial filling of the register storing the minimum amount of 2.5 maximum value of the stored number.

To encrypt the first information block q-ary symbols N error correcting blocks of cryptograms hairout on hash functions, secret key, and the starting block of binary symbols in the block hashing 3. The value of the secret key stored in the memory module secret key 4, N times is read on input a secret key block hashing 3 on the control signal shown in Fig. 12(b) received at a control input of the memory module secret key 4. The value of the starting block of binary symbols stored in the memory module starting block 6, N times is read at the first input of the switching unit 5 to the control signal shown in Fig. 12(C) arriving at the panel the first input of the switching unit 5 is switched to the output of this block. This switching is performed when it arrives at the control input of the switching unit 5 of the control signal unit level, as shown in Fig. 12(g), and reads the values of the starting block of binary symbols on the first information input unit hashing 3.

The values of N error correcting blocks of cryptograms stored in the memory module error correcting blocks of cryptograms 10, in turn, from first to N-th read information switch input 9 of the control signal shown in Fig. 12(W) supplied to the second control input of the memory module error correcting blocks of cryptograms 10. The data control signals counted by the counter 10.1. The output signal of the counter 10,1 supplied to the second information input (input X2) multiplexer 10.3, is switched to the input storage module 10.4 fed to the control input (S) of the multiplexer 10.3 control signal of a zero level, as shown in Fig. 12(C). Mode hashing N error correcting blocks of cryptograms information input switch 9 is switched to its first output under the control of the control signal unit level received at a control input of the switch 9 and shows the Odom block hashing 3, that ensures alternate with the first through N-th read values of N error correcting blocks of cryptograms on the second information input unit hashing 3.

In block hashing 3 steps of the construction value of the secret key a to the extent the total value of the starting block of binary symbols and values first, and then the next, the error correcting unit cryptogram, and the calculation of the unit-values of the Prime numbers p and q are executed in sequential action: calculates the total value of the starting block of binary symbols and values first, and then the next, the error correcting unit cryptogram if the calculated total value is zero, the output unit 3 hash value hash error correcting unit cryptogram read a single value. If the calculated total value is a unit, the computing unit modulo 3.5 computes the secret key modulo p, and is read from the output unit 3 hash value hash error correcting unit cryptogram. If the calculated total value is neither a unit nor a zero, then the value of the data is the value the value of the intermediate results of the multiplication are computed modulo q, the resulting value of the multiplication is computed modulo p, and is read from the output unit 3 hash value hash error correcting unit cryptogram.

Steps hashing error correcting unit cryptogram block hashing 3 are as follows. The value of the secret key is read on input a secret key block hashing 3. Write the value of the secret key is performed by the control signal on the control input of the switching unit 3.17, which is the second managing unit 3 hash. The appearance of this control signal shown in Fig.13(a). This control signal polychaet first information input of the switching unit 3.17 on its output, thereby providing a record of the values of the secret key at the first input of the computing unit modulo 3.18. The appearance of the signal of the secret key shown in Fig.13(b). From the output of the register 3.19 reads the value of p according to the second input of the computing unit modulo 3.18. To write the values of the secret key and the number p and the subsequent calculation of the residue from division by managing vodoprivredi signal, view of which is shown in Fig.13(b). In the computing unit modulo 3.18 the value of the secret key is supplied to the first information input key 3.18.5, prokruchenny on his way out, and recorded in the register 3.18.1. Register 3.18.1 the value of the secret key is supplied to the first input of vicites 3.18.2. To the second input of vicites 3.18.2 sprinkles value of R. the Calculated differential value from the output of vicites 3.18.2 is supplied to the second input of the comparator 3.18.4. When the difference value is less than the value p, then the output signal of the comparator 3.18.4 received at a control input, polychaet information input switch 3.18.3 at its second output, which is the output of the computing unit modulo 3.18. Otherwise, the output signal of the comparator 3.18.4 polychaet information input switch 3.18.3 at its first output, a differential value from the output of vicites 3.18.2 is overwritten in the register 3.18.1, in myCitadel 3.18.2 subtracted the value of the number p, and the previously described steps are repeated.

Since in this case the value of p is greater than the value of the secret key a, and so a mod p = a, then from the output of the computing unit modulo 3.18 in the case 3.16 value is written as. On the control input klucze in Fig. 13(g). This control signal opens the key 3.14 and through public key 3.14 recorded in the register 3.16 value and is overwritten in the register 3.12.

The first and second inputs of the adder 3.1, which is the first and the second information input unit 3 hash, read the value of the starting block of binary symbols and the value of the first, and then the next, the error correcting unit cryptogram. Their total value is shown in Fig. 13(e), from the output of the adder 3.1 is read by the first information input of the switching unit 3.3 and the first comparator input 3.4. In the comparator 3.4 total value is compared to zero and if equality is generated at the output of the comparator 3.4 signal at the control input of the switching unit 3.7, allowing the passage of a single signal value from the first information input of the switching unit 3.7 on his way out and record this signal on the first input of the computing unit modulo 3.5. On the control input of the computing unit modulo 3.5, which is the fourth managing unit hashing 3, receives the control signals, the view of which is shown in Fig. 13(g). From the output of the register 3.2 to the second input of the computing unit of the balance of delenne 3.5, identical to the previously described sequence of actions performed in the computing unit modulo 3.18. As the value of the number q more than a single value, and therefore 1 mod q = 1, then the output of the computing unit modulo 3.5 single value is read on the output unit 3 hash value hash error correcting unit cryptogram. View hashed error correcting unit cryptogram shown in Fig.13(C).

If the total value of the read input of the comparator 3.4 is not equal to zero, then the control signal from the output of the comparator 3,4 polychaet second information input of the switching unit 3.7 on its output. A single value of the control signal is shown in Fig. 13(d), is fed to the control input of the switching unit 3.3, which is the first managing unit hashing 3, and poluchaut first information input of the switching unit 3.3 on his way out. The total value of the output of the adder 3.1 through switching unit 3.3 is read in the register 3.6 and corresponds to the first input of vicites 3.8. Of the total recorded value in myCitadel 3.8 subtracted a single value. Decremented value is compared in the comparator 3.13 with zero snakeeater 3.9. The value of register 3.12. read to the second input of multiplier 3.10 and in the absence of the second factor value and is read from the output of the multiplier 3.10 input switch 3.9, prokruchenny on his way out. The output signal of the comparator 3.4 polychaet second information input of the switching unit 3.7 on his way out and is and is read to the input of the computing unit modulo z 5, which is a mod p is read on the output unit 3 hash value hash error correcting unit cryptogram.

At the same time the value from the output of vicites 3.8 compared with a single value in the comparator 3.11 and when they are equal, the output signal of the comparator 3.11 through the element OR 3.20 polychaet second information input of the switch 3.9 on his way out. This same output signal of the comparator 3.11, inverted in inverter 3.22 passes through the element OR 3.21 and polychaet information input key 3.15 on his way out. Therefore, the value as read from register 3.16 through public key 3.15 at the first input of the multiplier 3.10 and at the output of the multiplier 3.10 is formed is a mod R. This value from the output of the multiplier 3.10 through the switch 3.9 and switching unit 3.7 to the input of the computing unit of the balance of Deleni is no single, neither is zero, then the zero value of the control signal received at a control input of the switching unit 3.3, is shown in Fig. 13(d), this value with the second information block commutation 3.3 read its output, and the previously described steps are repeated until such time as the input of the unit for computing the modulo 3.5 will not be the value of the secret key, to the extent the total value modulo the number of R.

Read from unit 3 hash value of the digital representation of the k-th q-ary symbols of the i-th hash error correcting unit cryptogram fed to the input (input B) myCitadel 2.1 unit 2. Type read from unit 3 hash hashed error correcting blocks shown in Fig.12(and). To the second input (input a) myCitadel 2.1 in accordance with the control signal received at a control input of the memory module information unit 1 shown in Fig. 12(K) are values of the digital representation of the k-th q - ary symbols of an information block from the memory module information block 1. In myCitadel 2.1 are subtracting from the value of the digital representation of the k-th q-ary symbols of the i-th ( i=1,2,..,N) hash error correcting unit cryptogram sootvetstvuyuschengo adds up the values of the obtained differences.

With the receipt of the control signal shown in Fig. 12(l), the control input of the controlled switch 2.3, which is the first Manager of the input unit 2, the value obtained from the output of the adder 2.2 is input (input B) of the comparator 2.4 and at the same time on the first information input (input X) multiplexer 2.6. On the control input (S) of the multiplexer 2.6, which is the second managing unit selection 2, receives the control signal unit level, as shown in Fig. 12(m). This control signal commented the output of the adder 2.2 on input X of the register storing the minimum amount of 2.5. To the second input (the input) of the comparator 2.4 receives the value stored in the register storing the minimum amount of 2.5. Output (output AB) comparator 2.4 formed a control signal, provided that the value of the signal on the second input (input B) is not more than the value of the signal on the first input (input a). This control signal filed on (log W) the write-enable register storing the minimum amount of 2.5, provides an update value register storing the minimum amount of 2.5 output signal from the adder 2.2 using a managed switch 2.3. In each i-th cycle of the block 2 in the register storing the minimum e, than the stored value in the memory register storing the minimum amount of 2.5.

Formed at the output of the comparator 2.4 control signal, which is the output signal of the block selection 2, is input to the write-enable (log W) register storing address 10.2 memory module error correcting blocks of cryptograms 10 and provides a record of the next i-th value of the address block from the output of the address generator 10.1 register storing address 10.2. In the register storing the address 10.2 will be written to the new address value provided that at the output of the comparator 2.4 unit 2 will be formed a new control signal. After N cycles of operation of the block selection 2 register storing the minimum amount of 2.5 to be written is the minimum sum of differences, and in the holding register addresses 10.2 will be written to the address value of the error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram. Selected hashed robust unit cryptogram is closest to the first information block q-ary symbols.

Upon receipt of the control signal of zero level, as shown in Fig. 12(e), to the control input of the switch 9 it is but a single level, it is shown in Fig.12(C), the first control input of the memory module error correcting blocks of cryptograms 10 address value error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram from the register storing the address 10.2 through multiplexer 10.3 is read to the input storage module 10.4. The value of the error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, is read through the second information output switch 9 on the information input to the memory module unit cryptogram 7 and parallel to the information input of the memory module of the previous cryptogram block 8. By the same control signal at the control input of the memory module unit cryptogram 7 and the control input of the memory module of the previous cryptogram block 8, in the memory unit cryptogram 7 and in the memory of the previous block cryptogram 8 records the value of the error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram.

Upon receipt of the control signal shown in Fig. 12(h), the second control input of the memory module b the corresponding selected kashirovannuyu error correcting unit cryptogram, transmitted by direct communication channel to the receiver of the message.

At the receiving node from the output of a direct channel of communication adopted by the error correcting unit cryptogram is read to the input of the memory module received cryptogram block 11. Record n q-ary symbol error correcting block cryptograms control signals received at a control input of the memory module received cryptogram block 11 shown in Fig. 12(a).

Upon receipt of control signals shown in Fig. 12(p), the control input of the memory module received cryptogram block 11, the output of this module is received error-correcting block cryptogram is read by the first information input of the identification block 12. Upon receipt of the control signal shown in Fig. 12(b), the control input of the identification block 12 address generator 12.2 is set to the initial state I is sequentially generates first through N-th address error-correcting blocks of cryptograms read from the memory module error correcting blocks of cryptograms 13. From the first to the N-th error-correcting blocks of cryptograms, in accordance with the generated address is read by the second information input of the identification block 12. With togram triggered comparator 12.1 and generates the control signal, arriving on the second control output of the identification block 12 and the opening key 14. If adopted by the error correcting unit cryptogram not identified, that is, the comparator 12.1 does not work for reading N error correcting blocks of cryptograms, (former 12.3 generates the control signal, the controlling re-transmission of the message recipient, error correcting unit cryptogram corresponding to the selected kashirovannuyu noiseproof cryptogram block, and erasing unidentified received error correcting unit cryptogram from the memory module received cryptogram block 11. This control signal unit level, as shown in Fig. 12(C), is formed on the second control output of the identification block 12. When receiving the first control input of the memory module unit 7 of this cryptogram of the control signal of zero level is erased robust unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, and if the signal unit is re-transmission error-correcting block cryptogram corresponding to the selected kashirovannuyu robust nl is officiously robust unit cryptogram hairout on hash functions, the secret key and the starting block of binary symbols in the block hash 16. The value of the secret key stored in the memory module secret key 15, is read on input a secret key block hashing 16 of the control signal shown in Fig. 12(t) received at a control input of the memory module secret key 15. The value of the starting block of binary symbols stored in the memory module starting block 19, is read by the first information input of the switching unit 17 to the control signal shown in Fig. 12(y) received at the control input of the memory module starting block 19. To decrypt the first data block q-ary symbols of the first information input of the switching unit 17 is switched to the output unit. This switching is performed when it arrives at the control input of the switching unit 17 of the control signal unit level, as shown in Fig. 12(f), and reads the values of the starting block of binary symbols at the first input of the block hash 16. Through the information output public key 14 on the second information input unit hashing 16 reads the value of the received identified error correcting unit cryptogram.

From the output of the block hash 16, which is the output of the device, read the first decrypted information block q-ary symbols.

For encryption of the next information block q - ary symbols is shown in Fig. 12(a), N error correcting blocks of cryptograms re hairout on hash functions, secret key, and error correcting unit cryptogram associated with the selected kashirovannuyu error correcting unit cryptogram, and perform the subsequent steps. Honors actions from the action when encrypting/decrypting the first information block q-ary symbols is the following.

On the sending node to the control input of the switching unit 5 receives the control signal of zero level, as shown in Fig. 12(g), and reads the values of the error correcting unit cryptogram corresponding to the selected kashirovannuyu noiseproof cryptogram block on the first information input unit 3 hash. The value of the error correcting unit cryptogram corresponding to the selected error correcting block is tion 5 of the control signal, it is shown in Fig. 12(x) received at a control input of the memory module of the previous cryptogram block 8. For encryption of the next information block q-ary symbols of the second information input of the switching unit 5 is switched to the output of the block that provides the read information to the input unit 3 hash values of the error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram. Next steps for encryption of the next information block q-ary symbols are identical when encrypting the first information block q-ary symbols.

At the receiving node, the value of the previous received identified error correcting unit cryptogram stored in the memory module of the previous received cryptogram block 18, is read by the second information input of the switching unit 17 to the control signal shown in Fig. 12(C) received at a control input of the memory module of the previous received block cryptogram. For decryption of the next information block q-ary symbols of the second information input of the switching unit 17 is switched to the output of the same block. Taka is level, it is shown in Fig. 12(f).

For decryption of the next information block q-ary symbols adopted by the identified error correcting unit cryptogram hairout on hash functions, secret key, and the previous received identified error correcting unit cryptogram block hashing 16. Steps hashing the received identified error correcting unit cryptogram on hash functions, secret key, and the previous received identified error correcting unit cryptogram block hashing 16 are identical hash of the received identified error correcting unit cryptogram on hash functions, secret key, and the starting block of binary symbols.

From the output of the block hash 16, which is the output of the device, read the next decrypted information block q-ary symbols, and describes the steps performed to Ter long as you do regular information blocks q-ary symbols.

1. Encryption/decryption of messages hashiriya function, which consists in the preliminary formation of hash functions, secret key, and the starting block of binary symbols, split the message into information blocks of symbols, the hashing message sender blocks of binary symbols, the transmission of the message recipient blocks of binary symbols and hashing the received blocks of binary symbols, characterized in that it further pre-form N error correcting blocks of cryptograms, where N > 2, hachirou error correcting blocks of cryptograms on hash functions, secret key, and the starting block of binary symbols, compare each i-th, where i = 1, 2, ..., N, hashed robust cryptogram block with the first block of information of q-ary symbols, where q > 2, among N hashed error correcting blocks cryptogram choose the most close to the first information block q-ary symbols, transmit a direct communication channel to the receiver of the message error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, identify adopted by the error correcting unit cryptogram with N error correcting blocks of cryptograms and if they are not identified, wash adopted by the error correcting unit cryptogram and a reverse communication channel transmit a control signal for re-transmission to the recipient the message is the eye of the cryptogram, adopted by the identified error correcting unit cryptogram hairout on hash functions, secret key, and the starting block of binary symbols, re-hairout N error correcting blocks of cryptograms on hash functions, secret key, and error correcting unit cryptogram corresponding selected in the previous step kashirovannuyu error correcting unit cryptogram, compare each i-th, where i = 1, 2, ..., N, hashed robust cryptogram block with the next block of information of q-ary symbols, choose among N error correcting blocks of cryptograms is closest to the next information block q-ary symbols, transmit a direct communication channel to the receiver of the message error correcting unit cryptogram corresponding to the selected kashirovannuyu error correcting unit cryptogram, identify adopted by the error correcting unit cryptogram with N error correcting blocks of cryptograms and if they are not identified, wash adopted by the error correcting unit cryptogram and a reverse communication channel transmit a control signal for re-transmission of the message recipient, error correcting unit cryptogram corresponding to the selected casinowebcam on hash functions, the secret key and the previous adopted identified by the error correcting unit cryptogram, and re-hashing of error-correcting blocks of cryptograms and the subsequent steps are performed until now receiving regular information blocks q-ary symbols.

2. The method according to p. 1, characterized in that the formation of the N error correcting blocks of cryptograms performed by multiplying each of the N blocks of binary symbols to generate a matrix of binary error-correcting code.

3. The method according to p. 1, characterized in that the comparison of each of the i-th, where i = 1, 2, ..., N, hash error correcting unit cryptogram information block q-ary symbols from the value of each q-ary counting the i-th hash error correcting unit cryptogram subtract the corresponding value of the q-ary reference information block q-ary symbols, for each i-th hash error correcting unit cryptogram absolute value of the obtained difference summarize, and the closest hashed robust unit cryptogram to the information block q-ary symbols choose the appropriate minimum amount of the obtained differences.

4. The mouth of the information block, which input is the input of the block hash, input a secret key which is connected to the output of the memory module secret key, the first information input of the block hash is connected to the output of the switching unit, the first input of the switching unit is connected to the output of the memory module starting block, the second input of the switching unit is connected to the output of the memory module previously selected block of the cryptogram, memory module selected block of the cryptogram, the information output of which is connected to the input of the direct communication channel, and at the receiving node, the memory module received cryptogram block, whose input is connected to the output of the direct communication channel, the block hash input a secret key which is connected to the output of the memory module secret key, the first information input of the block hash is connected to the output of the switching unit, the first input of the switching unit is connected to the output of the memory module starting block, the second input of the switching unit is connected to the output of the memory module preceding the received cryptogram block, characterized in that it further on the sending site put selection block, the first information input of which is connected with the memory module information unit, the second information is th input of the memory module error correcting blocks of cryptograms, the output of which is connected with the information output switch, a first output switch connected to the second information input of the hash, the second information output switch connected to an information input of the memory module unit cryptogram and parallel to the input of the memory module of the previous block of the cryptogram, the first control input of the memory module unit cryptogram is connected to the output of the reverse communication channel, and at the receiving node further introduced the identification block, the first information input connected to the output of the memory module received cryptogram block, the second information input of the identification block is connected to the output of the memory module error correcting blocks of cryptograms, the first control output of the identification block is connected with the control input of the memory module error correcting blocks of cryptograms, the second control output of the identification block is connected with the control input of the key, the third control output of the identification block is connected to the input of the reverse communication channel and in parallel with the input erase the memory module of the received cryptogram block, an information input key is connected to the output of the memory module received cryptogram block, the m memory module of the previous received block of the cryptogram, the output of block hash is the output device, and memory information block, the block selection block hashing, memory module secret key, the switching unit, the memory module starting block, the memory block of the cryptogram, memory of the previous block of the cryptogram, memory module error correcting blocks of the cryptogram, the switch on the sending node, the memory module received blocks of the cryptogram, the identification block, the switching unit, the memory module secret key, the block hash, switching unit, a memory module of the previous received block cryptogram, memory module starting block at the receiving node is equipped with control inputs.

 

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FIELD: cryptography.

SUBSTANCE: method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2l, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (ub, ud) are used, on basis of random replacement tables, for generating next random number values z1=F(ui, uj), z2=F(ut, um), zg=F(z1, z2) are calculated, where ui, uj, ut, um - values of filling of respective register digits, value of result in check connection networks zg is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed.

EFFECT: higher speed and efficiency.

3 cl

FIELD: electrical communications and computer engineering; cryptographic data conversion.

SUBSTANCE: proposed method includes generation of protection key in the form of n-bit binary vector, its supply for initial filling of shift register producing maximal-length pseudorandom character sequence, conversion of data stream into encoded message, and its transfer over communication line; in the process total character of encoded text is shaped and its value is conveyed at moment when search sequence character assumed value equal to unity.

EFFECT: reduced redundancy in message transferred and enhanced message transfer speed.

1 cl, 2 dwg

FIELD: electric communications.

SUBSTANCE: method is performed using microcontrollers with two memory types: data and software. For transfer of each symbol individual main and reserve codes are used, on basis of number of repeats of symbol in transferred message. First transfer of symbol is performed by main code, second transfer of same symbol - by reserve code, and then codes synchronization displacement is activated for a step around circle relatively to symbols until finish of circle. After transfer of displaced reserve code, closing the circle, synchronous replacement of codes variants is performed, and then order of codes replacement is repeated in case of repeat of any symbol in transferred message. Number of required code variants is set by planned volume of information, sent via communication line.

EFFECT: higher efficiency.

1 dwg

FIELD: data carriers.

SUBSTANCE: data carrier is made in such a way, that for important data protection operations confidential data stored in chip memory or formed by it are separated on at least three portions, also provided is processor for calculation of random number and for dividing confidential data on such random number, while first portion of data is an integer result of such division, and third portion of data is the actual random number.

EFFECT: higher quality of data protection.

3 cl, 1 dwg

FIELD: computer science, communications.

SUBSTANCE: method includes generating a protection key in form of a binary vector n-bit long, sending it for primary filling of displacement register, generating pseudo-random series of maximal length, generating pseudo-random series of symbols, transforming data stream to encrypted message and transmitting the latter along communication line, while pseudo-random series is generated as pseudo-random series of symbols of finite field Fp with characteristic p=2k+1 in form of binary vectors k-nit long by getting information from k different bytes of displacement register with check connection, numbers of which are determined on basis of protection key, and number k is selected equal to one of members of geometric row, which has denominator and first member equal to two, and also a pseudo-random series of symbols is formed for finite field of odd values of symbols due to skipping clock pulses of displacement register with check connection for which pseudo-random series symbols take even values and serially transforming in finite field Fp symbols of source text by involution thereof, appropriate for pseudo-random series symbols.

EFFECT: higher resistance to attacks on basis of known and sorted out texts.

4 cl, 2 dwg

FIELD: radio engineering; secret intelligence protected radio communication systems.

SUBSTANCE: proposed radio communication system incorporating provision for suppressing enemy's radio communication means and radio control channels has information subsystem, noise jamming subsystem, noise memory subsystem, information subsystem elements, and subsystem elements interface unit; each element of information subsystem is made in the form of multichannel time-division radio station; each element of noise jamming subsystem is made in the form of time division multichannel radio station, and each of noise jamming subsystem elements is made in the form of barrage jamming transmitter built around noise signal generating driver; used as drivers are self-stochastic generator operating in different frequency bands.

EFFECT: enhanced intelligence protection of communication channels, simplified design, enhanced reliability.

2 cl, 13 dwg

FIELD: information protection.

SUBSTANCE: method for transferring messages while providing for confidentiality of identification signs of communication system objects with interaction of devices of communication system subscribers through central device for each communication session cryptographic conversion of subscriber device identifier is performed using encryption key of current subscriber device, while during said cryptographic conversion symmetrical cryptographic algorithm is used and two message transfer modes are taken in consideration, on initiative from subscriber device to central device and vice versa.

EFFECT: protection from unsanctioned access to identifiers of devices of system subscribers transferred via communication channels, in particular when providing for confidentiality of messages identification signs in communications systems with multiple subscriber devices.

6 dwg

FIELD: data processing.

SUBSTANCE: before beginning of decoding all possible non-repeating meanings of combinations of alphabet ui are recorded randomly into code spreadsheet with N lines by means of random numbers detector (RND). Number i of code line of code spreadsheet Tk is recorded in each line ui of address spreadsheet Ta. Meaning of combinations of alphabet ui is recorded in spreadsheet Tk, where N-size of alphabet coincident with number of lines of code and address spreadsheets Tk and Ta, ui is original combination being subject to coding. Moreover for filling any next i-line and line from code spreadsheet Tk (where i equals 1 to N) the next meaning of combination of alphabet from RND which is subsequently compared with each i-th meaning from recorded combinations of alphabet in code spreadsheet Tk. In case there is no coincidence with any recorded combinations of alphabet, the next meaning of combination of alphabet ui is recorded into i-th line of code spreadsheet Tk. When coding line ui of address spreadsheet Ta the address A(ui) of original combination is read out from code spreadsheet Tk. Value of coded combination vi of original combination ui at value of parameter of conversion of ξi equals to value of combination of alphabet being stored in line A(vi) of code spreadsheet Tk, which address is determined as A(vi)=A(ui)+ξi for module of N number. Value of coded combination vi is read out from line of code spreadsheet Tk with address A(vi). When decoding coded combination vi at value of conversion parameter of ξi the value of combination is defined, which combination is stored in address line A(ui) of spreadsheet Tk which address is determined as A(ui)=A(vi) - ξi for module N number. Value of ui combination is read out from line of code spreadsheet Tk having address A(ui).

EFFECT: increased speed of data processing.

FIELD: computer science.

SUBSTANCE: method is based on block-wise conversion of message, dependently on secret key, to Cyrillic text.

EFFECT: possible use of Russian texts as containers for steganographic conversion, decreased dependence of statistic characteristics of modified container from concealed message.

2 cl, 6 dwg

FIELD: cryptography.

SUBSTANCE: block for generation of sub-keys data uses two different processes for open generation of sub-keys. During encoding of T*n block of open text, where T - length of predetermined cycle, n - positive integer, sixteen sets of sub-key data is generated. In al other cases two sets of sub-key data are generated. Encryption block encrypts open text, using formed sixteen or two sets of sub-keys data.

EFFECT: higher efficiency.

6 cl, 15 dwg

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