The amplification circuit voltage for use in semiconductor memory device

 

(57) Abstract:

The circuit gain voltage gain supply voltage VCC supplied from the system to the desired level amplifying voltage V. The amplification circuit voltage contains the transmitting transistor formed by tracemanager of the manufacturing process. The transmitting transistor has bipolar characteristics and acts as a bipolar diode. Effect: increases the efficiency of amplification, because it does not change the current flowing in the amplifying an anchor point, even if amplifying the voltage at this point is increased. 3 C.p. f-crystals, 5 Il.

The invention relates to a semiconductor memory device and, in particular, to the amplifying circuit voltage (as used herein, the term "circuit voltage gain" has the same meaning as "amplifier circuit", "chain develop increased tension", "single-stage amplification circuit with a compensation feedback" and so on) to gain supplied from the system supply voltage to the desired gain level voltage.

In the semiconductor memory device such as a dynamic RAM (random access memory device or memory with random calls CMOS transistors, is the voltage drop of the MOS transistor during transmission capacity through the channel region of the MOS transistor. This unwanted voltage drop becomes an obstacle to accurately read and write data, and also leads to data loss. To solve the problem, it is necessary to use the circuit gain of the voltage to increase the voltage level. Known hardware device (see patent Korea N 91-19740 issued on a patent application that was filed on November 07, 1991, entitled "Circuit voltage gain and owned by the present applicant: the document entitled "A 35ns 64 Mb DRAM Using - Onship Boosted Power Supply" 1992 Symposium on ULSI Circuits Digest of Technical Paper, pp. 64 - 65; U.S. patent N 4704706 issued by a foreign company Japan Fudjitsu Co. etc.)

Fig. 1 schematically shows a typical part of the amplifying circuit voltage, is well known in the art and described in the above documents. Input the nodal point of the electric circuit 2 receives the oscillating signal OSC generated by the generator (not shown). Charge the capacitor 4 by its output connected to the input nodal point 2, and the other output from secondary anchor point 8. Charge the capacitor by its output connected to the input of knots is om and runoff from feed points 8 and 10, respectively, produces amplifying the voltage VPP. Additionally, not shown in Fig. 1 chain preparada for preparada secondary anchor points 8 and 10 to the level of the supply voltage VCC. The design according to Fig. 1 known from the prior art as a chain of filing of the charge. The generator operates when amplifying the voltage VPP is lowered to below normal internal circuit in the process of powering the chip and its active cycle. If the oscillating signal OSC is applied to the input node 2, secondary capacitors 4 and 6 lead charge nodal points 8 and 10 to a voltage approximately equal to twice the supply voltage VCC. Voltage, filed on pre-supply node 10, is transmitted through the transmitting channel of the transistor 12 in the form of amplifying voltage VPP. The circuit according to Fig. 1 is driven by a generator that uses the supply voltage VCC as the voltage source, so that you can reach the level of amplifying the voltage VPP is equal to 2 VCC-VT (where VT is the limit voltage of the transmitting transistor 12). Secondary anchor points 8 and 10 in the initial state prezerajte to the level of the supply voltage VCC.

The amplification circuit voltage according to Fig. 1 is formed using a typical Prieto transmitting transistor 12 is a CMOS transistor, formed in the manufacturing process of the CMOS. As is well known in the art, the MOS transistor has the following design characteristics that the effect of the substrate increases with increasing voltage between its source and drain. It is obvious that the effect of the substrate increases even more if the dimensions of each device are reduced and the intervals between them become more narrow with increasing integration of semiconductor memory devices. The amplification circuit voltage according to Fig. 1 has the fundamental disadvantage that the efficiency of the swap decreases the constructive characteristics of the MOS transistor, i.e., the transmitting transistor and not the structure of the chain.

Brief description of the invention

The object of the invention is amplifying circuit voltage to improve the effectiveness of the swap.

Another object of the invention is circuitry voltage to generate an amplifying voltage at high speed.

Another object of the invention is amplifying circuit voltage to improve the effectiveness of the swap, regardless of the effect of the substrate, even if the level of the amplifying voltage increases.

Additional Atraktivnih characteristics of the transmitting transistor.

In accordance with one aspect of the present invention provides amplification circuit voltage to generate voltage by amplifying the transmitting transistor with characteristics of a bipolar transistor. The amplification circuit voltage contains the transmitting transistor formed "trencherman" process conventional process of manufacturing the CMOS. The transmitting transistor acts as a bipolar diode containing a pocket pair of the second conductivity type formed on the substrate of the first conductivity type, the second pocket of the first conductivity type, formed inside the first pocket, the first diffusion layer of the second conductivity type formed inside the first pocket, but not mentioned inside the second pocket, the first diffusion layer is connected to the line connected to charge the capacitor; a first diffusion layer of the first conductivity type, formed within the mentioned second pocket and connected to said line, and a second diffusion layer of the second conductivity type, formed within the mentioned second pocket and is connected to an amplifying host.

Brief description of drawings

For a better understanding of the invention, ukazanii, are:

Fig. 1 is a schematic diagram showing a typical part of the conventional amplifying circuit voltage;

Fig. 2 is an equivalent circuit showing a schematic construction of the amplifying circuit voltage in accordance with the present invention;

Fig. 3 is a view in section of a structural implementation of the circuit of Fig. 2;

Fig. 4 is a schematic diagram showing one embodiment of the amplifying circuit voltage in accordance with Fig. 2 and 3;

Fig. 5 is a graph showing curves of increasing the resulting amplifying voltage VPP in the circuit of Fig. 4.

A detailed description of the preferred options for performing

In Fig. 2 circuit voltage gain according to the present invention uses a bipolar transistor 26 as the transmitting transistor for generating an amplifying voltage VPP. It should be noted that the term "bipolar transistor" means the same as "bipolar diode and transmitting bipolar transistor", applied below. As is well known in the art, the bipolar transistor is a device managed by the current, while the MOS transistor is a device managed by naprjazhennosti. The transmitting transistor 26 created from a bipolar transistor as the amplifying circuit voltage has a complex structural characteristics, and has such advantages as improved efficiency swap, high speed gain to the desired level of amplification and the prevention effect of the substrate.

Fig. 3 is a view in section of a structural implementation of the circuit of Fig. 2. Bipolar transistor 26 is formed tricarbonyl process conventional process of manufacturing the CMOS. Briefly, the process of manufacturing a bipolar transistor 26 as the transmitting transistor is as follows. N-pocket 30 is formed on the substrate 28 of P-type conductivity. P-pocket 32 is formed in the middle part of the N-pocket 30. Inside the N-pocket 30, but outside of the P-pocket 32 formed of the n+ layer 38 by making the n+ impurity, the p+ layer 40 and the n+ layer 42 is formed inside the P-pocket 32 by making the p+ and n+ impurities, respectively. So is the structure of the bipolar transistor 26, shown in Fig. 2. n+ layers 34 and 36 formed by depositing an n+ impurity on a substrate 28 of P-type, and the shutter 35 is formed charge the capacitor 22 of Fig. 2. Since the structure according to Fig. 3 is readily achievable using conventional process podney anchor point 20 and frighten formed on them, the shutter 35 in response to the voltage at the input node 20, thus swapping swapping anchor point 24, connected to the shutter 35. It should be noted that the secondary anchor point 24 is typically connected with the n+ layer 38 within the N-pocket 30 and the p+ layer 40 within the P-pocket 32, the details of which will be discussed later. Line to which is applied amplifying the voltage VPP, is connected with the n+ layer 42 within the P-pocket 32. It is easy to understand that bipolar transistor 26 operates through the P-pocket 32 between the active anchor point 24 and line amplifying voltage VPP. For paging amplifying voltage VPP through the bipolar transistor 26 secondary anchor point 24 should be isolated from the substrate 28 of P-type. Otherwise, the voltage of the swap, which is charged secondary anchor point 24, is discharged through the substrate 28. The specialist will understand the necessity of forming a bipolar transistor within the N-pocket 30 to prevent the discharge of pre-supply voltage.

Let us now describe the reasons why secondary anchor point 24 is normally connected to the n+ layer 28 within the N-pocket 30 and the p+ layer 40 within the P-pocket 32.

If the secondary anchor point 24 is not permitted to file pre-supply voltage to the N-pocket 30 through the n+ layer 38, that is, if the booster is operating. Accordingly, high voltage, filed on the P-pocket 32, flows down to the N-pocket 30. Then n+ layer 42 of P-pocket 32 is not pokachivaetsya to the desired level. Therefore, a high voltage must be supplied from the N-pocket 30. To overcome this situation it is desirable to feed an anchor point 24 was connected with the n+ layer 38 within the N-pocket 30. Meanwhile, it is desirable that the substrate 28 of P-type was connected to voltage GND or the substrate voltage VBB to prevent the P-N forward bias. If formed of the bipolar transistor 26 with the above trenckmann structure, then the current change, even when increasing the amplifying voltage VPP, thereby minimizing time paging to podtachivaniya amplifying voltage VPP to a desired high voltage. Because of this increases the efficiency of paging and guaranteed performance amplifying circuit voltage.

Fig. 4 shows one embodiment of the amplifying circuit voltage generated in accordance with Fig. 2 and 3. The amplification circuit voltage according to Fig. 4 shows the circuit design of the swap charge. The amplification circuit voltage performs the dual operation handouts in response to a change in logic level of the OSC, produced by a generator (not shown). The first inverter 46 has an output connected to the input junction point 44. The first charge capacitor 48, included both conclusions between the first inverter 46 and the first pumping node point 50, swaps the first pumping node 50 in response to the voltage level of the output signal of the first inverter 46. The first transistor 52 preparada prajarajyam first pumping node 50 to the voltage level of VCC-Vth. The first bipolar transistor 54 NPN transistor with its base and collector commonly connected to the first pumping node point 50, and the emitter - to reinforcing anchor point 72 to generate an amplifying voltage VPP. The second inverter 60 its input connected to the input nodal point 44, and the third inverter 62 input connected to the output of the second inverter 60. The second charge capacitor 64, the two conclusions is connected between the third inverter 62 and the second secondary anchor point 66, swaps the second pumping node 66 in response to the voltage level of the output signal of the third inverter 62. The second transistor 68 recharging prajarajyam second secondary anchor point 66 to the voltage level of VCC-Vtn. The second is Slavoj point 66, and the emitter - to reinforcing anchor point 72. The third transistor 56 preparada with the channel connected between the output of the supply voltage VCC and the first pumping node point 50, and a gate connected to the second pumping node point 66, prajarajyam first pumping node 50 to the voltage level VCC. The fourth transistor 58 preparada with the channel connected between the second secondary anchor point 66 and the output of the supply voltage VCC, and a gate connected to the first pumping node point 50, prajarajyam second secondary anchor point 66 to the level of the supply voltage VCC. The structure according to Fig. 4 has the feature that the chain swap charge uses a bipolar transistor as the transmitting transistor.

Next is discussed the operation of the circuit of Fig. 4. After powering the circuit, when the circuit gain of the voltage in Fig. 4 is in a locked state by maintaining the amplifying voltage VPP to a desired level or before the enabled chip swapping anchor points 50 and 66 prezerajte to the voltage level of VCC-Vtn by using the operation preparada first and second transistors 52, 68 preparada, where Vtn is the limit voltage is e VPP is reduced to below the desirable enables the amplification circuit voltage according to Fig. 4. Then the oscillating signal OSC is applied to the input nodal point 44 in the form of a rectangular signal with a constant period. Next follows a detailed description.

First, if the oscillating signal OSC is supplied to the input node 44, rises from a logically low to logically high level, the first inverter 46 produces a logical "low" level. Through the first pumping capacitor 48 is not any swap and the first pumping node point 50 maintains its level of preparada. The second and third inverters 60 and 62 produce a logically "low" and "high" levels, respectively. The second charge capacitor 64 amplifies the second pumping node 66 to the voltage level, which is twice larger than VCC - Vtn. The amplified voltage level of the second pumping anchor point 66 is transmitted through the second bipolar transistor 70 to the reinforcement anchor point 72 to increase the amplifying voltage VPP. The second bipolar transistor 70 is a device with the structure in Fig. 3. During the split operation of the second charge pumping anchor point 66 and reinforcing anchor point 72 through the second bipolar transis way the high voltage charged in the secondary anchor point 66, is transmitted reinforcing anchor point 72 at high speed, and the effect of the substrate does not occur, even though reinforcing anchor point 72 goes to a high voltage level. The emitter of the first or second bipolar transistor 54 or 70 in Fig. 4 corresponds to the n+ layer 42 within the P-pocket 32 of Fig. 3, the base of which is a p+ layer 40 within the P-pocket 32 of Fig. 3, and the collector is n+ layer 38 within the N-pocket 30 of Fig. 3. Therefore, it is easy to understand that the effect of the substrate is not detected, even though reinforcing anchor point 72 comes to high voltage. The voltage level 2 (VCC-Vtn), swapped to the second pumping node point 66, includes the channel of the third transistor 56 preparada for preparada first pumping node point 50 to the voltage level VCC.

Then, if the oscillating signal OSC is applied to the input of the junctions 44, reduced from logical high to logical "low" level, the first inverter 46 produces a logically "high" level. The first charge capacitor 48 swaps the first pumping node 60 from the previous level of preparada VCC (this level is achieved using a third of the enhanced pre-supply voltage nodal point 50 is transmitted reinforcing anchor point 72 through the first bipolar transistor 54 to increase the amplifying voltage VPP to the level of higher than the previous amplifying voltage. The first bipolar transistor 54 is also formed in the structure in Fig. 3, and the structural characteristics described with reference to Fig. 3, are supported during the split operation of the second charge pumping node point 50 and the reinforcing anchor point 72 through the first bipolar transistor 54. Therefore, the high voltage charged in the secondary anchor point 30, is transmitted to the reinforcing anchor point 72 at high speed, and prevents the effect of the substrate, caused by increased tension reinforcing anchor point 72. On the other hand, the second and third inverters 60 and 62 produce a logically "high" and "low" levels, respectively. Through the second charge capacitor 64 will not pass any of the transfer operations of the secondary anchor point 66. Level voltage 2 VCC, swapped in the first pumping node 50, includes the channel of the fourth transistor 58 preparada for preparada second secondary anchor point 66 to the level of the supply voltage VCC. Therefore, the efficiency of the next paging increases.

If the oscillating signal OSC goes again with a logically "low" ur the point 50 becomes the voltage level VCC, and then there is a paging operation. The processes are repeated until amplifying the voltage VPP will not be raised to the desired level amplifying the voltage, and by means of these processes amplifying the voltage VPP rises to the specified level.

Fig. 5 shows a graph of the rise amplifying voltage VPP arising from performance Fig. 4. As shown, the proposed invention the amplification circuit voltage has a shorter installation time for ascending amplifying voltage VPP to the desired level amplifying voltage (dual supply voltage VCC) than the conventional circuit. Obviously, these characteristics can be achieved by using the first and second bipolar transistors 54 and 70 in Fig. 4, constructed in accordance with the structure of Fig. 3.

As described above, proposed in the present invention the amplification circuit voltage raises amplifying voltage VPP to the desired level amplifying the voltage by using the chain swap charge containing bipolar transistor. Even if amplifying the voltage VPP on reinforcing the junctions increases, the efficiency gain increases, as does not change the current flowing in the about raised amplifying voltage in the conventional amplifying circuit voltage.

The previous description shows only a preferred embodiment of the present invention. Various modifications obvious to a person without going over the amount of the present invention.

1. The amplification circuit voltage for use in a semiconductor memory device comprising a generator and an input node to receive a signal generator, a first inverter, whose input is connected to the input nodal point, the first pumping capacitor connected between the first inverter and the first secondary anchor point, and the first pumping capacitor pre-charge the first pokazivaushee anchor point in response to the voltage level of the output signal of the first inverter, the first transistor preparada first pumping node points to the level of the supply voltage, characterized in that it contains the first bipolar transistor, the base and collector of which are connected together to the first pumping node point, and the emitter of which is connected to the amplifying nodal point for generating an amplifying voltage higher than the supply voltage, the second inverter, whose input is connected to the input nodal point, the third inverter, the third control inverter and the second secondary anchor point, and the second charge capacitor pre-charge the second pumping node in response to the voltage level of the output signal of the third inverter, the second transistor preparada second secondary anchor point to the level of the supply voltage and the second bipolar transistor, the base and collector of which are connected together to the second pumping node point, and the emitter of which is connected to the reinforcement anchor point.

2. The amplification circuit voltage under item 1, characterized in that it further includes a third transistor preparada, the channel of which is connected between the first pumping node point and the terminal voltage, and the gate of which is connected to the second pumping node point, the third transistor preparada pre-charges the first charge node to the level equal to the full supply voltage, and the fourth transistor preparada, the channel of which is connected between the second secondary anchor point and the terminal voltage, and the gate of which is connected to the first pumping node point, and the fourth transistor preparada pre-charges the second pumping node todaydate fact, the signal generator has a rectangular shape constant period.

4. The amplification circuit voltage under item 1, characterized in that the first and second bipolar transistors are bipolar transmitting transistors.

 

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