Microcomputer with advanced support tools

 

(57) Abstract:

The invention relates to computing. The technical result consists in increasing the efficiency of testing the operation of the processor core. The processing unit contains an integrated circuit that has a processor core and the layout. The processor core may execute software commands using either the clock signal of the system, either the clock signal verification. Clock selection bits inside software commands for the test mode indicates the clock signal should be used, and the device clock select selects the specified clock signal and sends it to the processor core. 2 C. and 7 C.p. f-crystals, 2 Il.

The invention relates to a device for data validation. In particular this invention relates to the technical inspection data.

It is known that for technical maintenance of microprocessor based system with debugging features that allow the user to poll the status of the processor core. Such test systems allow you to isolate the core from other parts of the processing unit, and through the impact on the core processor when systems, as integrated circuit AMD 29200, you let the company Advanced Micro Devices, these debug commands are not loaded into the processor core through a conventional bus command/data. These debug commands sequentially loaded through the layout type-JTAG and then in expanded form is transmitted to the bus command/data. Serial for the load command in the layout is controlled by the clock signal verification, consistent with the external device, which receives serial commands. Loaded this way commands are executed at a speed much less than usual, for example, for a 32-bit command 32 clock cycle checks for boot commands before the clock signal checks can be sent to the kernel that it has executed the command.

In one aspect, a device for processing data containing core processor running software commands, the means for supplying the clock signal of the system in the processor core, means for supplying a clock signal validation in the processor core, the picker clock signal to select between a clock signal of the system, which controls the operation of processor cores and a clock signal validation panel the Ala of the system during the normal operation mode and the clock signal validation when downloading software commands during the test mode, moreover, the selector clock signal in response to one or more bits select the clock signal within the software team, performs during the test mode selecting either the clock signal of the check, or the clock signal of the system to control the processor core when executing this software commands.

This feature selection clock signal allows the processor core to perform once loaded commands in accordance with a valid clock signal system that will be used during normal operation. Thus, it is possible to make more realistic assessments of the processor core.

In a preferred variant of the invention contains at least one auxiliary circuit associated with the processor core and driven by the clock signal of the system, and the picker clock signal is for selecting the clock signal of the system during the test mode to execute software commands using the auxiliary circuit.

The invention provides vital capacity of the device to check on the status of auxiliary circuits associated with the processor core as the core I signal verification but the support circuitry of this type that are used with the CPU cores, does not have this ability (for example, DRAM requires constant updating at a clock frequency of the system). In General, the operation of the processor core with its auxiliary circuits require precise alignment and less prone to deviation from the clock frequency of the system, for example, data must be synchronized with the core and with the auxiliary circuit using the clock signal.

The invention allows to load commands, using the clock signal verification and switch to run these commands clock signal of the system. This raises the possibility of using the analysis of validation that can be done in this way.

As indicated above, the support circuitry associated with the processor core, can take various forms. However, the invention is suitable for systems in which the auxiliary circuit includes circuit memory and coprocessors. Such auxiliary circuits can be fabricated on the same integrated circuit, where the processor core, so the analysis of the interaction between these circuits and the processor core will be very difficult to implement droppedout in the core software team,

serves the clock signal of the system in the processor core,

serves the clock signal validation in the processor core, and

choose between a clock signal of the system, controls the operation of the processor core, and a clock signal validation, controls the operation of the processor core, and

choose the clock signal of the system during normal operation and selects the clock signal validation when downloading software commands during the test mode, one or more bits select the clock signal within a software team perform during the test mode managed a choice of either the clock signal of the check, or the clock signal of the system to control the processor core when executing this software commands.

In a preferred embodiment, the method is fed through a command pipeline software commands to the processor core, take in the selection of the clock signal to one or more bits select the clock signal from the cascade command pipeline, which retain the following command intended for execution by the processor core.

Microprocessors with high performance include command pipelines in order to increase the speed of the signal together with its attached program teams so to make a smooth change of the clock signal, when it is necessary.

Every software team during the test mode can be downloaded from the debug control system in various ways, for example, a parallel manner through the transmitting bus. However, it is a particular advantage for a system in which to appeal to the processor core during the scan mode sequentially loaded under control of the clock signal test each software command that includes one or more bits select the clock signal.

Serial download software commands during the test mode reduces the number of pins on the device, thereby simplifying the design.

In preferred embodiments, progressive download is advantageous to provide such a layout in which software commands sequentially load during the test mode.

The layout can be used for other functions, such as signal acquisition and application control action during the hardware test. Thus, the layout can be made such that it performs more than one function, thus R is ora clock signal will have the value as is the normal mode uses the clock signal of the system. Accordingly, in a preferred embodiment, during normal operation each software command loaded in parallel from the program memory, one or more bits select the clock signal separately added to software commands read from the program memory.

Adding bits select the clock signal after downloading the software commands means that the memory storing program commands for use in normal operation, there is no need to save bits select the clock signal that are redundant, since they have the same value for the same software commands in normal mode. In this case it is better used storage capacity of the program memory.

In Fig. 1 shows an integrated circuit having a processor core, operating in normal mode and in test mode according to the invention; Fig. 2 - the clock signals used in the claimed device according to the invention.

Integrated circuit 2 (Fig. 1) has a core 4.

Auxiliary circuit in the form of dynamic storage usteristrasse circuit is provided 10 scan type JTAG.

The clock signal system MC1k and the clock signal validation DC1k fed to the clock input of the multiplexer 12, which switches either under the influence of an external control signal Cnt, or an internal control signal generated by the clock 14 clock pulses. On the coprocessor 8 and DRAM 6 continuously served the clock signals of the system MC1k.

Software commands are issued in the core 4 processor through a command pipeline 16. Team conveyor 16 is filled via a multiplexer software commands 18, which selects software command or from the bus command and data 20, or from scanner 10. The output of multiplexer 18 software commands directly connected with the core 4 processor with regard to the status bus command and data 20, which also serves to transfer data words, passing directly to and from cores 4 processor without passing through a command pipeline 16. The multiplexer 18 software command switches through the logic circuit 22 of the control test, which is used to select software commands sequentially loaded in scheme 10 scanner, which is preferable in test mode software commands from the bus 20, the command and data for use by external controller debug (not shown).

The core 4 processor works by using what is usually considered as a set of 32-bit commands. 32-bit software commands are converted by adding S bits select the clock signal to one end of a software team. This exercise 33-domestic software commands. S bits select the clock signal used to transfer the flag, and software command, to which it is linked will be performed using the clock signal of the system MC1k or the clock signal validation DC1k. S bits select the clock signal is routed from the output of the last cascade command of the conveyor 16 in the core 4 processor, where it enters the synchronizer 14. The synchronizer 14 affects the reception of bits of the clock selection signal indicating that the clock signal of the system will be used to switch the clock of the multiplexer 12 in the clock system MC1k when you receive the first current pulse of a clock signal of the system. The synchronizer 14 serves to prevent flow in the core 4 processor pulse the clock signal of the system, which is not trustworthy to act (for example, the leading edge of the clock signal asynchronous system, appearing shortly after the decline of the clock signal validation D loaded in scheme 10 sweep. 33 cell circuit 10 scanner are used to store one full software commands (S-bit and 32-bit command), which, when fully loaded, in parallel, switched through the multiplexer 18 software command to the command of the conveyor 16. When the command reaches the command pipeline that are in the ready state, it's bits select the clock signal is used to control a clock multiplexer 12, which selects either the clock signal system MC1k, or the clock signal validation DC1k to provide the necessary impetus to complete this software teams inside the 4 cores of the processor.

In the case of a software command that causes or DRAM 6, or co-processor 8 uses the clock signal of the system MC1k. For example, in the case of memory access DRAM 6, the DRAM must be constantly updated and can be accessed only at certain intervals of time inside the update loop. Accordingly, the same clock signal should be used for cores 4 processor and DRAM 6 to such a memory access can be had to properly synchronize.

In Fig. 2 on the top row depicts the shift clock signal ShC1k, which is used to managed the testing team is loaded into the circuit 10 of the scanner. After the software team is loaded, it goes to command the conveyor 16, as all teams move along the command line. Command of the conveyor 16, you must perform the core 4 processor and, accordingly, either the clock signal validation DC1k, or the clock signal of the system MC1k should be selected depending on bits select the clock signal.

In the case of software commands that will be executed clock signal validation DC1k, the clock signal checking is the output of the external control device and sent to the core 4 processor through the clock multiplexer 12. This is shown in the second row of Fig. 2.

In the case of software commands that will be executed clock signal MC1k must be selected corresponding pulse of clock signal system MC1k. The synchronizer 14 controls the clock signal system MC1k following the receipt of the corresponding S bits select the clock signal, and identifies the first right impulse clock systems that can be used, and switches the clock multiplexer 12 to send it to the core 4 processor. In the depicted case, the first pulse of the clock signal is e after the previous pulse of the clock signal and is therefore not suitable for use.

1. Data processing method, comprising the following operations: served in the processor core software team, serves the clock signal of the system in the core and serves the clock signal verification core processor and choose between a clock signal of the system, controls the operation of the processor core, and a clock signal validation, controls the operation of the processor core, wherein the select clock signal of the system during normal operation and selects the clock signal validation when downloading software commands during the test mode, one or more bits select the clock signal within a software team perform during the test mode managed a choice of either the clock signal of the check, or the clock signal of the system to control the processor core when executing this software commands.

2. The method according to p. 1, characterized in that it serves through a command pipeline software commands to the processor core, take in the selection of the clock signal to one or more bits select the clock signal from the cascade command pipeline, which retain the following command intended for execution by the processor core.

3. The method according to p. 1 or 2, otlichayushchimsya command including one or more bits select the clock signal, under control of the clock signal of the scan.

4. The method according to p. 3, wherein the software instructions sequentially load during the test mode in the layout.

5. The method according to any of paragraphs.1 to 4, characterized in that during normal operation each software command loaded in parallel from the program memory, one or more bits select the clock signal separately added to software commands read from the program memory.

6. A device for processing data containing core processor running software commands, the means for supplying the clock signal of the system in the processor core, means for supplying a clock signal validation in the processor core, the picker clock signal to select between a clock signal of the system, controls the operation of the processor core, and a clock signal validation, controls the operation of the processor core, wherein the selector clock signal is for selecting the clock signal of the system during the normal operation mode and the clock signal validation when downloading software commands in presignal within the software team, performs during the test mode selecting either the clock signal of the check, or the clock signal of the system to control the processor core when executing this software commands.

7. The device according to p. 6, characterized in that it contains at least one auxiliary circuit associated with the processor core and driven by the clock signal of the system, and the picker clock signal is for selecting the clock signal of the system during the test mode to execute software commands using the auxiliary circuit.

8. The device according to p. 7, characterized in that the auxiliary schema contains the schema memory.

9. The device according to p. 7, characterized in that the auxiliary circuit includes a coprocessor.

 

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