The transport interface processor and video recorder/playback for digital television system

 

(57) Abstract:

The transmitted signal of the high definition television presents the flow of data in packet form in a sequence of data fields with uneven speed sequence data due to the inequality of intervals containing auxiliary information between the data. Each data field is preceded by an auxiliary segment synchronization field followed by 312 data segments in packet form, each of which contains appropriate supporting information. In the transmitter, the transport processor generates data packets with appropriate headers and performs continuous processing with a constant uniform data rate, at the same time feeding the flow of data in packet form in a block, which generates a serial data fields by inserting into the data stream inserted into the stream of auxiliary information that does not contain data. The technical result of the invention is that the transport processor operates with a constant uniform velocity-distance data without converting the original structure of the data fields to meet the requirements of the processing unit of the data field. This is in response to a character clock signal 3/8 ARTICLE, and also due to a predetermined fill level of the buffer. The recorder/playback video receives packetized data stream from the transport processor with a constant uniform velocity-distance data and outputs the data stream with a constant uniform speed to the interface block/buffer. The corresponding transport processor in the receiver works in conjunction with the processor data fields and also carries out continuous processing with a constant uniform data rate. The recorder/playback video takes a stream of data with a constant uniform speed of the interface/ buffer after removal of the auxiliary information, and outputs the data stream with a constant uniform speed in the transport decoder. The technical result - the relief and improvement of the recording/playback in the processing stream structured in the form of data fields in the system high definition TV. 4 C. and 5 C.p. f-crystals, 34 ill.

The invention relates to the field of digital signal processing. In particular, the invention relates to a system designed to facilitate recording/playback in the processing stream structured in the form of data fields, CLASS="ptx2">

Recent developments in the field of video processing has led to the creation of systems for processing and transmitting digital television signals high-resolution (high-definition). One such system is described in U.S. patent N 5168356. In this system, the transport processor is a stream of data, which consists of code words in the standard that is compatible with the known compression standard MPEG. The main function of the transport processor is packing data consisting of code words of variable length, with getting Packed data words. Collectively Packed data words, which is called the data packet or cell data, preceded by a header that contains, among other information, information that identifies the corresponding data words. Thus, at the output of the transport processor generates a packetized stream of data consisting of a sequence of transport packets. The use of the transport packets increases the possibility of re-synchronization and recovery of the signal in the receiver, for example, after a signal failure which may occur due to disturbances in the transmission channel. This is achieved through the header data, with which the receiver when potetial terrestrial television broadcasting high definition the recently proposed as a system of high definition TV Large Alliance in the United States, uses to transmit packetized data stream with a predetermined structure of the data field format digital transmission with partially suppressed sideband. TV system high-resolution Large Alliance is a proposed standard for the transmission, which is now under consideration in the US the Federal communications Commission in its Advisory Committee on advanced television. System description high definition TV Large Alliance, as it was directed to the Technical subgroup of the Advisory Committee on advanced television on February 22, 1994 (draft document), published in the Proceedings of the National Association of broadcasters 1994, 48th Annual Broadcast Engineering Conference Proceedings, March 20-24, 1994.

In the system of the Great Alliance data is organized into a sequence of data fields. Each structure field includes 313 segments: synchronization segment field (which contains no useful information), followed by 312 data segments. Each data segment includes a data component and a direct component error correction (VEC). Each with the length of 188 bytes to the processor of the transmission, which provides various encoding functions for each package with the formation of the output character segments for their submission to the output transmission channel. Each byte contains a predetermined number of characters, for example, 4 characters. The data packets contain data in accordance with a compression standard MPEG-2, developed by the International organization for standardization (Group of experts on moving images). The transport processor generates only data packets to processor transfer, which adds an auxiliary component detection and error correction for forward error correction in each segment and sub segment sync field at the beginning of each data field, i.e., between each group of segments of data fields. For these operations, the data flow must be regulated, as will be seen hereinafter, accessories direct error correction and auxiliary segment sync field take place at different times and have different duration.

The packages are separated by intervals that enable the transport processor to insert into the data stream auxiliary data required for each segment and field of greater length, which does not contain useful data, as other packages, the flow of the compressed data must be interrupted and delayed for a time equal to the interval of the segment. The data stream is created taking into account the need to interrupt and insert him in the auxiliary information of different duration (data direct error correction or synchronization field), is illustrated in Fig. 3 . This data flow contains the intervals between synchronization field packet length is 312 bytes plus intervals direct error correction, as will be discussed in the future.

The essence of the invention.

The authors found that interrupted the flow of data, as described above, not only reduces undesirable speed data, but also leads to the formation between the data packets of unequal intervals. The existence of such unequal intervals between packets complicates the signal processing.

In particular, the authors found that interrupted the flow of data is undesirable increases the requirements for the interface between the transport processor and the processor of the transmission in the transmitter, particularly in relation to data synchronization, as well as between any of the systems for recording and playback packaged sweat the nd apparatus or equipment of the consumer. To meet the synchronization requirements of the MPEG standard, any system of records should without distortion to reproduce the synchronization packet, including any uneven gaps between packets, which, if they exist, must be inserted between packets. These requirements significantly increase the complexity of the circuits required as an interface for the recording system. In addition, any such gap, formed by the processing for transmission, should be kept in the demodulator of the receiver.

Preferably the present invention is used in a system designed for processing packetized data stream representing a predetermined sequential patterns data fields. The system according to the invention eliminates the need for alignment of structures of data fields that can be characterized by different velocity-distance data due to differences in type auxiliary (service), i.e. does not contain data, information of different duration, such as what is used in the above-described system of high definition TV Large Alliance.

In the transmitter, the transport processor (e.g., formine data without interruption in the system, which inserts the auxiliary information does not contain data of different duration in the data stream with the formation of the predetermined sequential patterns data fields. Preferably, the transport processor runs at such a constant uniform speed data without the need of modifying the predetermined initial structure of the data field. According to the invention in the transmitter in the path of the data stream coming from a constant uniform speed from the output of the transport processor, the device recording/playback.

The corresponding transport processor/decoder in the receiver likewise has a continuous processing with a constant uniform data rate. In the input path of the transport processor/decoder, where the data stream has a constant uniform speed, installed video recorder/playback.

In the described embodiment, the transmitter according to the present invention for the supply of data bytes in the buffer circuit interface with uniform speed data transport processor runs at a constant uniform speed data without interruption, PCT, buffer writes data and reads the data with uneven speed with issuing them in the scheme of formation of the field data. The scheme of formation of the field works with uneven speed sequence data and, in response to the data containing the bytes, and the auxiliary information does not contain data, produces a sequence of output structures of the character fields. The scheme of formation of the field data requests data from an uneven speed. The interface circuit converts this query into a query with a constant velocity-distance data transport processor. In the signal path between the transport processor and interface scheme is video recorder/playback.

In the described embodiment, the receiver according to the present invention the received stream of symbols is characterized by the sequential structure of the data fields. The processing device data field processes adopted the structure of the field of character data with uneven speed and generates output data coming from the uneven speed. Diagram of front-end buffer responds to the clock signal 3/8 ARTICLE reads and converts these data into the output stream of bytes of data in MPEG format, characterized by Kee is which in response to the clock signal 3/8 ARTICLE, carries out continuous processing with a constant uniform velocity-distance data. In the signal path between the interface circuit and the transport processor is video recorder/playback.

A brief description of the drawings.

In Fig. 1 illustrates the sequential structure of the data fields including a segment sync and data,

in Fig. 2 depicts a block diagram illustrating in General terms the device for processing packetized data stream,

in Fig. 3 shows the packetized data stream in which the data packets are uneven auxiliary intervals

in Fig. 4 depicts a block diagram of the encoder in the transmitter, which includes a scheme buffer/interface and schema structuring data fields, suitable for use with recording devices according to the invention,

in Fig. 5 illustrates the spectrum of a television signal, which can be used to transfer output data generated by the system shown in Fig. 4; it is shown in comparison with the spectrum of a normal television signal in the NTSC system,

in Fig. 6-16 shows the signals hrenovo in the receiver decoder, which includes a processing device of the data fields in the primary frequency band and the scheme buffer/interface suitable for use with recording devices according to the invention, for submission to the transport processor output,

in Fig. 18-27 describes the signals that characterize the system operation of the receiver shown in Fig. 17,

in Fig. 28 and 29 depicts the nodes of the system depicted in Fig. 4 and 17, respectively,

in Fig. 30-32 depict signals, which are useful for understanding the operation of the system, made according to the invention,

in Fig. 33 and 34 are illustrated device, is shown in Fig. 4 and 17, respectively, together with the device recording/playback in accordance with the invention.

Detailed description of the invention.

In Fig. 1 shows the structure of a data field television systems high resolution Large Alliance in the United States for use in a system for processing packetized data stream. The output stream of character data representing the structure of data fields, is generated by the processor of the transmission in response to the packet input from the previous transport processor. The processor transfer and transport processor will describe the St does not contain useful data), prior to the group of segments of data fields, each of which has a corresponding component synchronization. Each segment of the data field includes a component package data from 187 bytes, component, synchronization of one byte before each data segment and component direct error correction after the data. Each segment corresponds to the spacing "Y" defines the interval of the ban data between each data package. The transport processor generates packets input data of 188 bytes plus the segment synchronization processor transfer. The processor transmission adds auxiliary information relating to the coding for forward error correction and synchronization fields, and generates output segments in symbolic form for transmission to the output channel.

Synchronization component corresponding to each segment, and a synchronization component fields facilitate the establishment of synchronization symbols and packages and phase-lock loop in the receiver in conditions of excessive noise and interference. A four-character synchronization component is a binary (2-level) in order to improve the reliability of recovery packets and synchronization signals and represents a signal that is n is noise and interference. The synchronization symbols are not encoded according to the method of reed-Solomon or using the lattice code and are not subject to alternation. Synchronization component of the field may contain a pseudo-random sequence and is used for several purposes. It provides a means for determining the beginning of each data field, and can also be used by the adaptive equalizer in the receiver, as a reference training sequence to remove intersymbol and other distortions. In addition, it provides a means by which the receiver can determine whether or not to use the noise filter, and can be used for diagnostic purposes, for example for measuring the signal-to-noise and frequency characteristics of the channel. In addition, the synchronization component can be used in schemes for tracking phase in the receiver to determine the parameters in the control loop phase. As component synchronization, synchronization component of the field is not encoded by the ECC or cage code and not punctuated. In this example, the field data does not necessarily correspond to the alternating fields of the image, which constitute the image frame in the television signal in the NTSC standard.

In Fig. 3 shows the flow of data packets in accordance with the structure of the data fields shown in Fig. 1. Each data field has 312 segments, each of which includes synchronization components, data and direct error correction. More specifically, each segment of the data field contains the interval that covers the 188 bytes of data including the synchronization signal, ("packet bytes"), and the interval that covers the 20 bytes of code direct error correction. In each segment 188 data bytes correspond 188 intervals (periods) of the clock signal, and every 20 bytes of codes direct error correction correspond to 20 intervals (periods) of the clock signal. When an insert segment sync field transmission of data segments/direct error correction should be detained at 228 periods of the clock signal that corresponds to the synchronization interval of the segment (i.e., 20+188+20 periods of the clock signal). The segment synchronization ponich cause undesirable unequal intervals or gaps between packets, as shown in Fig. 3. This interrupted the flow of data and unequal intervals between packages very complicate data management and increase hardware requirements related to the interface between the transport processor and the processor of the transmission as in the receiver and transmitter, as well as reduce the rate of repetition of the data. Moreover, when the playback of recorded materials is difficult to achieve the synchronization patterns of the data fields. Unequal intervals between packages very complicate the task of recording the flow of packet data on the Studio equipment or the equipment of the consumer, since the unequal intervals between packets should be stored where they are, i.e., the recording equipment shall faithfully reproduce the synchronization packet MPEG. In addition, unequal intervals should be preserved in the output signal produced by the demodulator in the receiver.

Describes the problems caused by unequal intervals between packets and associated with irregular auxiliary data are considered and resolved by the system, made according to the present invention. In the described system, the transport processor processes the data packets with a constant is blazei data. This clock signal also controls the operation of the unit buffer/interface located between the transport processor and device level transfer, which processes the data in accordance with predetermined structure of the data field. The advantage of this system is that to achieve the desired operation with a constant uniform velocity-distance data is no need to modify the original structure of the data field. In addition, there is no impact on such parameters as the speed of the repetition symbols, interleaving segments, and synchronization components and coding with error correction according to the method of reed-Solomon.

In the system of the transmitter (Fig. 4) according to the present invention, the transport processor 14 operates with a constant uniform velocity-distance data without interruption and gives the byte data in the MPEG standard with uniform velocity-distance data in block 16, the buffer interface. The transmission path of the byte data in the MPEG standard according to the invention includes a video recorder/playback, as will be shown in the discussion of Fig. 33. The interface 16 generates byte data with uneven speed in block 17 the em byte data and support information does not contain data (the data synchronization field and direct error correction), produces a sequence of structures of output fields of the characters. Unit 17 requests the data with non-uniform speed by a signal Request Service Data Field. The interface block 16 converts this request into a request signal with uniform velocity-distance data (Request Package For Transportation), served in the transport processor 14.

More specifically, the transport processor 14 applies to the transport system level and unit 17 refers to the system level transmission (which includes also the output processor 18), which is separated from the transport layer interface 16. The data source 12 includes a data compression scheme that is compatible with the MPEG standard, and outputs the byte data in the MPEG-2 transport processor 14. The transport processor 14 packs the bytes of the MPEG format in the data words of a fixed length, which in the end are grouped into data packets of a fixed length (188 bytes). Each packet is preceded by a header containing explanatory information about the source program, the service type, and other information describing the payload in the corresponding package and related. In addition to the ATA MPEG. The processor 10 performs transmission operations, which include the input buffering, encoding for direct detection/error correction, inserting synchronization signal field, lattice coding for improving the signal-to-noise interleaving to reduce the inuence of errors that occur during transmission of the data packet, and character conversion.

Unit 17 performs the function of forming field data, while the input data packets are formed in the structure of the data fields including data and synchronization components of the field and direct error correction, as described previously. Data packets from the interface block 16 block 17 is followed up with a constant uniform intervals between packets so that the data fields are generated by the block 17 "without joints and without interrupting the data flow. The transmission system of Fig. 4 operates in response to a character clock pulses (ST) and clock pulses derived on their basis, as will be described below. A suitable frequency character of clock pulses equal 10,762237 MHz.

The described system according to the present invention allows the transport processor to operate at a uniform rate of sequence data without modifying the original stryrofoam uniform data flow 313-segment field. Moreover, there is no need to interrupt the flow of data to be inserted between the data fields of the auxiliary synchronization information field.

The system of the transmitter depicted in Fig. 4, uses heartbeats 1/4 CT and 3/8 CT, where CT is a character clock pulses of the system. Choice for signal processing clock signal is 1/4 of the ARTICLE, as will be shown below, due to the fact that one byte (8 bits) contains 4 characters, with 2 bits per symbol. The clock signal 3/8 CT is preferred for systems with 8-position modulation with partial suppression of the sidebar, while the clock signal 3/4 ART also are within the scope of the present invention, preferred for faster systems with 16-position modulation with partial suppression of the sidebar. In the system, which will be described below, the block contains 16 between the output of the transport processor 14 and the input unit 17 the formation of the field data buffer 46 FIFO type. Packages byte data is read from the transport processor 14 and stored in the buffer 46 in response to the clock pulses 3/8 ARTICLE, and from the buffer 46, the data packets are read and fed to the encoder 17 in response to the clock pulses 1/4 CT. Both of these clock pulse preferably vyrabatyvayutsya work as a transport processor 14, and buffer 46 so that transport data between the processor and the buffer are transmitted synchronously. As will be described below, similar requirements apply to the receiver.

In Fig. 6-9 character heartbeats ARTICLE (Fig. 6) and obtained from them a synchronous clock pulses 1/4 CT (Fig. 7) is generated by circuit 40 synchronization control, for example, by a microprocessor, in block 17. The circuit 40 also generates a signal to Request Service Data Field (Fig. 10), which is synchronized with a symbol clock pulse ARTICLE, so as to generate a signal to Request Service Data Field used heartbeats 1/4 CT. The generator 42 to the clock signal in block 16 generates clock pulses 3/8 ARTICLE (Fig. 8), which is synchronized with a clock pulse ST and the clock pulses 1/4 CT of circuit 40 synchronization. In Fig. 9 (shown only for reference) shows the pulse length (1 byte associated with the emergence of single-byte synchronizing pulse as the first byte at the beginning of each data packet.

Heartbeats 3/8 ARTICLE are generated by counting clock pulses ARTICLE. Unit 42 generates three output pulse for every eight clock pulses ARTICLE. In Fig. 7 and 8 illustrate one possible, zootoxin is it any combination of 3 clock pulses within the time interval of 8 clock pulses, however, between the three pulses and clock pulses 1/4 of the ARTICLE should be fixed phase relationship, and it is the same ratio should be maintained between clock pulses 1/4 ST and the clock pulses 3/8 ARTICLE in the receiver and the transmitter. Illustrated on Fig. 8 structure of clock pulses 3/8 ARTICLE is preferable, since this signal is easy to convert and align with byte synchronization (which is easy to detect at the beginning of each package), and can be easily replicated in the receiver. Similar considerations apply to the use of any six of the eight character clock pulses for generating clock pulses 3/4 ARTICLE for a signal with 16-position modulation with partial suppression of the sidebar. Illustrated shows the relationship between clock pulses is carried out in the circuit 40 controls the timing by reset the cutting edge of clock pulses 1/4 of the ARTICLE, resulting from the buffer 46 is given byte synchronization package. The count of characters counted from 0 to 7, where 0 is synchronized with the byte synchronization packet that is issued from the buffer 46. Can be used any three of the eight counts of the counter clock pulses ARTICLE, but p is it provides the ability to generate patterns of the data field, containing 312 data segments and one segment sync field. In response to the clock pulses 1/4 ST, signal Request Service Data Field (Fig. 10, 13) of the circuit 40 has a high logic level in a period of 188 bytes and a logic low for a period of 20 bytes. The signal Request Service Data Field of the controller 40 (Fig. 10) has a non-uniform intervals between packets. Shows the portion of the field data, in particular the two last segment 311 and 312 data of one field of the data segment 313 synchronization field before the next data field and the first data segment of the next data field. This signal contains the intervals permissions data, when data is requested (each contains 188 bytes of data synchronized with 188 clock pulses 1/4 ST), intervals deny data (each contains 20 clock pulses 1/4 ST) when the data flow should be added direct error correction, or intervals of length 228 of clock pulses 1/4 ST, between fields when data should be supplemented with information regarding the synchronization field. This signal is an Autonomous input signal for the circuit 44 of the control system in block 16.

Scheme 44 management responds to the clock pulses 3/8 ARTICLE and the beat is. 1. This signal requests a 188-byte data packet from the transport processor 14 whenever 313-th clock pulse 1/4 CT. For the formation of a uniform rate of sequence data and data flow without interrupting the signal Request Packet has a constant uniform intervals between requests package. Constant uniform intervals of length 125 clock pulses 3/8 ARTICLE between requests package facilitate the insertion unit 17 of auxiliary data, such as information about direct error correction and synchronization of the field, between fields of data in the data flow without joints and interrupts to create patterns of data fields, as will be explained subsequently.

This invention relates to a data flow having a field structure with 313 segments on the field, including the field synchronization segment, followed by 312 segments of data fields. In this context, the described system will work with the clock pulses, the repetition frequency which is a multiple of the clock pulses 3/8 ARTICLE, for example with a faster clock pulses, including heartbeats 3/4 ST, 3/2 ARTICLE and ARTICLE 3, in schemes, for example, an 8-position modulation with partial suppression of the sidebar or 16-position modulation part is that the discussion will become clear as well the principles of the present invention are applicable to other types of structures of the data fields.

The waveform shown in Fig. 10, is a constant for the described variant with the structure of data fields, including 313 segments. The structure of the signal, shown in Fig. 11, may vary depending on several factors as follows. Fig. 30 corresponds to Fig. 11, which depicts the signal Request Package with uniform velocity-distance data and sent from the circuit 44 in the transport processor 14 in response to the clock pulses 3/8 ARTICLE 8-position modulation with partial suppression of the sidebar. If the 8-position modulation with partial suppression of the sideband used heartbeats 3/4 ARTICLE that goes with twice the frequency, the waveform Request Packet sent to the transport processor 14 will be such as shown in Fig. 31. Since the size of each data packet is fixed and equal to 188 bytes, the interval of the data packet remains unchanged and equal to 188 clock pulses 3/4 CT. However, the intervals of the ban data between packages significantly increase and reach 438 clock pulses 3/4 CT. In this example, the number of clock pulses in each segment of wotro is mulsow 3/4 CT. In other words: 626 clock pulses in segment 188 of clock pulses (fixed value) = 438 clock pulses.

Although the number of bytes in the segment has increased, the structure of the data packet has not changed. The structure of the data fields have not changed, because each data field still contains 312 segments, each of which contains 188-byte data packet, in front of which is a segment synchronization field. Similar comments apply to the synchronization pulses fold greater frequency, for example 3/2 ARTICLE or ARTICLE 3, under which the number of clock pulses in the interval between data packets increases. It was determined that the frequency of clock pulses 3/8 ARTICLE is the minimum frequency for synchronization 313 bytes in the segment in the data field of 313 segments.

In Fig. 32 illustrates the use of clock pulses 3/8 ARTICLE that have a high repetition rate, in a system with 16-position modulation with partial suppression of the sidebar. In the case of a 16-position modulation with partial suppression of the sideband frequency of the clock pulses is doubled, as compared with the system with an 8-position modulation with partial suppression of bacow and the interval of the ban data between the data length of 125 clock pulses are the same as in the case of an 8 - position modulation with partial suppression of the sidebar, because of the connection between the frequency of the clock pulses and the data rate with a corresponding modulation type. Lower frequency clock pulses 3/8 ARTICLE at a lower speed data for 8-position modulation with partial suppression of the sidebar is the same, because of the higher frequency clock pulses 3/4 ST at higher speed data for the 16-position modulation with partial suppression of the sidebar. It can be shown that the desired ratio (e.g., 3/8 ST, 3/4, ARTICLE and so on) clock pulses can be obtained in accordance with the following expression that specifies the number of characters per field:

NX(188 + Y) = S(X + 1),

where X(188 + Y) and S(X + 1) - number of characters in the field;

188 + Y is the number of symbols in the data segment;

X+1 is the number of segments in the field (e.g., 313);

S is the number of characters per segment (for example, 832);

X is the number of data segments in the field (e.g., 312);

Y is the interval between the data; and

N multiplier that you want to define.

N = 8/3 in the case of clock pulses 3/8 ARTICLE at the 8-position modulation with partial suppression of the sidebar, and N is equal to 4/3 in the case of clock pulses 3/4 CT.

Data packets from the transport processor 14 (Data) are fed into the buffer 46 of the block 16. This buffer is relatively small, it is designed for multiple packages. To enable writing of data packets in the buffer 46 in response to the clock pulses records 3/8 ARTICLE (WCK), the buffer 46 also receives at its input the write-enable (WEN) signal Data is True. In addition, from the transport processor 14 in the buffer 46 is flag the Start of Packet (SOP). This flag is generated at the beginning of each data packet simultaneously with the byte synchronization, which precedes each packet. Requests to the transport processor 14 to send a data packet in block 17 via the interface block 16 not serviced until then, until the buffer 46 is not Dover 46 is carried out using a flag Filling, served on the control input of the controller 44.

188-byte data packet is placed in the buffer 46 every 188/313 periods of clock pulses 3/8 ARTICLE (Fig. 11 and 12). For the remaining 125 periods of clock pulses 3/8 ARTICLE in the buffer 46 FIFO type data recording is not performed. The arrival rate of the data input buffer 46 uniform and exactly equal to the speed of data output from the buffer 46. The speed of data output is controlled by the signal Request Packet Frame Data from the circuit 40. The signal Request Packet Frame Data and the signal Request Package for Transportation are not synchronized, but are linked through the relation between clock pulses 3/8 ARTICLE and clock pulses 1/4 CT.

The controller 44 includes logic circuit, responsive to the clock pulses 3/8 ARTICLE, the Request signal of the Packet Data Field, the flag buffer (Fig. 15) from the buffer 46 and the flag of the Start of Packet (SOP), derived from circuit 45 alignment through the buffer 46. To allow reading of data of the transport packet from the buffer in block 17 at the appropriate time, the controller 44 generates the control signal (Fig. 14) at the enable input read (REN) buffer 46. This occurs as depicted in Fig. 13-16. The signal shown on edyvane (Fig. 14) synchronized with the signal of the Request Data Packet Fields (Fig. 13). Flag the Start of a Batch, which normally appears at the beginning of each data packet, causes the controller 44 to issue a signal to the enable input of the read buffer 46 to prevent buffer read data. Specifically, the controller 44 is programmed so that in response to flag the Beginning of a Packet, it reads from the buffer 46 of 188 bytes, then stops reading in the interval signal direct error correction length of 20 bytes. This allows the circuit 50 direct error correction encoder 17 transfer to calculate information relating to direct error correction, for a package that immediately precedes the current packet stored in the buffer 46. This information related to error correction, is inserted into the data stream during the 20-byte auxiliary interval adjustment error at the end of the preceding package. As the signal Request Service Data Field (Fig. 13), and the enable signal read when he was present (Fig. 14), have a structure characterized by uneven gaps between packets needed to insert a 20-byte auxiliary information scheme 50 unit 17 and to insert the block 58 supporting information about xing the data stream.

Let us return to the description of Fig. 4. Inserting a field synchronization segment without stopping and interrupting flow is facilitated by synchronizing the read/write buffer 46 in combination with a preset fill level of the buffer. As request packets they are continuously written to the buffer 46 from the transport processor. During one period of the field data the exact number of data bytes required for the formation of the field data will be transferred from the transport processor 14 to the buffer 46. The buffer 46 is relatively small, in this example, it holds only 4 data package. Predefined fill level of the buffer is 2 data packet, but this level may be changed in accordance with the requirements of a particular system. In practice, this level should be determined so that the known data intervals and intervals of the ban data in the system buffer is not overflowed, when reading from it will be stopped for insertion into the data stream, the auxiliary information, and is not empty in the rest of the time. When reading from the buffer temporarily stopped to be inserted into the data stream supporting information (e.g., signal synchronization field), the data packets continue to be recorded in the buffer 46 by a constant is turning intervals between data packets (Fig. 11) provide buffer 46 enough time to re-fill until the read data is temporarily prohibited to insert additional information. Once in the interval ban reading auxiliary data is inserted, the data is again read from the buffer 46. During this time, the transport processor 14 is continuously sent data packets in the buffer 46, as a result, while the transport processor 14 processes the data without interrupting the flow of data flows without interruption.

When using higher frequency synchronization, for example 3/4 ST, 3/2 ARTICLE, the buffer 46 is not empty, because the intervals between packets in mode 8-position modulation with partial suppression of the sidebar is longer. This gives additional buffer time to repopulate from the transport processor.

If the flag buffer has a low logic level, indicating that the buffer 46 contains less than a predetermined number of packets, the controller 44 also cancels the permission signal read to the buffer 46. At this time, the signal Data is True of the circuit 44 (Fig. 16) is "low" (no), as read from the buffer 46 is prohibited. This citratrate field data is initiated at the beginning of the day of the transfer, and from that moment the transmission of data packets continues without a break to exit the station from work at the end of the day transfer. During this time, in those intervals when reading from the buffer 46 is prohibited, the transport processor in response to the signal Request Package for Transportation from the controller 44 continues to send data packets in the buffer 46. After a predetermined number of packets to be recorded and the condition of the buffer is satisfied, the flag state Population (Fig. 15) changes to a high logic level. In the buffer 46 will again be submitted to the enable signal read, which will allow him issuing data packets. Operation permits the read buffer is triggered by leading edge of the first interval resolution of the data, which appears once in response to execution conditions fill flag Filling will be set to the high logic level. Therefore, at time T2 the first byte (sync) packet of data is aligned with the beginning of the request packet from the Request signal of the Packet Data Field (Fig. 13) and the signal Data True (Fig. 16).

Scheme 45 alignment in Fig. 4 facilitates the above-mentioned operation, which is illustrated in Fig. 13-16. Circuit 45 shown in Fig. 28 together with the blocks 17, 42, 44 and 46, shown in Fig. 4. Scheme 45 alignment contains enabled cascaded D-three is abbokinase by applying to the input buffer 46 enable signal read (REN) from the system controller 44. The data from the buffer 46 via triggers 102 and 104 are served in the encoder 17 transfer. In response to the flag of the Start of Packet ( SOP ) ( detained case a copy of the input signal the Beginning of a Packet) from the output of the trigger 102, the controller 44 generates the enable signal to the read buffer. The Start signal is a delayed copy of signal the Start of a Batch input buffer 46.

Let us return to Fig. 4. From the output of the block 45 byte data in parallel code 8 bits and the Data signal is True (Fig. 16) are fed to corresponding inputs of a block 50 direct error correction encoder 17 transfer. Block 50 direct error correction adds 20 bytes of data direct correction of errors in the data flow within the auxiliary spacing data false intervals between each data packet in accordance with the waveform shown in Fig. 16. The flow of data from block 50 direct error correction is supplied to the Converter 52 parallel data in the serial. Unit 52 converts each byte of the 8 parallel bits in a group of four case of double-bit words, which are output sequentially. Using well-known methods, the data from block 52 encode block 54 lattice codes with rate 2/3 code with the formation on the improvement of the characteristics of the signal to noise ratio. These bits are calculated according to a predetermined algorithm, examples of which are well known to specialists in this field. The encoder 54 operates in conjunction with the block 56 generation of bits that forms the third bit in accordance with a preset algorithm.

The output of the encoder 54 lattice code is formed by a sequence of 3-bit words trellis code, and four 3-bit words are bytes. The Converter 58 converts characters each 3-bit word received at its input from the encoder 54, one output symbol and performs a temporal multiplexing of these output symbols received from the block 60 component of the synchronization field, the value of which is set in advance, with the formation of the output character stream.

According to a conversion function block 58, eight successively increasing binary values received from block 54, 000, 001, 010, ... up to 111 is converted into the following eight character levels, respectively:

-7 -5 -3 -1 +1 +3 +5 +7.

The control signals for the generator 60, the synchronization field and the inverter 58 are formed by circuit 40 synchronization control, for example a microprocessor. Circuit 40 controls the operation of the generator 60 is Aranea specified duration between adjacent data fields, that is, after each of the 312 data segments, as described above. Each segment sync field multiplexed predictable path in the data flow between groups of data fields without interrupting the data flow, as noted above in the description of the buffer 46. The multiplexer 58 also replaces the component synchronization of MPEG at the beginning of each packet to the synchronization signal segment before the final processing block 18.

an 8-level symbol data signal from the block 58 is supplied to the output processor 18, where it suppressed high-frequency carrier may be added a small pilot signal for a sustainable recovery of the carrier in the receiver in difficult reception conditions. Using known methods of signal processing, the modulator 8-position modulation with partial suppression of the sidebar in the processor 18 receives a composite signal containing lattice codes, filters and shapes the spectrum of the signal for transmission through a standard television channel with a bandwidth of 6 MHz, modulates (converts with increasing frequency) signal data carrying intermediate frequency (if) and transfers the signal to the carrier of the high frequency. In Fig. 5 the upper diagram for this example is depicted spec is Hz in the NTSC standard, which is shown in the bottom diagram.

In Fig. 17 shows a signal receiver with a partial suppression of the sidebar, made according to the invention. The demodulated stream of character data from the preprocessor 72 has the structure of data fields, which was described above, when the uneven speed of the sequence data. The processor 75 data fields related to the level of the transmission system, processes the structure of data fields, walking with an uneven speed data, and outputs data with nonuniform velocity-distance data. Scheme 84 buffer interface converts the data into a byte stream of data in the MPEG standard, coming with a constant uniform speed. This thread is processed in the transport decoder 86 which operates without interruption with a constant uniform data rate and outputs the decoded byte data to the output processor 88. The transport decoder 88 refers to the transport system level. The transmission path of the byte data in the MPEG standard according to the invention includes a video recorder/playback, as will be shown in the discussion of Fig. 34.

More specifically, the signal taken from the transmission channel is processed radiofrequency Tun is given for the if filtering and synchronous detection on the preprocessor 72, using known methods for forming a signal in the band of the modulating signal. Block 72 also includes an equalizer to compensate for amplitude and phase distortions introduced by the transmission channel. The signal symbol data output unit 72 then decoding trellis code, direct detection/correction of errors and other signal processing that is the reverse of the processing performed in the transmission system shown in Fig. 4.

Heartbeats ARTICLE and derivatives heartbeats 1/4 CT and 3/8 ARTICLE identical to the corresponding clock pulses in the transmitter. Thus, the output data stream (byte data in the MPEG standard), which is served in the transport processor/decoder 86 corresponds to the data stream (byte data in the MPEG standard) issued by the processor 14 in the system of the transmitter depicted in Fig. 4. The input character data is supplied to the block character Converter and demultiplexer 74 correspond to the signal output character data generated by the block 17 in Fig. 4. The input stream of character data component contains a synchronization field, a relatively long duration, which respectively define the neighboring pengolah data in the receiver has a non-uniform velocity-distance data. Before entering into a transport processor 86 of the receiver, this input stream of character data with nonuniform velocity-distance data is converted into an output signal of the byte data in the MPEG (scheme 84), which contains the data packets coming from uniform speed, divided evenly between packages. This data flow, the following constant uniform speed, easy handling and demultiplexing data transport decoder 86 which operates without interrupting the data flow.

More specifically, the input stream of character data in the frequency band of the modulating signal with non-uniform velocity-distance data obtained after demodulation and equalization, served in character Converter and demultiplexer 74, which carries out the operations reverse to those performed by the Converter 58, shown in Fig. 4. Unit 74 converts each character in a 3-bit word, which is using the decoder 76 lattice code working in conjunction with the block 78, decoded 2-bit word. In addition, the block 74 replaces the synchronization signal segment at the beginning of each packet segment on the synchronization signal packet MPEG. The flow character Yes testuya during the sync interval field, for example, the so-called "training sequence" for use during the previous equalizer in block 72, the information about the mode and other information. This information is extracted by the block 90 and is served in the previous schemes in accordance with the requirements of a particular system.

Group 2-bit data words from the output of decoder 76 lattice code Converter 80 serial data in parallel is converted from serial form into 8-bit (one byte) parallel form. Consecutive words from the transducer 80 is served in the block 82 detection and error correction, for example a reed-Solomon decoder. After error correction data from the block 82 is served in the block 84, a buffer/interface receiver together with the Data signal is True, the clock pulses ARTICLE and 1/4 of the ARTICLE, and also signal the Beginning of a Packet from the controller 92. Heartbeats ARTICLE and 1/4 ST synchronized and are produced by the local oscillator in the controller 92. Signal the Beginning of a Packet is generated in response to the appearance at the beginning of each packet byte synchronization. In response to signal the Start of a Batch unit 82 direct error correction generates a Data signal is True.

Block 84 buffer/interface similar blockbustery controller 120, the generator 122 clock pulses 3/8 ARTICLE and circuit 145 alignment characteristics of each of these devices are similar to the characteristics of such devices in block 16 of the transmitter depicted in Fig. 28. Buffer 100 shown in Fig. 29 is essentially the same as the buffer 46 FIFO type in block 16 of the transmitter buffer in Fig. 4, except that the clock pulses of the read and write are reversed. More specifically, the clock input write buffer 100 filed heartbeats 1/4 of the ARTICLE, and the clock input read buffer 100 filed heartbeats 3/8 ARTICLE. In Fig. 29 signal the Beginning of the Packet in the input register 110 is a buffered version of the signal the Beginning of the Packet, and signal the Start of a Batch input transport processor 86 is a delayed version of the signal the Beginning of the Packet in the input register 110.

Let us return to Fig. 17. The byte stream of the data in the frequency band of the modulating signal in the MPEG from the block 84 is processed by the transport processor/decoder 86, which essentially performs the operations inverse to those performed by the transport processor 14 in the transmitter (Fig. 4). The transport processor 86 decodes the data by dividing them into components of konoeharuko, routers signal in accordance with information contained in the header decompression scheme signal of MPEG and other data processing units of image and sound, which generate signals formatted as needed for audio/video processor 88, shown in Fig. 17. Video and audio data recovered by the transport decoder 86, processed, respectively, the video and audio circuits block 88 with the formation of the image signals and sound, suitable for playback.

The detector 90 in the block 75 provides a signal Marker Field in block 92 management. Signal Marker Field prevents the controller 92 record segment sync field in block 84, a buffer, resulting in the output data stream loses synchronization components of the field. The data is output from the block buffer 84 form a single stream that does not contain the components of the synchronization field, resulting in a stream of byte data in the MPEG from the block 84 is characterized by a constant uniform velocity-distance data and constant uniform intervals between packets.

Remove auxiliary segment sync field without stopping or breaking the flow of data is picii packages they continuously read from the buffer 46 to the transport processor. During one period, the corresponding field data from the buffer 84 to the transport processor 86 will be given the same number of bytes, what is needed to make a data field. The buffer 84 is characterized by the same amount and requirements of its filling that buffer 46 in the transmitter. When the record in the buffer 84 is temporarily forbidden to remove from the data stream supporting information (e.g., signal synchronization field), the data packets continue to read in the transport processor 86 with a constant uniform speed. During this time, the buffer 84 is not emptied completely. A constant uniform gap between data packets provides a buffer 84 a sufficient time to partially emptied during the interval when the record it temporarily forbidden to remove from the data stream supporting information. Once during the interval when the record was banned, auxiliary information is deleted, the data is again written to the buffer 84. During this time, the transport processor 86 continuously received data packets from the buffer 84, resulting in the data stream flowed without interruption, and the transport processor 86 to process data without interruption.

In Fig. 22 illustrates the synchronization signal True Data generated by the circuit block 82 75 simultaneously with the data signal from the processor 75. Waveform Data corresponds to the True form of the data signal from the processor 75. The synchronization signal Data True has an uneven structure with uneven intervals between packets, including the period of 20 clock cycles corresponding to the data adjustment to osibova in the data signal to the synchronization signal field. Data packets in the data signal appear during 188 cycles during which the Data signal is a True positive. Thus, the data signal from the circuit 82 is characterized by an uneven flow data compared to the packet data. Similar shown in Fig. 22 signal Data True in the transmitter shown in Fig. 3 and 10.

In contrast, the signal of the True Data supplied from the block 84 of the buffer to the transport processor/decoder 86 (Fig. 23), has a uniform structure with uniform intervals between packets. The form of this signal indicates that the flow of data from the block buffer 84 has a constant uniform packet intervals (intervals deny, data length 125 periods of clock pulses 3/8 ST) between constant uniform data packets (intervals permissions "data" in length 188 periods of clock pulses 3/8 ARTICLE). Thus, for the transport processor 86 without interrupting the flow of the byte data in the MPEG standard is constant in a steady stream of data. In response to the signal Data is True, is shown in Fig. 23, the transport processor 86 during each interval of length 188 clock receives packets of data from the continuous is. 1 and 12.

Block 84 buffer/interface in the receiver is similar to the same block in the transmitter shown in Fig. 28. As noted above, the appropriate buffers FIFO type differ in the input clock pulse Reading and writing. In addition, while the system controller 44 of the transmitter of Fig. 28 in response to the Request Service Data Field, produces a signal Request Package For Transportation, the corresponding block in the receiver shown in Fig. 29, to indicate the beginning of a new packet is sent to the transport processor 86 flag the Start of a Batch. As in the case of buffer 46 in the transmitter buffer 100 in the receiver of Fig. 29 every time you reboot your system cleaned and loaded to a predetermined level. Before data is allowed to read, the buffer 100 must reach a predetermined level of "completion". This operation is illustrated in Fig. 24-27 and is similar to the corresponding operations in the transmitter described above in connection with Fig. 13-16.

The controller 120 generates Autonomous time intervals, is shown in Fig. 24 a dashed line. This signal has a uniform structure. More specifically, this signal consists of a regular uniform intervals to dliu constant uniform intervals of length 188 periods of clock pulses 3/8 ARTICLE (corresponding to intervals of the resolution of the data in the data packet). From this signal, the controller 120 generates the enable signal read from the buffer FIFO type (Fig. 25) for the buffer 100 and the Data signal is True (Fig. 27) for the transport processor 86, and both signals have a constant uniform structure. These signals are produced in response to a signal buffer (Fig. 26) and flag the Start of a Batch, fed to the input register 110. This flag is a buffered and delayed version of signal the Start of a Batch. Signal the Start of a Batch (detainee in register with output register 110 is fed to the control input unit 120 and the transport processor 86. The signal buffer is generated when the buffer 100 reaches a predetermined fill. Operation permissions read is triggered by leading edge of the first (positive) interval resolution of the data that appears after the signal Fill in the satisfaction conditions of the buffer is set to high level. Therefore, at time T2 the first byte (byte synchronization) packet of data is aligned with the beginning of the interval of the truthfulness of the data signal Data True (Fig. 27).

As the trigger and clock input read buffer 84 is synchronized pulses 3/8 ARTICLE, as explained above. Heartbeats 3/8 ARTICLE are also in the controller 120. Through triggers 110 and 112 signal byte data in the MPEG standard is fed to the input of the data transport processor 86, when the trigger is unlocked by permission signal read generated by the controller 120. Simultaneously, the controller 120 flag the Start of a Batch together with the signal Data True (Fig. 27) is fed to the transport processor 86. The signal Data is True is served in the transport processor 86 in order to permit him to accept data during those intervals when there are data packets.

The interface between the transport processor and the processor of the transmission containing the block 17, which is important for many applications. For example, in television broadcasting, when transmission is started, it is required that the processor has generated and issued field data without interruption. The operation of television receivers based on a continuous stream of data fields, including the field synchronization segments to ensure synchronization. Any change in the speed of the following data fields or patterns in the broadcasting process will lead to the breakdown of synchronization in the receiver. Usually the broadcasting Studio has several sets videomagician the VCRs issue of transport packets, containing information of a transport stream. Each recorder synchronizes its output signal with a data flow processor of the transmission, which cannot change the speed of the following data fields or structure fields. Uneven gaps in the flow of packets from the transport processor in the processor transfer will lead to the fact that the structure of the field passed to the data interface will distort the data stream that contains both the package and the structure of the data field. Each Studio VCR will require complex interfaces that have been able to synchronize the signals at the output of the tape recorder with the boundaries of a package, and fields. You will need to pass through the interface for additional information about the structure of the field or control data flow in the interface. The interface of the tape must contain a means for detecting the synchronization signal packet, detection fields and memory sufficient to store in the buffer structure of the data field. Additional difficulties arise in the case of pre-recorded sounds and insertion of local programming and advertising. These and other difficulties successfully removed by the system recording/playback ispolzuyutsya and receiver, is depicted in Fig. 4 and 17, respectively, with the difference that the system of Fig. 33 and 34 include a video capture device. In Fig. 33 tape device 15 recording/playback receives a stream of data with uniform velocity-distance data from the transport processor 14, and through the buffer/interface 16 outputs with uniform speed playback data in the encoder and the block 17 the formation of the field data. As in the case of the system depicted in Fig. 4, the system of Fig. 33 is characterized by the data flow in the interface between the transport layer and transport layer. In this example, the data source 12 contains a Studio video camera and the MPEG encoder for encoding the output signal of the camera to its packaging transport processor 14.

The device 15 may be a device for byte-by-byte write to the tape, commercially available, for example a VCR type PanasonicTMD3. In the design of some devices for recording can be enabled interface 16. The device 15 can be a one of the sets consisting of several devices for recording and widely used, as is well known in the broadcast studios to facilitate the transfer of Studio materials of various types.

going with uniform speed (with remote auxiliary information) from the interface/buffer 84, and generates playback data with uniform velocity-distance transport processor/decoder 86. The system shown in Fig. 34, also characterized by a uniform velocity of flow in the interface between the transport layer and transport layer. In this system, the device 85 record is a cassette recorder user is capable of recording from a broadcast or reproduce material, for example, pre-recorded using a device with characteristics similar to unit 15 in Fig. 33. Block 85 may be a separate unit in the system, where the elements 72, 75, 84 and 86 are embedded in a television receiver. Alternative elements 72, 75, 84 and 86 may be included in the device 85 entries.

1. System for transmitting digital data stream representing successive data fields, including equal intervals for data and unequal intervals for auxiliary information between data containing a data processor that generates a data stream with a constant uniform speed, video recorder/playback to receive the specified data flow with a uniform velocity from the specified processor of the data and the driver data field responsive to the output stream dnsdomainname intervals between the data of the specified data stream, without interruption of the data stream, the data stream having a structure of fields representing sequential data fields with equal intervals for data and unequal auxiliary intervals.

2. System for receiving the digital data stream representing sequential data field containing equal intervals for data and unequal intervals for auxiliary information between the data containing the data processor, responsive to the received data stream having a structure of fields, to remove the auxiliary information without interrupting it, means for transmitting the output data stream from the data processor to output a constant uniform speed, and video recorder/playback for receiving a data stream having a constant uniform speed, with the specified output.

3. The system under item 2, characterized in that said data stream is an MPEG-compatible.

4. The system under item 2, characterized in that it further comprises a data decoder, responsive to the output data stream from the video recorder/playback and running with a constant uniform data rate to generate an output decoder is ignal in the system for receiving the digital data stream, having a structure of fields representing sequential data field containing equal intervals for data and unequal intervals for auxiliary information between the data, according to which (a) remove the auxiliary information from the specified data stream without interruption to form a data flow with nonuniform velocity-distance data (b) transmit the specified data stream after the operation (a) in the recorder/playback with a constant uniform velocity-distance data.

6. The method according to p. 5, characterized in that it further (in) decode the output data from the specified device/ write /playback operation (b) with a constant uniform velocity-distance data.

7. The method according to p. 5, characterized in that said data stream is an MPEG-compatible.

8. System for transmitting digital data stream representing successive data fields, including equal intervals for data and unequal intervals for auxiliary information between data containing a data processor that generates a data stream with a constant uniform velocity-distance data, video recorder/playback for the data, responsive to the output data stream from the device recording/playback to insert auxiliary information in these unequal auxiliary intervals between the data of the specified data stream without interruption of the data stream, the data stream having a structure of fields representing sequential data fields with equal intervals for data and unequal intervals between the data, and a modulator, responsive to the specified data stream from the driver data fields for receiving the modulated signal with a partially suppressed sideband for transmission, the specified auxiliary information includes auxiliary information data and auxiliary information synchronization fields, occupying respectively the auxiliary intervals of unequal duration.

9. The system under item 8, wherein the specified data stream having a structure field contains a sequence of fields, each of which includes (a) a set of data segments, each of which includes the interval for data and auxiliary interval, and (b) the segment sync field containing the specified auxiliary timing information field, predshestvuyut the

 

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